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| v850es/kf1 tm , v850es/kg1 tm , v850es/kj1 tm 32-bit single-chip microcontrollers hardware printed in japan document no. u15862ej3v0ud00 (3rd edition) date published january 2003 n cp(k) user?s manual v850es/kf1: v850es/kg1: v850es/kj1: pd703208 pd703212 pd703216 pd703208(a) pd703212(a) pd703216(a) pd703208y pd703212y pd703216y pd703208y(a) pd703212y(a) pd703216y(a) pd703209 pd703213 pd703217 pd703209(a) pd703213(a) pd703217(a) pd703209y pd703213y pd703217y pd703209y(a) pd703213y(a) pd703217y(a) pd703210 pd703214 pd70f3217 pd703210(a) pd703214(a) pd70f3217(a) pd703210y pd703214y pd70f3217y pd703210y(a) pd703214y(a) pd70f3217y(a) pd70f3210 pd70f3214 pd70f3210(a) pd70f3214(a) pd70f3210y pd70f3214y pd70f3210y(a) pd70f3214y(a) 2002
user?s manual u15862ej3v0ud 2 [memo] user?s manual u15862ej3v0ud 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. purchase of nec electronics i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. v850 series, v850es/kf1, v850es/kg1, and v850es/kj1 are trademarks of nec electronics corporation. user ? s manual u15862ej3v0ud 4 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of november, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1 user ? s manual u15862ej3v0ud 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 fax: 6250-3583 j02.11 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 sucursal en espa ? a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 tyskland filial taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: user ? s manual u15862ej3v0ud 6 major revisions in this edition (1/2) pages description throughout ? addition of the following special quality grade products. pd703208(a), 703208y(a), 703209(a), 703209y(a), 703210(a), 703210y(a), 703212(a), 703212y(a), 703213(a), 703213y(a), 703214(a), 703214y(a), 703216(a), 703216y(a), 703217(a), 703217y(a), 70f3210(a), 70f3210y(a), 70f3214(a), 70f3214y(a), 70f3217(a), 70f3217y(a) p. 33 addition of caution in 1.2.4 pin configuration (top view) (v850es/kf1) p. 41 addition of caution in 1.3.4 pin configuration (top view) (v850es/kg1) p. 49 addition of caution in 1.4.4 pin configuration (top view) (v850es/kj1) p. 55 addition of description in chapter 2 pin functions and addition of table 2-1 pin i/o buffer power supplies pp.93, 95 modification of description on recommended connection of p70 to p77, p78 to p715, ic, v pp , and xt1 in 2.4 pin i/o circuits and recommended connection of unused pins p. 134 modification of description in 3.4.8 (2) access to special on-chip peripheral i/o registers p. 285 modification of description in 5.11 bus timing p. 291 addition of 5.12 cautions p. 292 addition of description on the main clock oscillator in 6.1 overview p. 293 addition of description in 6.2 (1) main clock oscillator p. 296 addition of caution 3 in 6.3 (1) processor clock control register (pcc) p. 302 addition of description in chapter 7 16-bit timer/ event counters 00 to 05 p. 306 modification of description of caution 4 in 7.2 (2) 16-bit timer capture/compare register 0n0 (cr0n0) p. 307 modification of description of caution 4 in 7.2 (3) 16-bit timer capture/compare register 0n1 (cr0n1) p. 311 modification of description of caution 1 in 7.3 (3) 16-bit timer output control register 0n (toc0n) p. 319 addition of setting procedures and modification of description in 7.4.1 operation as interval timer (16 bits) p. 322 addition of setting procedures in 7.4.2 ppg output operation p. 324 addition of figure 7-6 configuration of ppg output p. 325 addition of figure 7-7 ppg output operation timing p. 326 addition of setting procedures in 7.4.3 pulse width measurement p. 334 addition of setting procedures and addition of caution 2 in 7.4.4 operation as external event counter (16-bit timer/event counters 00, 01, 04 and 05 only) p. 337 addition of setting procedures and addition of caution in 7.4.5 square-wave output operation (16-bit timer/event counters 04 and 05 only) p. 340 addition of setting procedures in 7.4.6 one-shot pulse output operation p. 340 addition of caution 2 in 7.4.6 (1) one-shot pulse output with software trigger p. 342 addition of caution 2 in 7.4.6 (2) one-shot pulse output with external trigger p. 349 addition of caution in 7.4.7 (10) (b) when setting cr0n0, cr0n1 to compare mode p. 350 addition of description in chapter 8 8-bit timer/ event counters 50 and 51 p. 369 addition of description in chapter 9 8-bit timers h0 and h1 p. 373 addition of caution 3 in 9.3 (1) (a) 8-bit timer h mode register 0 (tmhmd0) p. 374 addition of caution 3 in 9.3 (1) (b) 8-bit timer h mode register 1 (tmhmd1) p. 386 addition of caution 2 in figure 9-7 transfer timing p. 388 addition of caution 4 in 9.4.3 (4) timing chart p. 427 addition of 13.4 relationship between analog input voltage and a/d conversion result user ? s manual u15862ej3v0ud 7 major revisions in this edition (2/2) pages description p. 430 addition of 13.6 (3) a/d converter sampling time and a/d conversion start delay time p. 432 addition of 13.7 how to read a/d converter characteristics table p. 441 addition of description in chapter 15 asynchronous serial interface (uart) p. 458 modification of description in figure 15-6 continuous transmission starting procedure p. 473 addition of description in chapter 16 clocked serial interface 0 (csi0) p. 501 modification of description in chapter 17 clocked serial interface a (csia) with automatic transmit/receive function p. 544 addition of description in chapter 18 i 2 c bus p. 682 addition of cautions in table 25-1 wiring between pd70f3210 and 70f3210y (v850es/kf1), and pg-fp3 p. 683 addition of figure 25-1 wiring example of v850es/kf1 flash writing adapter (fa-80gc-8bt, fa-80gk-9eu) p. 684 addition of cautions in table 25-2 wiring between pd70f3214 and 70f3214y (v850es/kg1), and pg-fp3 p. 685 addition of figure 25-2 wiring example of v850es/kg1 flash writing adapter (fa-100gc-8eu) p. 686 addition of cautions in table 25-3 wiring between pd70f3217 and 70f3217y (v850es/kj1), and pg-fp3 p. 687 addition of figure 25-3 wiring example of v850es/kj1 flash writing adapter (fa-144gj-uen) p. 699 addition of note 1 and description in absolute maximum ratings in chapter 26 electrical specifications p. 700 addition of description on storage temperature in absolute maximum ratings in chapter 26 electrical specifications p. 704 addition of (i) murata manufacturing co., ltd.: ceramic resonator (t a = ? ? ? ? 40 to +85 c) in chapter 26 electrical specifications p. 709 change of values of supply current (flash memory version) in dc characteristics in chapter 26 electrical specifications p. 710 change of values of supply current (mask rom version) in dc characteristics in chapter 26 electrical specifications p. 711 addition of caution and a timing chart in data retention characteristics in chapter 26 electrical specifications p. 715 addition of caution in bus timing (1) (a) clkout asynchronous: in multiplex bus mode (2/2) in chapter 26 electrical specifications p. 720 addition of caution 2 in bus timing (2) (a) read cycle (clkout asynchronous): in separate bus mode (1/2) in chapter 26 electrical specifications p. 721 addition of cautions in bus timing (2) (a) read cycle (clkout asynchronous): in separate bus mode (2/2) in chapter 26 electrical specifications p. 723 addition of caution 2 in bus timing (2) (c) write cycle (clkout asynchronous): in separate bus mode (1/2) in chapter 26 electrical specifications p. 724 addition of cautions in bus timing (2) (c) write cycle (clkout asynchronous): in separate bus mode (2/2) in chapter 26 electrical specifications p. 730 addition of description in basic operation in chapter 26 electrical specifications p. 739 addition of description in flash memory programming characteristics in chapter 26 electrical specifications p. 745 addition of chapter 28 recommended soldering conditions p. 755 addition of appendix b revision history the mark shows major revised points. user?s manual u15862ej3v0ud 8 preface readers this manual is intended for users who wish to understand the functions of the v850es/kf1, v850es/kg1, and v850es/kj1 and design application systems using these products. the target products are as follows. ? standard products: pd703208, 703208y, 703209, 703209y, 703210, 703210y, 703212, 703212y, 703213, 703213y, 703214, 703214y, 703216, 703216y, 703217, 703217y, 70f3210, 70f3210y, 70f3214, 70f3214y, 70f3217, 70f3217y ? special products: pd703208(a), 703208y(a), 703209(a), 703209y(a), 703210(a), 703210y(a), 703212(a), 703212y(a), 703213(a), 703213y(a), 703214(a), 703214y(a), 703216(a), 703216y(a), 703217(a), 703217y(a), 70f3210(a), 70f3210y(a), 70f3214(a), 70f3214y(a), 70f3217(a), 70f3217y(a) purpose this manual is intended to give users an understanding of the hardware functions of the v850es/kf1, v850es/kg1, and v850es/kj1 shown in the organization below. organization this manual is divided into two parts: hardware (this manual) and architecture ( v850es architecture user?s manual ). hardware architecture ? pin functions ? cpu function ? on-chip peripheral functions ? flash memory programming ? electrical specifications ? data types ? register set ? instruction format and instruction set ? interrupts and exceptions ? pipeline operation how to read this manual it is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. cautions 1. the application examples in this manual apply to ?standard? quality grade products for general electronic systems. when using an example in this manual for an application that requires a ?special? quality grade product, thoroughly evaluate the component and circuit to be actually used to see if they satisfy the special quality grade. 2. when using this manual as a manual for a special grade product, read the part numbers as follows. user?s manual u15862ej3v0ud 9 pd703208 pd703208(a) pd703214y pd703214y(a) pd703208y pd703208y(a) pd703216 pd703216(a) pd703209 pd703209(a) pd703216y pd703216y(a) pd703209y pd703209y(a) pd703217 pd703217(a) pd703210 pd703210(a) pd703217y pd703217y(a) pd703210y pd703210y(a) pd70f3210 pd70f3210(a) pd703212 pd703212(a) pd70f3210y pd70f3210y(a) pd703212y pd703212y(a) pd70f3214 pd70f3214(a) pd703213 pd703213(a) pd70f3214y pd70f3214y(a) pd703213y pd703213y(a) pd70f3217 pd70f3217(a) pd703214 pd703214(a) pd70f3217y pd70f3217y(a) to find the details of a register where the name is known refer to appendix a register index . to understand the details of an instruction function refer to the v850es architecture user?s manual . register format the name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. to understand the overall functions of the v850es/kf1, v850es/kg1, and v850es/kj1 read this manual according to the contents . to know the electrical specifications of the v850es/kf1, v850es/kg1, and v850es/kj1 refer to chapter 26 electrical specifications. conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (overscore over pin or signal name) memory map address: hi gher addresses on the top and lower addresses on the bottom note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 user?s manual u15862ej3v0ud 10 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850es/kf1, v850es/kg1, and v850es/kj1 document name document no. v850es architecture user?s manual u15943e v850es/kf1, v850es/kg1, v850es/kj1 hardware user?s manual this manual documents related to development tools (user?s manuals) document name document no. ie-v850es-g1 (in-circuit emulator) to be prepared ie-703217-g1-em1 (in-circuit emulator option board) to be prepared operation u16053e c language u16054e pm plus u16055e ca850 ver. 2.50 c compiler package assembly language u16042e id850 ver. 2.50 integrated debugger operation u16217e sm850 ver. 2.50 system simulator operation u15182e sm850 ver. 2.00 or later system simulator external part user open interface specifications u14873e fundamental u13430e installation u13410e rx850 ver. 3.13 or later real-time os technical u13431e fundamental u13773e installation u13774e rx850 pro ver. 3.15 real-time os technical u13772e rd850 ver. 3.01 task debugger u13737e rd850 pro ver. 3.01 task debugger u13916e az850 ver. 3.0 system performance analyzer u14410e pg-fp3 flash memory programmer u13502e pg-fp4 flash memory programmer u15260e user?s manual u15862ej3v0ud 11 contents chapter 1 introduction ...................................................................................................... ...........29 1.1 v850es/kf1, v850es/kg1, and v850es/kj1 product lineup ...............................................29 1.2 v850es/kf1 .................................................................................................................. ...............31 1.2.1 features (v850es/kf1) ..................................................................................................... ............31 1.2.2 applications (v850es/kf1) ................................................................................................. ...........32 1.2.3 ordering information (v850es/kf1)......................................................................................... ......32 1.2.4 pin configuration (top view) (v850es/kf1) ................................................................................. ...33 1.2.5 function block configuration (v850es/kf1)................................................................................. ..35 1.3 v850es/kg1.................................................................................................................. ...............39 1.3.1 features (v850es/kg1)..................................................................................................... ............39 1.3.2 applications (v850es/kg1) ................................................................................................. ..........40 1.3.3 ordering information (v850es/kg1) ......................................................................................... .....40 1.3.4 pin configuration (top view) (v850es/kg1)................................................................................. ...41 1.3.5 function block configuration (v850es/kg1) ................................................................................. .43 1.4 v850es/kj1 .................................................................................................................. ...............47 1.4.1 features (v850es/kj1)..................................................................................................... .............47 1.4.2 applications (v850es/kj1) ................................................................................................. ...........48 1.4.3 ordering information (v850es/kj1) ......................................................................................... ......48 1.4.4 pin configuration (top view) (v850es/kj1)................................................................................. ....49 1.4.5 function block configuration (v850es/kj1) ................................................................................. ..51 chapter 2 pin functions .................................................................................................... ............55 2.1 list of pin functions ....................................................................................................... ...........55 2.2 pin status.................................................................................................................. ...................64 2.3 description of pin functions ................................................................................................ .....66 2.3.1 v850es/kf1................................................................................................................ ...................66 2.3.2 v850es/kg1 ................................................................................................................ ..................74 2.3.3 v850es/kj1 ................................................................................................................ ...................83 2.4 pin i/o circuits and recommended connection of unused pins..........................................93 2.5 pin i/o circuits ............................................................................................................ ................96 chapter 3 cpu functions .................................................................................................... ..........98 3.1 features .................................................................................................................... ...................98 3.2 cpu register set ............................................................................................................ ............99 3.2.1 program register set ...................................................................................................... ...............100 3.2.2 system register set....................................................................................................... ................101 3.3 operation modes............................................................................................................. ..........107 3.4 address space ............................................................................................................... ...........108 3.4.1 cpu address space......................................................................................................... .............108 3.4.2 image ..................................................................................................................... ......................109 3.4.3 wraparound of cpu address space ........................................................................................... ..110 3.4.4 memory map................................................................................................................ .................111 3.4.5 areas ..................................................................................................................... .......................113 3.4.6 peripheral i/o registers.................................................................................................. ...............119 3.4.7 special registers ......................................................................................................... ..................131 3.4.8 cautions .................................................................................................................. .....................134 user?s manual u15862ej3v0ud 12 chapter 4 port functions ................................................................................................... .......137 4.1 features .................................................................................................................... ................ 137 4.1.1 v850es/kf1 ................................................................................................................ ................ 137 4.1.2 v850es/kg1 ................................................................................................................ ............... 137 4.1.3 v850es/kj1 ................................................................................................................ ................ 137 4.2 basic port configuration .................................................................................................... ..... 138 4.2.1 v850es/kf1 ................................................................................................................ ................ 138 4.2.2 v850es/kg1 ................................................................................................................ ............... 139 4.2.3 v850es/kj1 ................................................................................................................ ................ 140 4.3 port configuration.......................................................................................................... .......... 141 4.3.1 port 0 .................................................................................................................... ....................... 142 4.3.2 port 1 .................................................................................................................... ....................... 149 4.3.3 port 3 .................................................................................................................... ....................... 153 4.3.4 port 4 .................................................................................................................... ....................... 165 4.3.5 port 5 .................................................................................................................... ....................... 172 4.3.6 port 6 .................................................................................................................... ....................... 182 4.3.7 port 7 .................................................................................................................... ....................... 194 4.3.8 port 8 .................................................................................................................... ....................... 198 4.3.9 port 9 .................................................................................................................... ....................... 204 4.3.10 port cd .................................................................................................................. ...................... 223 4.3.11 port cm.................................................................................................................. ...................... 227 4.3.12 port cs .................................................................................................................. ...................... 234 4.3.13 port ct .................................................................................................................. ...................... 240 4.3.14 port dh .................................................................................................................. ...................... 246 4.3.15 port dl .................................................................................................................. ...................... 251 4.4 port function operation ..................................................................................................... ..... 262 4.4.1 write operation to i/o port ............................................................................................... ............ 262 4.4.2 read operation from i/o port .............................................................................................. ......... 262 4.4.3 arithmetic operation with i/o ports....................................................................................... ........ 262 chapter 5 bus control function ...........................................................................................2 63 5.1 features .................................................................................................................... ................ 263 5.2 bus control pins ............................................................................................................ .......... 263 5.2.1 pin status when internal rom, internal ram, or on-chip peripheral i/o is accessed................... 265 5.2.2 pin status in each operation mode......................................................................................... ...... 265 5.3 memory block function ....................................................................................................... ... 266 5.3.1 chip select control function.............................................................................................. ............ 269 5.4 external bus interface mode control function..................................................................... 269 5.5 bus access .................................................................................................................. ............. 270 5.5.1 number of clocks for access............................................................................................... ......... 270 5.5.2 bus size setting function ................................................................................................. ............. 270 5.5.3 access by bus size ........................................................................................................ .............. 271 5.6 wait function............................................................................................................... ............. 277 5.6.1 programmable wait function ................................................................................................ ........ 277 5.6.2 external wait function.................................................................................................... ............... 278 5.6.3 relationship between programmable wait and external wait ....................................................... 279 5.6.4 programmable address wait function........................................................................................ ... 280 5.7 idle state insertion function............................................................................................... .... 281 user?s manual u15862ej3v0ud 13 5.8 bus hold function ........................................................................................................... .........282 5.8.1 functional outline ........................................................................................................ .................282 5.8.2 bus hold procedure ........................................................................................................ ..............283 5.8.3 operation in power save mode.............................................................................................. .......283 5.9 bus priority................................................................................................................ ................284 5.10 boundary operation conditions .............................................................................................2 84 5.10.1 program space ............................................................................................................ .................284 5.10.2 data space ............................................................................................................... ....................284 5.11 bus timing................................................................................................................. ................285 5.12 cautions................................................................................................................... ..................291 chapter 6 clock generation function ...............................................................................292 6.1 overview .................................................................................................................... ................292 6.2 configuration............................................................................................................... ..............293 6.3 control registers ........................................................................................................... ...........295 6.4 operation ................................................................................................................... ................299 6.4.1 operation of each clock................................................................................................... .............299 6.4.2 clock output function ..................................................................................................... ...............299 6.4.3 external clock input function............................................................................................. ............299 6.5 pll function ................................................................................................................ .............300 6.5.1 overview .................................................................................................................. ....................300 6.5.2 control register .......................................................................................................... ...................300 6.5.3 usage ..................................................................................................................... ......................301 chapter 7 16-bit timer/event counters 00 to 05 ............................................................302 7.1 functions ................................................................................................................... ................302 7.2 configuration............................................................................................................... ..............303 7.3 control registers ........................................................................................................... ...........308 7.4 operation ................................................................................................................... ................319 7.4.1 operation as interval timer (16 bits)..................................................................................... .........319 7.4.2 ppg output operation ...................................................................................................... .............322 7.4.3 pulse width measurement ................................................................................................... .........326 7.4.4 operation as external event counter....................................................................................... ......334 7.4.5 square-wave output operation .............................................................................................. .......337 7.4.6 one-shot pulse output operation ........................................................................................... .......340 7.4.7 cautions .................................................................................................................. .....................345 chapter 8 8-bit timer/event counters 50 and 51 ...........................................................350 8.1 functions ................................................................................................................... ................350 8.2 configuration............................................................................................................... ..............351 8.3 control registers ........................................................................................................... ...........353 8.4 operation ................................................................................................................... ................356 8.4.1 operation as interval timer (8 bits)...................................................................................... ..........356 8.4.2 operation as external event counter (8 bits).............................................................................. ...358 8.4.3 square-wave output operation (8-bit resolution)........................................................................... 359 8.4.4 8-bit pwm output operation................................................................................................ ..........361 8.4.5 operation as interval timer (16 bits)..................................................................................... .........364 8.4.6 operation as external event counter (16 bits)............................................................................. ..366 8.4.7 square-wave output operation (16-bit resolution).........................................................................3 67 user?s manual u15862ej3v0ud 14 8.4.8 cautions .................................................................................................................. .................... 368 chapter 9 8-bit timers h0 and h1........................................................................................ ....369 9.1 functions ................................................................................................................... ............... 369 9.2 configuration............................................................................................................... ............. 369 9.3 control registers ........................................................................................................... .......... 372 9.4 operation ................................................................................................................... ............... 376 9.4.1 operation as interval timer............................................................................................... ............ 376 9.4.2 pwm pulse generator mode operation ........................................................................................ 379 9.4.3 carrier generator mode operation.......................................................................................... ...... 385 chapter 10 real-time output function (rto) ....................................................................392 10.1 function ................................................................................................................... ................. 392 10.2 configuration.............................................................................................................. .............. 393 10.3 rto control registers...................................................................................................... ....... 394 10.4 operation .................................................................................................................. ................ 396 10.5 usage...................................................................................................................... ................... 397 10.6 cautions ................................................................................................................... ................. 397 10.7 security function .......................................................................................................... ........... 398 chapter 11 watch timer functions........................................................................................40 0 11.1 functions .................................................................................................................. ................ 400 11.2 configuration.............................................................................................................. .............. 402 11.3 watch timer control registers .............................................................................................. 402 11.4 operation .................................................................................................................. ................ 404 11.4.1 operation as watch timer................................................................................................. ............ 404 11.4.2 operation as interval timer.............................................................................................. ............. 404 11.4.3 cautions ................................................................................................................. ..................... 405 11.5 prescaler 3 ................................................................................................................ ................ 406 11.5.1 control registers ........................................................................................................ .................. 406 11.5.2 generation of count clock ................................................................................................ ............ 407 chapter 12 watchdog timer functions ...............................................................................408 12.1 watchdog timer 1 ........................................................................................................... ......... 408 12.1.1 functions ................................................................................................................ ..................... 408 12.1.2 configuration ............................................................................................................ ................... 410 12.1.3 watchdog timer 1 control register ........................................................................................ ........ 410 12.1.4 operation ................................................................................................................ ..................... 413 12.2 watchdog timer 2 ........................................................................................................... ......... 416 12.2.1 functions ................................................................................................................ ..................... 416 12.2.2 configuration ............................................................................................................ ................... 417 12.2.3 watchdog timer 2 control register ........................................................................................ ........ 417 12.2.4 operation ................................................................................................................ ..................... 419 chapter 13 a/d converter ................................................................................................... .......420 13.1 function ................................................................................................................... ................. 420 13.2 configuration.............................................................................................................. .............. 421 13.3 control registers .......................................................................................................... ........... 423 13.4 relationship between analog input voltage and a/d conversion result ......................... 427 user?s manual u15862ej3v0ud 15 13.5 operation .................................................................................................................. .................428 13.5.1 basic operation.......................................................................................................... ...................428 13.5.2 conversion operation (software trigger mode) ............................................................................. 429 13.5.3 power fail monitoring function ........................................................................................... ...........429 13.6 cautions................................................................................................................... ..................430 13.7 how to read a/d converter characteristics table ...............................................................432 chapter 14 d/a converter ................................................................................................... .......436 14.1 functions .................................................................................................................. .................436 14.2 configuration.............................................................................................................. ...............437 14.3 d/a converter control register............................................................................................. ..437 14.4 operation .................................................................................................................. .................439 14.4.1 operation in normal mode ................................................................................................. ...........439 14.4.2 operation in real-time output mode ....................................................................................... .......439 14.4.3 cautions ................................................................................................................. ......................440 chapter 15 asynchronous serial interface (uart) .....................................................441 15.1 selecting uart2 or i 2 c1 mode ................................................................................................441 15.2 features ................................................................................................................... ..................442 15.3 configuration.............................................................................................................. ...............443 15.4 control registers .......................................................................................................... ............445 15.5 interrupt requests ......................................................................................................... ...........452 15.6 operation .................................................................................................................. .................453 15.6.1 data format.............................................................................................................. .....................453 15.6.2 transmit operation....................................................................................................... .................454 15.6.3 continuous transmission operation ........................................................................................ ......456 15.6.4 receive operation........................................................................................................ .................460 15.6.5 reception error.......................................................................................................... ...................461 15.6.6 parity types and corresponding operation ................................................................................. ...463 15.6.7 receive data noise filter ................................................................................................ ...............464 15.7 dedicated baud rate generator n (brgn).............................................................................465 15.7.1 baud rate generator n (brgn) configuration ............................................................................... .465 15.7.2 serial clock generation .................................................................................................. ...............466 15.7.3 baud rate setting example................................................................................................ ............469 15.7.4 allowable baud rate range during reception ............................................................................... ..470 15.7.5 transfer rate during continuous transmission............................................................................. ..472 15.8 cautions................................................................................................................... ..................472 chapter 16 clocked serial interface 0 (csi0).................................................................473 16.1 features ................................................................................................................... ..................473 16.2 configuration.............................................................................................................. ...............474 16.3 control registers .......................................................................................................... ............477 16.4 operation .................................................................................................................. .................485 16.4.1 single transfer mode ..................................................................................................... ...............485 16.4.2 repeat transfer mode..................................................................................................... ..............492 16.5 output pins................................................................................................................ ................500 chapter 17 clocked serial interface a (csia) with automatic transmit/receive function .................................................................................501 user?s manual u15862ej3v0ud 16 17.1 functions .................................................................................................................. ................ 501 17.2 configuration.............................................................................................................. .............. 502 17.3 control registers .......................................................................................................... ........... 504 17.4 operation .................................................................................................................. ................ 513 17.4.1 operation stop mode ...................................................................................................... ............. 513 17.4.2 3-wire serial i/o mode................................................................................................... ............... 513 17.4.3 3-wire serial i/o mode with automatic transmit/receive function .................................................. 521 chapter 18 i 2 c bus ......................................................................................................................... ..544 18.1 selecting uart2 or i 2 c1 mode................................................................................................ 544 18.2 features ................................................................................................................... ................. 545 18.3 configuration.............................................................................................................. .............. 548 18.4 control registers .......................................................................................................... ........... 550 18.5 functions .................................................................................................................. ................ 563 18.5.1 pin configuration ........................................................................................................ .................. 563 18.6 i 2 c bus definitions and control methods .............................................................................. 564 18.6.1 start condition.......................................................................................................... .................... 564 18.6.2 addresses................................................................................................................ .................... 565 18.6.3 transfer direction specification ......................................................................................... ........... 566 18.6.4 acknowledge signal (ack) ................................................................................................. ......... 567 18.6.5 stop condition ........................................................................................................... ................... 568 18.6.6 wait signal (wait)....................................................................................................... ................ 569 18.7 i 2 c interrupt requests (intiicn).............................................................................................. 571 18.7.1 master device operation .................................................................................................. ............ 571 18.7.2 slave device operation (when receiving slave address data (match with svan))........................ 574 18.7.3 slave device operation (when receiving extension code) ............................................................ 578 18.7.4 operation without communication.......................................................................................... ...... 582 18.7.5 arbitration loss operation (operation as slave after arbitration loss) ............................................ 582 18.7.6 operation when arbitration loss occurs (no communication after arbitration loss) ....................... 584 18.8 interrupt request (intiicn) generation timing and wait control ...................................... 589 18.9 address match detection method .......................................................................................... 590 18.10 error detection ........................................................................................................... .............. 590 18.11 extension code ............................................................................................................ ............ 590 18.12 arbitration ............................................................................................................... .................. 591 18.13 wakeup function ........................................................................................................... .......... 592 18.14 communication reservation ................................................................................................. . 593 18.15 cautions .................................................................................................................. .................. 596 18.16 communication operations .................................................................................................. .. 597 18.16.1 master operations ....................................................................................................... ................. 597 18.16.2 slave operation......................................................................................................... ................... 599 18.17 timing of data communication .............................................................................................. 600 chapter 19 interrupt/exception processing function................................................607 19.1 overview ................................................................................................................... ................ 607 19.1.1 features ................................................................................................................. ..................... 607 19.2 non-maskable interrupts .................................................................................................... ..... 614 19.2.1 operation ................................................................................................................ ..................... 617 19.2.2 restore .................................................................................................................. ...................... 618 19.2.3 np flag.................................................................................................................. ....................... 619 user?s manual u15862ej3v0ud 17 19.2.4 noise elimination for nmi pin............................................................................................ ............619 19.2.5 edge detection function for nmi pin...................................................................................... ........620 19.3 maskable interrupts ........................................................................................................ ..........622 19.3.1 operation................................................................................................................ ......................622 19.3.2 restore.................................................................................................................. .......................624 19.3.3 priorities of maskable interrupts ........................................................................................ ...........625 19.3.4 interrupt control register (xxlcn) ....................................................................................... ............629 19.3.5 interrupt mask registers 0 to 2 (imr0 to imr2)........................................................................... ..634 19.3.6 in-service priority register (ispr)...................................................................................... ............637 19.3.7 maskable interrupt status flag........................................................................................... ............638 19.3.8 watchdog timer mode register 1 (wdtm1) ..................................................................................6 39 19.3.9 elimination of noise from intp0 to intp6 ................................................................................. ...639 19.3.10 intp0 to intp6 edge detection function .................................................................................. ....640 19.4 software exceptions........................................................................................................ .........643 19.4.1 operation................................................................................................................ ......................643 19.4.2 restore.................................................................................................................. .......................644 19.4.3 exception status flag (ep) ............................................................................................... .............645 19.5 exception trap ............................................................................................................. .............646 19.5.1 illegal op code .......................................................................................................... ....................646 19.5.2 debug trap............................................................................................................... .....................648 19.6 multiple interrupt servicing control....................................................................................... .650 19.7 interrupt response time.................................................................................................... ......652 19.8 periods in which interrupts are not acknowledged by cpu ..............................................653 chapter 20 key interrupt function ......................................................................................654 20.1 function ................................................................................................................... ..................654 20.2 key interrupt control register ............................................................................................. ...655 chapter 21 standby function ................................................................................................ ...656 21.1 overview ................................................................................................................... .................656 21.2 halt mode .................................................................................................................. ..............659 21.2.1 setting and operation status............................................................................................. ............659 21.2.2 releasing halt mode ...................................................................................................... ...........659 21.3 idle mode.................................................................................................................. ................661 21.3.1 setting and operation status............................................................................................. ............661 21.3.2 releasing idle mode...................................................................................................... .............661 21.4 stop mode ................................................................................................................. ..................663 21.4.1 setting and operation status............................................................................................. ............663 21.4.2 releasing stop mode...................................................................................................... ...........663 21.5 securing oscillation stabilization time .................................................................................665 21.6 subclock operation mode.................................................................................................... ....666 21.6.1 setting and operation status............................................................................................. ............666 21.6.2 releasing subclock operation mode........................................................................................ .....666 21.7 sub-idle mode.............................................................................................................. ............668 21.7.1 setting and operation status............................................................................................. ............668 21.7.2 releasing sub-idle mode.................................................................................................. ..........668 21.8 control registers .......................................................................................................... ............670 chapter 22 reset function .................................................................................................. ......671 user?s manual u15862ej3v0ud 18 22.1 overview ................................................................................................................... ................ 671 22.2 configuration.............................................................................................................. .............. 671 22.3 operation .................................................................................................................. ................ 672 chapter 23 regulator ........................................................................................................ ..........675 23.1 overview ................................................................................................................... ................ 675 23.2 operation .................................................................................................................. ................ 675 chapter 24 rom correction function..................................................................................677 24.1 overview ................................................................................................................... ................ 677 24.2 control registers .......................................................................................................... ........... 678 24.2.1 correction address registers 0 to 3 (corad0 to corad3)........................................................ 678 24.2.2 correction control register (corcn) ...................................................................................... ..... 679 24.3 rom correction operation and program flow ..................................................................... 679 chapter 25 flash memory .................................................................................................... .......681 25.1 features ................................................................................................................... ................. 681 25.2 writing with flash programmer.............................................................................................. 682 25.3 programming environment.................................................................................................... . 688 25.4 communication mode......................................................................................................... ..... 688 25.5 pin processing ............................................................................................................. ............ 691 25.5.1 v pp pin ........................................................................................................................... .............. 691 25.5.2 serial interface pins .................................................................................................... ................. 692 25.5.3 reset pin ................................................................................................................ ................... 694 25.5.4 port pins ................................................................................................................ ...................... 694 25.5.5 other signal pins........................................................................................................ .................. 694 25.5.6 power supply ............................................................................................................. .................. 694 25.6 programming method ......................................................................................................... ..... 695 25.6.1 controlling flash memory ................................................................................................. ............ 695 25.6.2 flash memory programming mode ............................................................................................ .. 696 25.6.3 selecting communication mode ............................................................................................. ...... 696 25.6.4 communication commands ................................................................................................... ...... 697 25.6.5 resources used........................................................................................................... ................ 698 chapter 26 electrical specifications ..................................................................................699 chapter 27 package drawings ................................................................................................ .741 chapter 28 recommended soldering conditions ............................................................745 appendix a register index .................................................................................................. ........748 appendix b revision history ................................................................................................ ......755 user?s manual u15862ej3v0ud 19 list of figures (1/6) figure no. title page 3-1 cpu address space ........................................................................................................... ....................... 108 3-2 address space image......................................................................................................... ....................... 109 3-3 data memory map (physical addresses) ........................................................................................ ........... 111 3-4 program memory map .......................................................................................................... ..................... 112 3-5 internal rom/internal flash memory area (128 kb) ............................................................................ ..... 113 3-6 internal rom area (96 kb) ................................................................................................... ..................... 114 3-7 internal rom area (64 kb) ................................................................................................... ..................... 114 3-8 internal ram area (6 kb) .................................................................................................... ...................... 116 3-9 internal ram area (4 kb) .................................................................................................... ...................... 117 3-10 on-chip peripheral i/o area ................................................................................................ ...................... 118 4-1 block diagram of p00 and p01 ................................................................................................ .................. 147 4-2 block diagram of p02 to p06 ................................................................................................. .................... 148 4-3 block diagram of p10 and p11 ................................................................................................ .................. 152 4-4 block diagram of p30 ........................................................................................................ ........................ 160 4-5 block diagram of p31, p32, and p34.......................................................................................... ............... 161 4-6 block diagram of p33 and p35 ................................................................................................ .................. 162 4-7 block diagram of p36 and p37 ................................................................................................ .................. 163 4-8 block diagram of p38 and p39 ................................................................................................ .................. 164 4-9 block diagram of p40 ........................................................................................................ ........................ 169 4-10 block diagram of p41 ....................................................................................................... ......................... 170 4-11 block diagram of p42 ....................................................................................................... ......................... 171 4-12 block diagram of p50, p51, and p53......................................................................................... ................ 178 4-13 block diagram of p52 ....................................................................................................... ......................... 179 4-14 block diagram of p54 ....................................................................................................... ......................... 180 4-15 block diagram of p55 ....................................................................................................... ......................... 181 4-16 block diagram of p60 to p65, and p611...................................................................................... .............. 188 4-17 block diagram of p66, p69, p610, and p612 .................................................................................. .......... 189 4-18 block diagram of p67 ....................................................................................................... ......................... 190 4-19 block diagram of p68 ....................................................................................................... ......................... 191 4-20 block diagram of p613 ...................................................................................................... ........................ 192 4-21 block diagram of p614 and p615 ............................................................................................. ................. 193 4-22 block diagram of p70 to p715 ............................................................................................... .................... 197 4-23 block diagram of p80 ....................................................................................................... ......................... 202 4-24 block diagram of p81 ....................................................................................................... ......................... 203 4-25 block diagram of p90, p92, p94, and p96 .................................................................................... ............ 217 4-26 block diagram of p91 ....................................................................................................... ......................... 218 4-27 block diagram of p93, p95, p97, and p910 ................................................................................... ........... 219 4-28 block diagram of p98 and p911 .............................................................................................. .................. 220 4-29 block diagram of p99 and p912 .............................................................................................. .................. 221 4-30 block diagram of p913 to p915 .............................................................................................. ................... 222 4-31 block diagram of pcd0 to pcd3.............................................................................................. ................. 226 4-32 block diagram of pcm0 and pcm3............................................................................................. .............. 231 4-33 block diagram of pcm1 and pcm2............................................................................................. .............. 232 user?s manual u15862ej3v0ud 20 list of figures (2/6) figure no. title page 4-34 block diagram of pcm4 and pcm5 ............................................................................................. ..............233 4-35 block diagram of pcs0 to pcs3 .............................................................................................. .................238 4-36 block diagram of pcs4 to pcs7 .............................................................................................. .................239 4-37 block diagram of pct0, pct1, pct4, and pct6 ................................................................................ .....244 4-38 block diagram of pct2, pct3, pct5, and pct7 ................................................................................ .....245 4-39 block diagram of pdh0 to pdh7.............................................................................................. .................250 4-40 block diagram of pdl0 to pdl15 ............................................................................................. .................254 5-1 data memory map (v850es/kf1)................................................................................................ ..............266 5-2 data memory map (v850es/kg1) ................................................................................................ .............267 5-3 data memory map (v850es/kj1) ................................................................................................ ..............268 5-4 little endian address in word ............................................................................................... .....................271 5-5 example of inserting wait states ............................................................................................ ...................279 5-6 multiplex bus read timing (bus size: 16 bits, 16-bit access) ................................................................ ..285 5-7 multiplex bus read timing (bus size: 8 bits) ................................................................................ ............285 5-8 multiplex bus write timing (bus size: 16 bits, 16-bit access)............................................................... ....286 5-9 multiplex bus write timing (bus size: 8 bits) ............................................................................... .............286 5-10 multiplex bus hold timing (bus size: 16 bits, 16-bit access)............................................................... .....287 5-11 separate bus read timing (bus size: 16 bits, 16-bit access) ................................................................ ..288 5-12 separate bus read timing (bus size: 8 bits)................................................................................ ............288 5-13 separate bus write timing (bus size: 16 bits, 16-bit access) ............................................................... ...289 5-14 separate bus write timing (bus size: 8 bits) ............................................................................... .............289 5-15 separate bus hold timing (bus size: 8 bits, write)......................................................................... ..........290 5-16 address wait timing (separate bus read, bus size: 16 bits, 16-bit access)...........................................290 6-1 clock generator ............................................................................................................. ............................293 7-1 block diagram of 16-bit timer/event counter 0n.............................................................................. .........304 7-2 control register setting contents during interval timer operation ........................................................... 320 7-3 configuration of interval timer ............................................................................................. ......................320 7-4 timing of interval timer operation.......................................................................................... ...................321 7-5 control register settings in ppg output operation........................................................................... ........323 7-6 configuration of ppg output................................................................................................. .....................324 7-7 ppg output operation timing ................................................................................................. ..................325 7-8 control register settings for pulse width measurement with free-running counter and one capture register ....................................................................................................... ..................327 7-9 configuration for pulse width measurement with free-running counter ..................................................327 7-10 timing of pulse width measurement with free-running counter and one capture register (with both edges specified) .................................................................................................... ...................328 7-11 control register settings for measurement of two pulse widths with free-running counter ..................329 7-12 cr0n1 capture operation with rising edge specified ......................................................................... .....330 7-13 timing of pulse width measurement with free-running counter (with both edges specified).................330 7-14 control register settings for pulse width measurement with free-running counter and two capture registers...................................................................................................... ..................331 user?s manual u15862ej3v0ud 21 list of figures (3/6) figure no. title page 7-15 timing of pulse width measurement with free-running counter and two capture registers (with rising edge specified) ................................................................................................... ................... 332 7-16 control register settings for pulse width measurement by restarting ..................................................... 333 7-17 timing of pulse width measurement by restarting (with rising edge specified)...................................... 333 7-18 control register settings in external event counter mode ................................................................... .... 335 7-19 configuration of external event counter.................................................................................... ................ 336 7-20 timing of external event counter operation (with rising edge specified) ................................................ 336 7-21 control register settings in square-wave output mode....................................................................... .... 338 7-22 timing of square-wave output operation ..................................................................................... ............ 339 7-23 control register settings for one-shot pulse output with software trigger ............................................. 341 7-24 timing of one-shot pulse output operation with software trigger........................................................... 3 42 7-25 control register settings for one-shot pulse output with external trigger .............................................. 343 7-26 timing of one-shot pulse output operation with external trigger (with rising edge specified) .............. 344 7-27 start timing of 16-bit timer counter 0n .................................................................................... ................ 345 7-28 data hold timing of capture register ....................................................................................... ................ 345 7-29 operation timing of ovf0n flag ............................................................................................. .................. 347 8-1 block diagram of 8-bit timer/event counters 50 and 51....................................................................... .... 351 8-2 timing of interval timer operation.......................................................................................... ................... 356 8-3 timing of external event counter operation (with rising edge specified) ................................................ 358 8-4 timing of square-wave output operation ...................................................................................... ........... 360 8-5 timing of pwm output operation .............................................................................................. ................ 362 8-6 timing of operation based on cr5n register transitions ...................................................................... .. 363 8-7 cascade connection mode with 16-bit resolution .............................................................................. ...... 365 8-8 start timing of timer 5n.................................................................................................... ......................... 368 9-1 block diagram of 8-bit timers h0 and h1 ..................................................................................... ............ 370 9-2 register settings in interval timer mode .................................................................................... ............... 376 9-3 timing of interval timer operation.......................................................................................... ................... 377 9-4 register settings in pwm pulse generator mode ............................................................................... ...... 379 9-5 operation timing in pwm pulse generator mode ................................................................................ ..... 381 9-6 connection example of 8-bit timer hn and 8-bit timer/event counter 5n................................................ 385 9-7 transfer timing............................................................................................................. ............................. 386 9-8 register settings in carrier generator mode ................................................................................. ............ 387 9-9 carrier generator mode ...................................................................................................... ....................... 389 10-1 block diagram of rto ....................................................................................................... ........................ 392 10-2 example of operation timing of rto0 (when extr0 = 0, byte0 = 0) ................................................... 396 10-3 block diagram of security function ......................................................................................... .................. 398 11-1 block diagram of watch timer ............................................................................................... ................... 400 11-2 block diagram of prescaler 3............................................................................................... ...................... 401 11-3 operation timing of watch timer/interval timer ............................................................................. .......... 405 11-4 example of generation of watch timer interrupt request (intwt) (when interrupt period = 0.5 s)........ 405 user?s manual u15862ej3v0ud 22 list of figures (4/6) figure no. title page 12-1 block diagram of watchdog timer 1.......................................................................................... ................409 12-2 block diagram of watchdog timer 2.......................................................................................... ................416 13-1 block diagram of a/d converter ............................................................................................. ...................420 13-2 operation sequence ......................................................................................................... .........................424 13-3 relationship between analog input voltages and a/d conversion results...............................................427 13-4 power fail monitoring function (pfcm = 0) .................................................................................. ............429 13-5 timing of a/d converter sampling and a/d conversion start delay .........................................................430 13-6 overall error.............................................................................................................. .................................432 13-7 quantization error ......................................................................................................... .............................433 13-8 zero-scale error........................................................................................................... ..............................433 13-9 full-scale error ........................................................................................................... ...............................434 13-10 differential linearity error.............................................................................................. .............................434 13-11 integral linearity error.................................................................................................. ..............................435 13-12 sampling time ............................................................................................................. ..............................435 14-1 block diagram of d/a converter ............................................................................................. ...................436 15-1 selecting mode of uart2 or i 2 c1 ..............................................................................................................441 15-2 block diagram of asynchronous serial interface n ........................................................................... .........444 15-3 format of asynchronous serial interface transmit/receive data.............................................................. 453 15-4 asynchronous serial interface transmission completion interrupt timing ................................................455 15-5 continuous transmission processing flow.................................................................................... ............457 15-6 continuous transmission starting procedure ................................................................................. ...........458 15-7 continuous transmission end procedure ...................................................................................... ............459 15-8 asynchronous serial interface reception completion interrupt timing .....................................................461 15-9 when reception error interrupt is separated from intsrn interrupt (isrmn bit = 0)...............................462 15-10 when reception error interrupt is included in intsrn interrupt (isrmn bit = 1) ......................................462 15-11 noise filter circuit...................................................................................................... ................................464 15-12 timing of rxdn signal judged as noise ..................................................................................... ..............464 15-13 configuration of baud rate generator n (brgn)............................................................................. ..........465 15-14 allowable baud rate range during reception................................................................................ ..........470 15-15 transfer rate during continuous transmission .............................................................................. ..........472 16-1 block diagram of clocked serial interface .................................................................................. ...............476 16-2 timing chart in single transfer mode....................................................................................... .................486 16-3 timing chart according to clock phase selection ............................................................................ .........488 16-4 timing chart of interrupt request signal output in delay mode.............................................................. ..490 16-5 repeat transfer (receive-only) timing chart ................................................................................ ...........493 16-6 repeat transfer (transmission/reception) timing chart ...................................................................... ....495 16-7 timing chart of next transfer reservation period........................................................................... ..........496 16-8 transfer request clear and register access conflict ........................................................................ .......498 16-9 interrupt request and register access conflict............................................................................. ............499 user?s manual u15862ej3v0ud 23 list of figures (5/6) figure no. title page 17-1 block diagram of csian ..................................................................................................... ....................... 503 17-2 3-wire serial i/o mode timing.............................................................................................. ..................... 518 17-3 format of transmit/receive data ............................................................................................ .................. 519 17-4 transfer bit order switching circuit....................................................................................... .................... 520 17-5 automatic transmission/reception mode operation timings.................................................................... 529 17-6 automatic transmission/reception mode flowchart ............................................................................ ..... 530 17-7 internal buffer ram operation in 6-byte transmission/reception (in automatic transmission/reception mode)..................................................................................... ....... 531 17-8 automatic transmission mode operation timing ............................................................................... ....... 533 17-9 automatic transmission mode flowchart ...................................................................................... ............ 534 17-10 internal buffer ram operation in 6-byte transmission (in automatic transmission mode) ...................... 535 17-11 repeat transmission mode operation timing................................................................................. .......... 537 17-12 repeat transmission mode flowchart........................................................................................ ............... 538 17-13 internal buffer ram operation in 6-byte transmission (in repeat transmission mode)........................... 539 17-14 format of csian transmit/receive data ..................................................................................... .............. 541 17-15 automatic transmission/reception suspension and restart................................................................... .. 542 17-16 automatic data transmit/receive interval time ............................................................................. ........... 543 18-1 selecting mode of uart2 or i 2 c1.............................................................................................................. 544 18-2 block diagram of i 2 cn ............................................................................................................................. ... 546 18-3 serial bus configuration example using i 2 c bus....................................................................................... 547 18-4 pin configuration diagram .................................................................................................. ....................... 563 18-5 i 2 c bus?s serial data transfer timing............................................................................................ ............ 564 18-6 start conditions ........................................................................................................... .............................. 564 18-7 address.................................................................................................................... .................................. 562 18-8 transfer direction specification ........................................................................................... ...................... 566 18-9 ack signal................................................................................................................. ................................ 567 18-10 stop condition ............................................................................................................ ............................... 568 18-11 wait signal............................................................................................................... .................................. 569 18-12 arbitration timing example ................................................................................................ ........................ 591 18-13 communication reservation timing .......................................................................................... ................ 594 18-14 timing for accepting communication reservations........................................................................... ........ 594 18-15 communication reservation flowchart ....................................................................................... .............. 595 18-16 master operation flowchart (1) ............................................................................................ ..................... 597 18-17 master operation flowchart (2) ............................................................................................ ..................... 598 18-18 slave operation flowchart................................................................................................. ........................ 599 18-19 example of master to slave communication (when 9-clock wait is selected for both master and slave) ..................................................................... 6 01 18-20 example of slave to master communication (when 9-clock wait is selected for both master and slave) ..................................................................... 6 04 19-1 acknowledging non-maskable interrupt requests .............................................................................. ...... 615 19-2 non-maskable interrupt servicing........................................................................................... ................... 617 19-3 reti instruction processing................................................................................................ ....................... 618 user?s manual u15862ej3v0ud 24 list of figures (6/6) figure no. title page 19-4 maskable interrupt servicing............................................................................................... .......................623 19-5 reti instruction processing................................................................................................ .......................624 19-6 example of interrupt nesting............................................................................................... .......................626 19-7 example of servicing simultaneously generated interrupt requests ........................................................628 19-8 software exception processing.............................................................................................. ....................643 19-9 reti instruction processing................................................................................................ .......................644 19-10 exception trap processing ................................................................................................. .......................647 19-11 processing flow for restore from exception trap ........................................................................... ..........647 19-12 debug trap processing..................................................................................................... .........................648 19-13 processing flow for restore from debug trap ............................................................................... ...........649 19-14 pipeline operation during interrupt request acknowledgment (outline)...................................................652 20-1 key return block diagram ................................................................................................... ......................654 21-1 status transition .......................................................................................................... ..............................657 21-2 oscillation stabilization time ............................................................................................. ........................665 22-1 reset block diagram........................................................................................................ ..........................671 22-2 hardware status on reset input............................................................................................. .................674 22-3 operation on power application............................................................................................. ....................674 23-1 regulator.................................................................................................................. ..................................675 23-2 regc pin connection........................................................................................................ ........................676 24-1 block diagram of rom correction ............................................................................................ .................677 24-2 rom correction operation and program flow .................................................................................. ........680 25-1 wiring example of v850es/kf1 flash writing adapter (fa-80gc-8bt, fa-80gk-9eu) ..........................683 25-2 wiring example of v850es/kg1 flash writing adapter (fa-100gc-8eu) ................................................685 25-3 wiring example of v850es/kj1 flash writing adapter (fa-144gj-uen) .................................................687 25-4 environment for writing program to flash memory ............................................................................ .......688 25-5 communication with dedicated flash programmer (uart0) ....................................................................68 8 25-6 communication with dedicated flash programmer (csi00) ...................................................................... 689 25-7 communication with flash programmer (csi00+hs) ............................................................................. ...689 25-8 example of connection of v pp pin .............................................................................................................691 25-9 signal collision (input pin of serial interface) ........................................................................... .................692 25-10 malfunction of other device ............................................................................................... ........................693 25-11 signal collision (reset pin) .............................................................................................. .......................694 25-12 flash memory manipulation procedure....................................................................................... ...............695 25-13 flash memory programming mode ............................................................................................. ...............696 25-14 communication commands .................................................................................................... ...................697 user?s manual u15862ej3v0ud 25 list of tables (1/4) table no. title page 2-1 pin i/o buffer power supplies............................................................................................... ....................... 55 2-2 pin operation status in operation modes of v850es/kf1 ....................................................................... ... 64 2-3 pin operation status in operation modes of v850es/kg1 ....................................................................... .. 65 2-4 pin operation status in operation modes of v850es/kj1 ....................................................................... ... 65 3-1 program registers ........................................................................................................... .......................... 100 3-2 system register numbers ..................................................................................................... .................... 101 3-3 interrupt/exception table ................................................................................................... ........................ 115 4-1 port configuration (v850es/kf1) ............................................................................................. ................. 141 4-2 port configuration (v850es/kg1) ............................................................................................. ................ 141 4-3 port configuration (v850es/kj1) ............................................................................................. ................. 141 4-4 alternate-function pins of port 0 ........................................................................................... .................... 142 4-5 valid edge specification .................................................................................................... ........................ 146 4-6 alternate-function pins of port 1 (v850es/kg1, v850es/kj1) ................................................................ 14 9 4-7 alternate-function pins of port 3 (v850es/kf1) .............................................................................. ......... 154 4-8 alternate-function pins of port 3 (v850es/kg1, v850es/kj1) ................................................................ 15 4 4-9 alternate-function pins of port 4 ........................................................................................... .................... 165 4-10 alternate-function pins of port 5 .......................................................................................... ..................... 172 4-11 alternate-function pins of port 6 (v850es/kj1)............................................................................. ........... 182 4-12 alternate-function pins of port 7 (v850es/kf1, v850es/kg1) ................................................................ 1 94 4-13 alternate-function pins of port 7 (v850es/kj1)............................................................................. ........... 195 4-14 alternate-function pins of port 8 (v850es/kj1)............................................................................. ........... 198 4-15 alternate-function pins of port 9 (v850es/kf1) ............................................................................. .......... 205 4-16 alternate-function pins of port 9 (v850es/kg1, v850es/kj1) ................................................................ 2 05 4-17 valid edge specification ................................................................................................... ......................... 216 4-18 alternate-function pins of port cd (v850es/kj1) ............................................................................ ........ 223 4-19 alternate-function pins of port cm (v850es/kf1, v850es/kg1) ............................................................ 227 4-20 alternate-function pins of port cm (v850es/kj1) ............................................................................ ........ 227 4-21 alternate-function pins of port cs (v850es/kf1, v850es/kg1) ............................................................. 234 4-22 alternate-function pins of port cs (v850es/kj1)............................................................................ ......... 234 4-23 alternate-function pins of port ct (v850es/kf1, v850es/kg1) ............................................................. 240 4-24 alternate-function pins of port ct (v850es/kj1)............................................................................ ......... 240 4-25 alternate-function pins of port dh (v850es/kg1) ............................................................................ ....... 246 4-26 alternate-function pins of port dh (v850es/kj1) ............................................................................ ........ 246 4-27 alternate-function pins of port dl......................................................................................... .................... 251 4-28 settings when port pins are used for alternate functions ................................................................... .... 255 5-1 v850es/kf1 bus control pins................................................................................................. .................. 263 5-2 v850es/kg1 bus control pins ................................................................................................. ................. 264 5-3 v850es/kj1 bus control pins ................................................................................................. .................. 264 5-4 v850es/kg1 bus control pins ................................................................................................. ................. 264 5-5 v850es/kj1 bus control pins ................................................................................................. .................. 265 5-6 pin status when internal rom, internal ram, or on-chip peripheral i/o is accessed ............................ 265 user?s manual u15862ej3v0ud 26 list of tables (2/4) table no. title page 5-7 bus priority................................................................................................................ .................................284 6-1 operation status of each clock .............................................................................................. ...................299 7-1 configuration of 16-bit timer/event counters 00 to 05 ....................................................................... .......303 7-2 valid edge of ti0n0 pin and capture trigger of cr0n0 register ..............................................................3 05 7-3 valid edge of ti0n1 pin and capture trigger of cr0n0 register ..............................................................3 05 7-4 valid edge of ti0n0 pin and capture trigger of cr0n1 register ..............................................................3 07 8-1 configuration of 8-bit timer/event counters 50 and 51 ....................................................................... ......351 9-1 configuration of 8-bit timers h0 and h1..................................................................................... ...............369 10-1 configuration of rto ....................................................................................................... ..........................393 10-2 operation during manipulation of real-time output buffer registers n ....................................................393 10-3 operation modes and output triggers of real-time output port (n = 0)...................................................395 10-4 operation modes and output triggers of real-time output port (n = 1, v850es/kj1 only) .....................395 11-1 interval time of interval timer............................................................................................ ........................401 11-2 configuration of watch timer............................................................................................... ......................402 11-3 interval time of interval timer............................................................................................ ........................404 12-1 configuration of watchdog timer 1.......................................................................................... ..................410 12-2 program loop detection time of watchdog timer 1 ............................................................................ .....414 12-3 interval time of interval timer............................................................................................ ........................415 12-4 configuration of watchdog timer 2.......................................................................................... ..................417 12-5 watchdog timer 2 clock selection ........................................................................................... .................418 13-1 configuration of a/d converter ............................................................................................. .....................421 13-2 operation mode control ..................................................................................................... ........................424 13-3 a/d converter sampling time and a/d conversion start delay time (adm set value) ...........................431 14-1 configuration of d/a converter ............................................................................................. .....................437 15-1 generated interrupts and default priorities ................................................................................ ................452 15-2 reception error causes ..................................................................................................... ........................461 15-3 baud rate generator setting data ........................................................................................... .................469 15-4 maximum and minimum allowable baud rate error .............................................................................. ....471 16-1 sck0n pin output status.................................................................................................... .......................500 16-2 so0n pin output status ..................................................................................................... ........................500 17-1 configuration of csian..................................................................................................... ..........................502 17-2 relationship between buffer ram address values and adtp0 register setting values .........................509 user?s manual u15862ej3v0ud 27 list of tables (3/4) table no. title page 17-3 relationship between buffer ram address values and adtp1 register setting values ......................... 509 17-4 csia0 buffer ram ........................................................................................................... .......................... 511 17-5 csia1 buffer ram ........................................................................................................... .......................... 512 17-6 relationship between buffer ram address values and adtp0 register setting values ......................... 526 17-7 relationship between buffer ram address values and adtp1 register setting values ......................... 526 18-1 configuration of i 2 cn ............................................................................................................................. ..... 548 18-2 selection clock setting .................................................................................................... .......................... 562 18-3 intiicn generation timing and wait control................................................................................. ............ 589 18-4 extension code bit definitions............................................................................................. ...................... 591 18-5 status during arbitration and interrupt request generation timing .......................................................... 592 18-6 wait periods............................................................................................................... ................................ 593 19-1 interrupt source list (v850es/kf1)......................................................................................... .................. 608 19-2 interrupt source list (v850es/kg1) ......................................................................................... ................. 610 19-3 interrupt source list (v850es/kj1) ......................................................................................... .................. 612 19-4 nmi valid edge specification............................................................................................... ...................... 621 19-5 interrupt control registers (xxlcn) (v850es/kf1)........................................................................... .......... 630 19-6 interrupt control registers (xxlcn) (v850es/kg1) ........................................................................... ......... 631 19-7 interrupt control registers (xxlcn) (v850es/kj1) ........................................................................... .......... 632 19-8 intp0 to intp3 pins valid edge specification ............................................................................... ........... 641 19-9 intp4 to intp6 pins valid edge specification ............................................................................... ........... 642 20-1 assignment of key return detection pins .................................................................................... ............. 654 21-1 standby modes .............................................................................................................. ............................ 656 21-2 operation after releasing halt mode by interrupt request ................................................................... . 659 21-3 operation status in halt mode .............................................................................................. .................. 660 21-4 operation after releasing idle mode by interrupt request................................................................... ... 661 21-5 operation status in idle mode .............................................................................................. ................... 662 21-6 operation after releasing stop mode by interrupt request................................................................... . 663 21-7 operation status in stop mode.............................................................................................. .................. 664 21-8 operation status in subclock operation mode ................................................................................ .......... 667 21-9 operation after releasing sub-idle mode by interrupt request .............................................................. 6 68 21-10 operation status in sub-idle mode......................................................................................... ................. 669 22-1 hardware status on reset pin input or occurrence of wdtres2 ......................................................... 673 22-2 hardware status on occurrence of wdtres1 ................................................................................... ...... 673 24-1 correspondence between corcn register bits and coradn registers ............................................... 679 25-1 wiring between pd70f3210 and 70f3210y (v850es/kf1), and pg-fp3 ............................................. 682 25-2 wiring between pd70f3214 and 70f3214y (v850es/kg1), and pg-fp3............................................. 684 25-3 wiring between pd70f3217 and 70f3217y (v850es/kj1), and pg-fp3.............................................. 686 user?s manual u15862ej3v0ud 28 list of tables (4/4) table no. title page 25-4 signals generated by dedicated flash programmer (pg-fp3).................................................................69 0 25-5 pins used by each serial interface......................................................................................... ...................692 25-6 communication modes........................................................................................................ .......................696 25-7 flash memory control commands.............................................................................................. ...............697 25-8 response commands.......................................................................................................... ......................698 28-1 surface mounting type soldering conditions ................................................................................. ...........745 user?s manual u15862ej3v0ud 29 chapter 1 introduction 1.1 v850es/kf1, v850es/kg1, and v850es/kj1 product lineup pd70f3217y pd70f3217 flash memory: 128 kb, ram: 6 kb i 2 c bus version 144-pin plastic lqfp (fine pitch) (20 20) pd703217y pd703217 mask rom: 128 kb, ram: 6 kb i 2 c bus version pd703216y pd703216 mask rom: 96 kb, ram: 6 kb i 2 c bus version v850es/kj1 pd70f3214y pd70f3214 flash memory: 128 kb, ram: 6 kb i 2 c bus version 100-pin plastic lqfp (fine pitch) (14 14) pd703214y pd703214 mask rom: 128 kb, ram: 6 kb i 2 c bus version pd703213y pd703213 mask rom: 96 kb, ram: 4 kb i 2 c bus version pd703212y pd703212 mask rom: 64 kb, ram: 4 kb i 2 c bus version v850es/kg1 pd70f3210y pd70f3210 flash memory: 128 kb, ram: 6 kb i 2 c bus version 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) pd703210y pd703210 mask rom: 128 kb, ram: 6 kb i 2 c bus version pd703209y pd703209 mask rom: 96 kb, ram: 4 kb i 2 c bus version pd703208y pd703208 mask rom: 64 kb, ram: 4 kb i 2 c bus version v850es/kf1 chapter 1 introduction user ? s manual u15862ej3v0ud 30 differences between products timer serial interface function part no. 8-bit 16-bit tmh watch wdt csi csia uart i 2 c a/d d/a rto i/o other pd703208 ? pd703208y 1 ch pd703209 ? pd703209y 1 ch pd703210 ? pd703210y 1 ch pd70f3210 ? v850es/kf1 pd70f3210y 2 ch 2 ch 2 ch 1 ch 2 ch 2 ch 1 ch 2 ch 1 ch 8 ch ? 6 ch 67 ? pd703212 ? pd703212y 1 ch pd703213 ? pd703213y 1 ch pd703214 ? pd703214y 1 ch pd70f3214 ? v850es/kg1 pd70f3214y 2 ch 4 ch 2 ch 1 ch 2 ch 2 ch 2 ch 2 ch 1 ch 8 ch 2 ch 6 ch 84 ? pd703216 ? pd703216y 2 ch pd703217 ? pd703217y 2 ch pd70f3217 ? v850es/kj1 pd70f3217y 2 ch 6 ch 2 ch 1 ch 2 ch 3 ch 2 ch 3 ch 2 ch 16 ch 2 ch 12 ch 128 ? remark in this manual, the v850es/kf1, v850es/kg1, and v850es/kj1 product names are used as follows. ? mask rom versions v850es/kf1: pd703208, 703208y, 703209, 703209y, 703210, 703210y v850es/kg1: pd703212, 703212y, 703213, 703213y, 703214, 703214y v850es/kj1: pd703216, 703216y, 703217, 703217y ? flash memory versions v850es/kf1: pd70f3210, 70f3210y v850es/kg1: pd70f3214, 70f3214y v850es/kj1: pd70f3217, 70f3217y ? i 2 c bus versions v850es/kf1: pd703208y, 703209y, 703210y, 70f3210y v850es/kg1: pd703212y, 703213y, 703214y, 70f3214y v850es/kj1: pd703216y, 703217y, 70f3217y chapter 1 introduction user ? s manual u15862ej3v0ud 31 1.2 v850es/kf1 1.2.1 features (v850es/kf1) { number of instructions: 83 { minimum instruction execution time: 50 ns (operation at main clock (f xx ) = 20 mhz) { general-purpose registers: 32 bits 32 registers { instruction set: signed multiplication (16 16 32): 1 to 2 clocks (instructions without creating register hazards can be continuously executed in parallel) saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space: 64 mb of linear address space memory block division function: 2 mb, 64 kb (total of 2 blocks) { external bus interface 16-bit data bus { internal memory pd703208, 703208y (mask rom: 64 kb/ram: 4 kb) pd703209, 703209y (mask rom: 96 kb/ram: 4 kb) pd703210, 703210y (mask rom: 128 kb/ram: 6 kb) pd70f3210, 70f3210y (flash memory: 128 kb/ram: 6 kb) { interrupts and exceptions non-maskable interrupts: 3 sources maskable interrupts: 30 sources ( pd703208, 703209, 703210, 70f3210) 31 sources ( pd703208y, 703209y, 703210y, 70f3210y) software exceptions: 32 sources exception trap: 1 source { i/o lines: total: 67 { key interrupt function { timer/counter 16-bit timer/event counter: 2 channels 8-bit timer/event counter: 2 channels 8-bit timer h: 2 channels { watch timer: 1 channel { watchdog timers watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel watchdog timer 2: 1 channel { serial interface (sio) asynchronous serial interface (uart): 2 channels 3-wire serial i/o (csi0): 2 channels 3-wire serial i/o (with automatic transmit/receive function) (csia): 1 channel i 2 c bus interface (i 2 c): 1 channel ( pd703208y, 703209y, 703210y, 70f3210y) { a/d converter: 10-bit resolution 8 channels { real-time output port: 6 bits 1 channel { power-save functions: halt/idle/stop modes, subclock/sub-idle modes chapter 1 introduction user ? s manual u15862ej3v0ud 32 { rom correction: 4 correction addresses specifiable { packages: 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) 1.2.2 applications (v850es/kf1) audio equipment, etc. 1.2.3 ordering information (v850es/kf1) part number package quality grade pd703208gc- -8bt pd703208ygc- -8bt pd703208gk- -9eu pd703208ygk- -9eu pd703209gc- -8bt pd703209ygc- -8bt pd703209gk- -9eu pd703209ygk- -9eu pd703210gc- -8bt pd703210ygc- -8bt pd703210gk- -9eu pd703210ygk- -9eu pd70f3210gc-8bt pd70f3210ygc-8bt pd70f3210gk-9eu pd70f3210ygk-9eu pd703208gc(a)- -8bt note pd703208ygc(a)- -8bt note pd703208gk(a)- -9eu note pd703208ygk(a)- -9eu note pd703209gc(a)- -8bt note pd703209ygc(a)- -8bt note pd703209gk(a)- -9eu note pd703209ygk(a)- -9eu note pd703210gc(a)- -8bt note pd703210ygc(a)- -8bt note pd703210gk(a)- -9eu note pd703210ygk(a)- -9eu note pd70f3210gc(a)-8bt note pd70f3210ygc(a)-8bt note pd70f3210gk(a)-9eu note pd70f3210ygk(a)-9eu note 80-pin plastic qfp (14 14) 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic qfp (14 14) 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic qfp (14 14) 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic qfp (14 14) 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic qfp (14 14) 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic qfp (14 14) 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic qfp (14 14) 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic qfp (14 14) 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) 80-pin plastic tqfp (fine pitch) (12 12) standard standard standard standard standard standard standard standard standard standard standard standard standard standard standard standard special special special special special special special special special special special special special special special special note under development remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. chapter 1 introduction user ? s manual u15862ej3v0ud 33 1.2.4 pin configuration (top view) (v850es/kf1) 80-pin plastic qfp (14 14) 80-pin plastic tqfp (fine pitch) (12 12) pd703208gc- -8bt pd703209gk- -9eu pd70f3210gc-8bt pd703208ygc- -8bt pd703209ygk- -9eu pd70f3210ygc-8bt pd703208gk- -9eu pd703210gc- -8bt pd70f3210gk-9eu pd703208ygk- -9eu pd703210ygc- -8bt pd70f3210ygk-9eu pd703209gc- -8bt pd703210gk- -9eu pd703208gc(a)- -8bt pd703209ygc- -8bt pd703210ygk- -9eu pd703208ygc(a)- -8bt pd703208gk(a)- -9eu pd703210gc(a)- -8bt pd70f3210gk(a)-9eu pd703208ygk(a)- -9eu pd703210ygc(a)- -8bt pd70f3210ygk(a)-9eu pd703209gc(a)- -8bt pd703210gk(a)- -9eu pd703209ygc(a)- -8bt pd703210ygk(a)- -9eu pd703209gk(a)- -9eu pd70f3210gc(a)-8bt pd703209ygk(a)- -9eu pd70f3210ygc(a)-8bt 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 av ref0 av ss p00/toh0 p01/toh1 p02/nmi p03/intp0 p04/intp1 v pp note 1 /ic note 1 v dd regc v ss x1 x2 reset xt1 xt2 p05/intp2 p06/intp3 p40/si00 p41/so00 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 pct6/astb pct4/rd pct1/wr1 pct0/wr0 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pcs1/cs1 pcs0/cs0 p915/intp6 p914/intp5 p913/intp4 p99/sck01 p98/so01 p97/si01 p42/sck00 p30/txd0 p31/rxd0 p32/asck0 p33/ti000/to00 p34/ti001 p35/ti010/to01 p38/sda0 note 2 p39/scl0 note 2 ev ss ev dd p50/ti011/rtp00/kr0 p51/ti50/rtp01/kr1 p52/to50/rtp02/kr2 p53/sia0/rtp03/kr3 p54/soa0/rtp04/kr4 p55/scka0/rtp05/kr5 p90/txd1/kr6 p91/rxd1/kr7 p96/ti51/to51 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5 pdl4/ad4 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 notes 1. ic: connect directly to v ss ( pd703208, 703208y, 703209, 703209y, 703210, 703210y). v pp : connect to v ss in normal operation mode ( pd70f3210, 70f3210y). 2. scl0 and sda0 can be used only for the pd703208y, 703209y, 703210y, and 70f3210y. caution make ev dd the same potential as v dd . chapter 1 introduction user ? s manual u15862ej3v0ud 34 pin identification (v850es/kf1) ad0 to ad15: ani0 to ani7: asck0: astb: av ref0 : av ss : clkout: cs0, cs1: ev dd : ev ss : hldak: hldrq: ic: intp0 to intp6: kr0 to kr7: nmi: p00 to p06: p30 to p35, p38, p39: p40 to p42: p50 to p55: p70 to p77: p90, p91, p96 to p99,: p913 to p915 pcm0 to pcm3: pcs0, pcs1: pct0, pct1, pct4, pct6: pdl0 to pdl15: address/data bus analog input asynchronous serial clock address strobe analog reference voltage ground for analog clock output chip select power supply for port ground for port hold acknowledge hold request internally connected interrupt request from peripherals key return non-maskable interrupt request port 0 port 3 port 4 port 5 port 7 port 9 port cm port cs port ct port dl rd: regc: reset: rtp00 to rtp05: rxd0, rxd1: sck00, sck01, scka0: scl0: sda0: si00, si01, sia0: so00, so01, soa0: ti000, ti001, ti010, ti011, ti50, ti51: to00, to01, to50, to51, toh0, toh1: txd0, txd1: v dd : v pp : v ss : wait: wr0: wr1: x1, x2: xt1, xt2: read strobe regulator control reset real-time output port receive data serial clock serial clock serial data serial input serial output timer input timer output transmit data power supply programming power supply ground wait lower byte write strobe upper byte write strobe crystal for main clock crystal for subclock chapter 1 introduction user ? s manual u15862ej3v0ud 35 1.2.5 function block configuration (v850es/kf1) (1) internal block diagram nmi to00, to01 sio ti000, ti001,ti010, ti011 so00, so01 si00, si01 sck00, sck01 intp0 to intp6 intc 16-bit timer/event counter: 2 ch to50, to51 ti50, ti51 8-bit timer/event counter: 2 ch toh0, toh1 txd0, txd1 rxd0, rxd1 asck0 rtp00 to rtp05 kr0 to kr7 uart : 2 ch csia : 1 ch rtp: 1 ch sda0 note 3 scl0 note 3 i 2 c note 3 : 1 ch watchdog timer key interrupt function regulator watch timer note 1 note 2 ram rom pc general-purpose registers 32 bits 32 multiplier 16 16 32 alu system registers 32-bit barrel shifter cpu hldrq hldak astb rd wait wr0, wr1 cs0, cs1 ad0 to ad15 ports cg a/d converter pdl0 to pdl15 pct0, pct1, pct4, pct6 pcs0, pcs1 pcm0 to pcm3 p90, p91, p96 to p99, p913 to p915 p70 to p77 p50 to p55 p40 to p42 p30 to p35, p38, p39 p00 to p06 regc av ref0 av ss ani0 to ani7 clkout x1 x2 xt1 xt2 reset v dd ic note 4 ev dd ev ss v pp note 5 v ss instruction queue bcu soa0 sia0 scka0 csi0: 2 ch 8-bit timer h: 2 ch rom correction notes 1. pd703208, 703208y: 64 kb (mask rom) pd703209, 703209y: 96 kb (mask rom) pd703210, 703210y: 128 kb (mask rom) pd70f3210, 70f3210y: 128 kb (flash memory) 2. pd703208, 703208y, 703209, 703209y: 4 kb pd703210, 703210y, 70f3210, 70f3210y: 6 kb 3. only for the pd703208y, 703209y, 703210y, and 70f3210y 4. only for the pd703208, 703208y, 703209, 703209y, 703210, and 703210y 5. only for the pd70f3210 and 70f3210y chapter 1 introduction user ? s manual u15862ej3v0ud 36 (2) internal units (a) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate processing of complex instructions. (b) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory space and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the prefetched instruction code is stored in an internal instruction queue. (c) rom this consists of a 128 kb, 96 kb, or 64 kb mask rom or flash memory mapped to the address spaces from 0000000h to 001ffffh, 0000000h to 0017fffh, or 0000000h to 000ffffh, respectively. rom can be accessed by the cpu in one clock cycle during instruction fetch. (d) ram this consists of a 6 kb or 4 kb ram mapped to the address spaces from 3ffd800h to 3ffefffh or 3ffe000h to 3ffefffh, respectively. ram can be accessed by the cpu in one clock cycle during data access. (e) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0 to intp6) from on-chip peripheral hardware and external hardware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. (f) clock generator (cg) the clock generator includes two types of oscillators: one for the main clock (f xx ) and one for the subclock (f xt ). it generates seven types of clocks (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, and f xt ), and supplies one of them as the operating clock for the cpu (f cpu ). (g) timer/counter two 16-bit timer/event counter channels and two 8-bit timer/event counter channels are incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. two 8-bit timer/event counters can be connected in cascade to configure a 16-bit timer. two 8-bit timer h channels are provided on chip. (h) watch timer this timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 khz) or f brg (32.768 khz) from the clock generator. at the same time, the watch timer can be used as an interval timer. chapter 1 introduction user ? s manual u15862ej3v0ud 37 (i) watchdog timer two watchdog timer channels are provided on chip to detect program loops and system abnormalities. watchdog timer 1 can be used as an interval timer. when used as a watchdog timer, it generates a non- maskable interrupt request signal (intwdt1) or system reset signal (wdtres1) after an overflow occurs. when used as an interval timer, it generates a maskable interrupt request (intwdtm1) after an overflow occurs. watchdog timer 2 operates by default following reset release. it generates a non-maskable interrupt request signal (intwdt2) or system reset signal (wdtres2) after an overflow occurs. (j) serial interface (sio) the v850es/kf1 includes four kinds of serial interfaces: an asynchronous serial interface (uartn), a clocked serial interface (csi0n), a clocked serial interface (with an automatic transmit/receive function) (csia0), and an i 2 c bus interface (i 2 c0). the pd703208, 703209, 703210, and 70f3210 can simultaneously use up to five channels, and the pd703208y, 703209y, 703210y, and 70f3210y up to six channels. for uartn, data is transferred via the txdn and rxdn pins. for csi0n, data is transferred via the so0n, si0n, and sck0n pins. for csia0, data is transferred via the soa0, sia0, and scka0 pins. for i 2 c0, data is transferred via the sda0 and scl0 pins. i 2 c0 is provided only for the pd703208y, 703209y, 703210y, and 70f3210y. for uart, a dedicated baud rate generator is provided on chip. remark n = 0, 1 (k) a/d converter this high-speed, high-resolution 10-bit a/d converter includes 8 analog input pins. conversion is performed using the successive approximation method. (l) rom correction this function is used to replace part of a program in the mask rom with that contained in the internal ram. up to four correction addresses can be specified. (m) key interrupt function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the eight key input pins. (n) real-time output function this function transfers 6-bit data set beforehand to output latches upon occurrence of an external trigger signal or a timer compare register match signal. for the v850es/kf1, a 1-channel 6-bit data real-time output function is provided on chip. chapter 1 introduction user ? s manual u15862ej3v0ud 38 (o) ports as shown below, the following ports have general-purpose port functions and control pin functions. port i/o port function control function p0 7-bit i/o nmi, external interrupt, timer output p3 8-bit i/o serial interface, timer i/o p4 3-bit i/o serial interface p5 6-bit i/o serial interface, timer i/o, key interrupt function, real-time output function p7 8-bit input a/d converter analog input p9 9-bit i/o serial interface, timer output, external interrupt, key interrupt function pcm 4-bit i/o external bus interface pcs 2-bit i/o chip select output pct 4-bit i/o external bus interface pdl 16-bit i/o general-purpose port external address/data bus chapter 1 introduction user ? s manual u15862ej3v0ud 39 1.3 v850es/kg1 1.3.1 features (v850es/kg1) { number of instructions: 83 { minimum instruction execution time: 50 ns (operation at main clock (f xx ) = 20 mhz) { general-purpose registers: 32 bits 32 registers { instruction set: signed multiplication (16 16 32): 1 to 2 clocks (instructions without creating register hazards can be continuously executed in parallel) saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space: 64 mb of linear address space memory block division function: 2 mb, 2 mb (total of 2 blocks) { external bus interface 16-bit data bus address bus: separate output possible { internal memory pd703212, 703212y (mask rom: 64 kb/ram: 4 kb) pd703213, 703213y (mask rom: 96 kb/ram: 4 kb) pd703214, 703214y (mask rom: 128 kb/ram: 6 kb) pd70f3214, 70f3214y (flash memory: 128 kb/ram: 6 kb) { interrupts and exceptions non-maskable interrupts: 3 sources maskable interrupts: 35 sources ( pd703212, 703213, 703214, 70f3214) 36 sources ( pd703212y, 703213y, 703214y, 70f3214y) software exceptions: 32 sources exception trap: 1 source { i/o lines: total: 84 { key interrupt function { timer/counter 16-bit timer/event counter: 4 channels 8-bit timer/event counter: 2 channels 8-bit timer h: 2 channels { watch timer: 1 channel { watchdog timers watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel watchdog timer 2: 1 channel { serial interface (sio) asynchronous serial interface (uart): 2 channels 3-wire serial i/o (csi0): 2 channels 3-wire serial i/o (with automatic transmit/receive function) (csia): 2 channels i 2 c bus interface (i 2 c): 1 channel ( pd703212y, 703213y, 703214y, 70f3214y) { a/d converter: 10-bit resolution 8 channels { d/a converter: 8-bit resolution 2 channels { real-time output port: 6 bits 1 channel { power-save functions: halt/idle/stop modes, subclock/sub-idle modes chapter 1 introduction user ? s manual u15862ej3v0ud 40 { rom correction: 4 correction addresses specifiable { packages: 100-pin plastic lqfp (fine pitch) (14 14) 1.3.2 applications (v850es/kg1) audio equipment, etc. 1.3.3 ordering information (v850es/kg1) part number package quality grade pd703212gc- -8eu pd703212ygc- -8eu pd703213gc- -8eu pd703213ygc- -8eu pd703214gc- -8eu pd703214ygc- -8eu pd70f3214gc-8eu pd70f3214ygc-8eu pd703212gc(a)- -8eu note pd703212ygc(a)- -8eu note pd703213gc(a)- -8eu note pd703213ygc(a)- -8eu note pd703214gc(a)- -8eu note pd703214ygc(a)- -8eu note pd70f3214gc(a)-8eu note pd70f3214ygc(a)-8eu note 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) standard standard standard standard standard standard standard standard special special special special special special special special note under development remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. chapter 1 introduction user ? s manual u15862ej3v0ud 41 1.3.4 pin configuration (top view) (v850es/kg1) 100-pin plastic lqfp (fine pitch) (14 14) pd703212gc- -8eu pd703214gc- -8eu pd703212ygc- -8eu pd703214ygc- -8eu pd703213gc- -8eu pd70f3214gc-8eu pd703213ygc- -8eu pd70f3214ygc-8eu pd703212gc(a)- -8eu pd703214gc(a)- -8eu pd703212ygc(a)- -8eu pd703214ygc(a)- -8eu pd703213gc(a)- -8eu pd70f3214gc(a)-8eu pd703213ygc(a)- -8eu pd70f3214ygc(a)-8eu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 pdh5/a21 pdh4/a20 pdh3/a19 pdh2/a18 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p31/rxd0 p32/asck0 p33/ti000/to00 p34/ti001 p35/ti010/to01 p36 p37 ev ss ev dd p38/sda0 note 2 p39/scl0 note 2 p50/ti011/rtp00/kr0 p51/ti50/rtp01/kr1 p52/to50/rtp02/kr2 p53/sia0/rtp03/kr3 p54/soa0/rtp04/kr4 p55/scka0/rtp05/kr5 p90/a0/txd1/kr6 p91/a1/rxd1/kr7 p92/a2/ti020/to02 p93/a3/ti021 p94/a4/ti030/to03 p95/a5/ti031 p96/a6/ti51/to51 p97/a7/si01 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 av ref0 av ss p10/ano0 p11/ano1 av ref1 p00/toh0 p01/toh1 v pp note 1 /ic note 1 v dd regc v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0 p04/intp1 p05/intp2 p06/intp3 p40/si00 p41/so00 p42/sck00 p30/txd0 pdl4/ad4 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 bv dd bv ss pct6/astb pct4/rd pct1/wr1 pct0/wr0 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pcs1/cs1 pcs0/cs0 p915/a15/intp6 p914/a14/intp5 p913/a13/intp4 p912/a12/scka1 p911/a11/soa1 p910/a10/sia1 p99/a9/sck01 p98/a8/so01 notes 1. ic: connect directly to v ss ( pd703212, 703212y, 703213, 703213y, 703214, 703214y). v pp : connect to v ss in normal operation mode ( pd70f3214, 70f3214y). 2. scl0 and sda0 can be used only for the pd703212y, 703213y, 703214y, and 70f3214y. caution make ev dd the same potential as v dd . bv dd can be used when v dd = ev dd bv dd . chapter 1 introduction user ? s manual u15862ej3v0ud 42 pin identification (v850es/kg1) a0 to a21: ad0 to ad15: ani0 to ani7: ano0, ano1: asck0: astb: av ref0 , av ref1 : av ss : bv dd : bv ss : clkout: cs0, cs1: ev dd : ev ss : hldak: hldrq: ic: intp0 to intp6: kr0 to kr7: nmi: p00 to p06: p10, p11: p30 to p39: p40 to p42: p50 to p55: p70 to p77: p90 to p915: pcm0 to pcm3: pcs0, pcs1: pct0, pct1, pct4, pct6: pdh0 to pdh5: pdl0 to pdl15: address bus address/data bus analog input analog output asynchronous serial clock address strobe analog reference voltage ground for analog power supply for bus interface ground for bus interface clock output chip select power supply for port ground for port hold acknowledge hold request internally connected interrupt request from peripherals key return non-maskable interrupt request port 0 port 1 port 3 port 4 port 5 port 7 port 9 port cm port cs port ct port dh port dl rd: regc: reset: rtp00 to rtp05: rxd0, rxd1: sck00, sck01, scka0, scka1: scl0: sda0: si00, si01, sia0, sia1: so00, so01, soa0, soa1: ti000, ti001, ti010, ti011, ti020, ti021, ti030, ti031, ti50, ti51: to00 to to03, to50, to51, toh0, toh1: txd0, txd1: v dd : v pp : v ss : wait: wr0: wr1: x1, x2: xt1, xt2: read strobe regulator control reset real-time output port receive data serial clock serial clock serial data serial input serial output timer input timer output transmit data power supply programming power supply ground wait lower byte write strobe upper byte write strobe crystal for main clock crystal for subclock chapter 1 introduction user ? s manual u15862ej3v0ud 43 1.3.5 function block configuration (v850es/kg1) (1) internal block diagram nmi to00 to to03 sio ti000, ti001, ti010, ti011, ti020, ti021, ti030, ti031 so00, so01 si00, si01 sck00, sck01 intp0 to intp6 intc 16-bit timer/event counter: 4 ch to50, to51 ti50, ti51 8-bit timer/event counter: 2 ch toh0, toh1 txd0, txd1 rxd0, rxd1 asck0 rtp00 to rtp05 kr0 to kr7 uart : 2 ch csia : 2 ch rtp : 1 ch sda0 note 3 scl0 note 3 i 2 c note 3 : 1 ch watchdog timer key interrupt function regulator watch timer note 1 note 2 ram rom pc general-purpose registers 32 bits 32 multiplier 16 16 32 alu system registers 32-bit barrel shifter cpu hldrq hldak astb rd wait wr0, wr1 cs0, cs1 a0 to a21 ad0 to ad15 ports cg a/d converter d/a converter pdl0 to pdl15 pdh0 to pdh5 pct0, pct1, pct4, pct6 pcs0, pcs1 pcm0 to pcm3 p90 to p915 p70 to p77 p50 to p55 p40 to p42 p30 to p39 p10, p11 p00 to p06 ano0, ano1 av ref1 regc av ref0 av ss ani0 to ani7 clkout x1 x2 xt1 xt2 reset v dd ic note 4 bv dd bv ss ev dd ev ss v pp note 5 v ss instruction queue bcu soa0, soa1 sia0, sia1 scka0, scka1 csi0: 2 ch 8-bit timer h: 2 ch rom correction notes 1. pd703212, 703212y: 64 kb (mask rom) pd703213, 703213y: 96 kb (mask rom) pd703214, 703214y: 128 kb (mask rom) pd70f3214, 70f3214y: 128 kb (flash memory) 2. pd703212, 703212y, 703213, 703213y: 4 kb pd703214, 703214y, 70f3214, 70f3214y: 6 kb 3. only for the pd703212y, 703213y, 703214y, and 70f3214y 4. only for the pd703212, 703212y, 703213, 703213y, 703214, and 703214y 5. only for the pd70f3214 and 70f3214y chapter 1 introduction user ? s manual u15862ej3v0ud 44 (2) internal units (a) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate processing of complex instructions. (b) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory space and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the prefetched instruction code is stored in an internal instruction queue. (c) rom this consists of a 128 kb, 96 kb, or 64 kb mask rom or flash memory mapped to the address spaces from 0000000h to 001ffffh, 0000000h to 0017fffh, or 0000000h to 000ffffh, respectively. rom can be accessed by the cpu in one clock cycle during instruction fetch. (d) ram this consists of a 6 kb or 4 kb ram mapped to the address spaces from 3ffd800h to 3ffefffh or 3ffe000h to 3ffefffh, respectively. ram can be accessed by the cpu in one clock cycle during data access. (e) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0 to intp6) from on-chip peripheral hardware and external hardware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. (f) clock generator (cg) the clock generator includes two types of oscillators: one for the main clock (f xx ) and one for the subclock (f xt ). it generates seven types of clocks (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, and f xt ), and supplies one of them as the operating clock for the cpu (f cpu ). (g) timer/counter four 16-bit timer/event counter channels and two 8-bit timer/event counter channels are incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. two 8-bit timer/event counters can be connected in cascade to configure a 16-bit timer. two 8-bit timer h channels are provided on chip. (h) watch timer this timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 khz) or f brg (32.768 khz) from the clock generator. at the same time, the watch timer can be used as an interval timer. chapter 1 introduction user ? s manual u15862ej3v0ud 45 (i) watchdog timer two watchdog timer channels are provided on chip to detect program loops and system abnormalities. watchdog timer 1 can be used as an interval timer. when used as a watchdog timer, it generates a non- maskable interrupt request signal (intwdt1) or system reset (wdtres1) after an overflow occurs. when used as an interval timer, it generates a maskable interrupt request signal (intwdtm1) after an overflow occurs. watchdog timer 2 operates by default following reset release. it generates a non-maskable interrupt request signal (intwdt2) or system reset signal (wdtres2) after an overflow occurs. (j) serial interface (sio) the v850es/kg1 includes four kinds of serial interfaces: an asynchronous serial interface (uartn), a clocked serial interface (csi0n), a clocked serial interface (with an automatic transmit/receive function) (csian), and an i 2 c bus interface (i 2 c0). the pd703212, 703213, 703214, and 70f3214 can simultaneously use up to six channels, and the pd703212y, 703213y, 703214y, and 70f3214y up to seven channels. for uartn, data is transferred via the txdn and rxdn pins. for csi0n, data is transferred via the so0n, si0n, and sck0n pins. for csia0, data is transferred via the soan, sian, and sckan pins. for i 2 c0, data is transferred via the sda0 and scl0 pins. i 2 c0 is provided only for the pd703212y, 703213y, 703214y, and 70f3214y. for uart, a dedicated baud rate generator is provided on chip. remark n = 0, 1 (k) a/d converter this high-speed, high-resolution 10-bit a/d converter includes 8 analog input pins. conversion is performed using the successive approximation method. (l) d/a converter a two 8-bit resolution d/a converter channels are included on chip. it uses the r-2r ladder method. (m) rom correction this function is used to replace part of a program in the mask rom with that contained in the internal ram. up to four correction addresses can be specified. (n) key interrupt function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the eight key input pins. (o) real-time output function this function transfers 6-bit data set beforehand to output latches upon occurrence of an external trigger signal or a timer compare register match signal. for the v850es/kg1, a 1-channel 6-bit data real-time output function is provided on chip. chapter 1 introduction user ? s manual u15862ej3v0ud 46 (p) ports as shown below, the following ports have general-purpose port functions and control pin functions. port i/o port function control function p0 7-bit i/o nmi, external interrupt, timer output p1 2-bit i/o d/a converter analog output p3 10-bit i/o serial interface, timer i/o p4 3-bit i/o serial interface p5 6-bit i/o serial interface, timer i/o, key interrupt function, real-time output function p7 8-bit input a/d converter analog input p9 16-bit i/o external address bus, serial interface, timer output, external interrupt, key interrupt function pcm 4-bit i/o external bus interface pcs 2-bit i/o chip select output pct 4-bit i/o external bus interface pdh 6-bit i/o external address bus pdl 16-bit i/o general-purpose port external address/data bus chapter 1 introduction user ? s manual u15862ej3v0ud 47 1.4 v850es/kj1 1.4.1 features (v850es/kj1) { number of instructions: 83 { minimum instruction execution time: 50 ns (operation at main clock (f xx ) = 20 mhz) { general-purpose registers: 32 bits 32 registers { instruction set: signed multiplication (16 16 32): 1 to 2 clocks (instructions without creating register hazards can be continuously executed in parallel) saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space: 64 mb of linear address space memory block division function: 2 mb, 2 mb, 4 mb, 8 mb (total of 4 blocks) { external bus interface 16-bit data bus address bus: separate output possible { internal memory pd703216, 703216y (mask rom: 96 kb/ram: 6 kb) pd703217, 703217y (mask rom: 128 kb/ram: 6 kb) pd70f3217, 70f3217y (flash memory: 128 kb/ram: 6 kb) { interrupts and exceptions non-maskable interrupts: 3 sources maskable interrupts: 43 sources ( pd703216, 703217, 70f3217) 45 sources ( pd703216y, 703217y, 70f3217y) software exceptions: 32 sources exception trap: 1 source { i/o lines: total: 128 { key interrupt function { timer/counter 16-bit timer/event counter: 6 channels 8-bit timer/event counter: 2 channels 8-bit timer h: 2 channels { watch timer: 1 channel { watchdog timers watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel watchdog timer 2: 1 channel { serial interface (sio) asynchronous serial interface (uart): 3 channels 3-wire serial i/o (csi0): 3 channels 3-wire serial i/o (with automatic transmit/receive function) (csia): 2 channels i 2 c bus interface (i 2 c): 2 channels ( pd703216y, 703217y, 70f3217y) { a/d converter: 10-bit resolution 16 channels { d/a converter: 8-bit resolution 2 channels { real-time output port: 6 bit 2 channels { power-save functions: halt/idle/stop modes, subclock/sub-idle modes chapter 1 introduction user ? s manual u15862ej3v0ud 48 { rom correction: 4 correction addresses specifiable { packages: 144-pin plastic lqfp (fine pitch) (20 20) 1.4.2 applications (v850es/kj1) audio equipment, etc. 1.4.3 ordering information (v850es/kj1) part number package quality grade pd703216gj- -uen pd703216ygj- -uen pd703217gj- -uen pd703217ygj- -uen pd70f3217gj-uen pd70f3217ygj-uen pd703216gj(a)- -uen note pd703216ygj(a)- -uen note pd703217gj(a)- -uen note pd703217ygj(a)- -uen note pd70f3217gj(a)-uen note pd70f3217ygj(a)-uen note 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) standard standard standard standard standard standard special special special special special special note under development remark indicates rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. chapter 1 introduction user ? s manual u15862ej3v0ud 49 1.4.4 pin configuration (top view) (v850es/kj1) 144-pin plastic lqfp (fine pitch) (20 20) pd703216gj- -uen pd70f3217gj-uen pd703217gj(a)- -uen pd703216ygj- -uen pd70f3217ygj-uen pd703217ygj(a)- -uen pd703217gj- -uen pd703216gj(a)- -uen pd70f3217gj(a)-uen pd703217ygj- -uen pd703216ygj(a)- -uen pd70f3217ygj(a)-uen pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 bv dd bv ss pct7 pct6/astb pct5 pct4/rd pct3 pct2 pct1/wr1 pct0/wr0 pcs7 pcs6 pcs5 pcs4 pcm5 pcm4 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pcs3/cs3 pcs2/cs2 pcs1/cs1 pcs0/cs0 pcd3 pcd2 pcd1 pcd0 p915/a15/intp6 p914/a14/intp5 p913/a13/intp4 p912/a12/scka1 av ref0 av ss p10/ano0 p11/ano1 av ref1 p00/toh0 p01/toh1 v pp note 1 /ic note 1 v dd regc v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0 p04/intp1 p05/intp2 p06/intp3 p40/si00 p41/so00 p42/sck00 p30/txd0 p31/rxd0 p32/asck0 p33/ti000/to00 p34/ti001 p35/ti010/to01 p36 p37 ev ss ev dd p38/sda0 note 2 p39/scl0 note 2 p50/ti011/rtp00/kr0 p51/ti50/rtp01/kr1 p52/to50/rtp02/kr2 p53/sia0/rtp03/kr3 p54/soa0/rtp04/kr4 p55/scka0/rtp05/kr5 p60/rtp10 p61/rtp11 p62/rtp12 p63/rtp13 p64/rtp14 p65/rtp15 p66/si02 p67/so02 p68/sck02 p69/ti040 p610/ti041 p611/to04 p612/ti050 p613/ti051/to05 p614 p615 p80/rxd2/sda1 note 2 p81/txd2/scl1 note 2 p90/a0/txd1/kr6 p91/a1/rxd1/kr7 p92/a2/ti020/to02 p93/a3/ti021 p94/a4/ti030/to03 p95/a5/ti031 p96/a6/ti51/to51 p97/a7/si01 p98/a8/so01 p99/a9/sck01 p910/a10/sia1 p911/a11/soa1 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 p712/ani12 p713/ani13 p714/ani14 p715/ani15 pdh7/a23 pdh6/a22 pdh5/a21 pdh4/a20 pdh3/a19 pdh2/a18 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5 pdl4/ad4 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 notes 1. ic: connect directly to v ss ( pd703216, 703216y, 703217, 703217y). v pp : connect to v ss in normal operation mode ( pd70f3217, 70f3217y). 2. scl0, sda0, scl1, and sda1 can be used only for the pd703216y, 703217y, and 70f3217y. caution make ev dd the same potential as v dd . bv dd can be used when v dd = ev dd bv dd . chapter 1 introduction user ? s manual u15862ej3v0ud 50 pin identification (v850es/kj1) a0 to a23: ad0 to ad15: ani0 to ani15: ano0, ano1: asck0: astb: av ref0 , av ref1 : av ss : bv dd : bv ss : clkout: cs0 to cs3: ev dd : ev ss : hldak: hldrq: ic: intp0 to intp6: kr0 to kr7: nmi: p00 to p06: p10, p11: p30 to p39: p40 to p42: p50 to p55: p60 to p615: p70 to p715: p80, p81: p90 to p915: pcd0 to pcd3: pcm0 to pcm5: pcs0 to pcs7: pct0 to pct7: pdh0 to pdh7: address bus address/data bus analog input analog output asynchronous serial clock address strobe analog reference voltage ground for analog power supply for bus interface ground for bus interface clock output chip select power supply for port ground for port hold acknowledge hold request internally connected interrupt request from peripherals key return non-maskable interrupt request port 0 port 1 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port cd port cm port cs port ct port dh pdl0 to pdl15: rd: regc: reset: rtp00 to rtp05, rtp10 to rtp15: rxd0 to rxd2: sck00 to sck02, scka0, scka1: scl0, scl1: sda0, sda1: si00 to si02, sia0, sia1: so00 to so02, soa0, soa1: ti000, ti001, ti010, ti011, ti020, ti021, ti030, ti031, ti040, ti041, ti050, ti051, ti50, ti51: to00 to to05, to50, to51, toh0, toh1: txd0 to txd2: v dd : v pp : v ss : wait: wr0: wr1: x1, x2: xt1, xt2: port dl read strobe regulator control reset real-time output port receive data serial clock serial clock serial data serial input serial output timer input timer output transmit data power supply programming power supply ground wait lower byte write strobe upper byte write strobe crystal for main clock crystal for subclock chapter 1 introduction user ? s manual u15862ej3v0ud 51 1.4.5 function block configuration (v850es/kj1) (1) internal block diagram nmi to00 to to05 sio ti000, ti001, ti010, ti011, ti020, ti021, ti030, ti031, ti040, ti041, ti050, ti051 so00 to so02 si00 to si02 sck00 to sck02 intp0 to intp6 intc 16-bit timer/event counter: 6 ch to50, to51 ti50, ti51 8-bit timer/event counter: 2 ch toh0, toh1 txd0 to txd2 rxd0 to rxd2 asck0 rtp00 to rtp05, rtp10 to rtp15 kr0 to kr7 uart : 3 ch csia : 2 ch rtp: 2 ch sda0, sda1 note 2 scl0, scl1 note 2 i 2 c note 3 : 2 ch watchdog timer key interrupt function regulator watch timer note 1 6 kb ram rom pc general-purpose registers 32 bits 32 multiplier 16 16 32 alu system registers 32-bit barrel shifter cpu hldrq hldak astb rd wait wr0, wr1 cs0 to cs3 a0 to a23 ad0 to ad15 ports cg a/d converter d/a converter pdl0 to pdl15 pdh0 to pdh7 pct0 to pct7 pcs0 to pcs7 pcm0 to pcm5 pcd0 to pcd3 p90 to p915 p80,p81 p70 to p715 p60 to p615 p50 to p55 p40 to p42 p30 to p39 p10,p11 p00 to p06 ano0, ano1 av ref1 regc av ref0 av ss ani0 to ani15 clkout x1 x2 xt1 xt2 reset v dd ic note 3 bv dd bv ss ev dd ev ss v pp note 4 v ss instruction queue bcu soa0, soa1 sia0, sia1 scka0, scka1 csi0 : 3 ch 8-bit timer h : 2 ch rom correction notes 1. pd703216, 703216y: 96 kb (mask rom) pd703217, 703217y: 128 kb (mask rom) pd70f3217, 70f3217y: 128 kb (flash memory) 2. only for the pd703216y, 703217y, 70f3217y 3. only for the pd703216, 703216y, 703217, and 703217y 4. only for the pd70f3217 and 70f3217y chapter 1 introduction user ? s manual u15862ej3v0ud 52 (2) internal units (a) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate processing of complex instructions. (b) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory space and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the prefetched instruction code is stored in an internal instruction queue. (c) rom this consists of a 128 kb or 96 kb mask rom or flash memory mapped to the address spaces from 0000000h to 001ffffh or 0000000h to 0017fffh, respectively. rom can be accessed by the cpu in one clock cycle during instruction fetch. (d) ram this consists of a 6 kb ram mapped to the address spaces from 3ffd800h to 3ffefffh. ram can be accessed by the cpu in one clock cycle during data access. (e) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0 to intp6) from on-chip peripheral hardware and external hardware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. (f) clock generator (cg) the clock generator includes two types of oscillators: one for the main clock (f xx ) and one for the subclock (f xt ). it generates seven types of clocks (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, and f xt ), and supplies one of them as the operating clock for the cpu (f cpu ). (g) timer/counter six 16-bit timer/event counter channels and two 8-bit timer/event counter channels are incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. two 8-bit timer/event counters can be connected in cascade to configure a 16-bit timer. two 8-bit timer h channels are provided on chip. (h) watch timer this timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 khz) or f brg (32.768 khz) from the clock generator. at the same time, the watch timer can be used as an interval timer. chapter 1 introduction user ? s manual u15862ej3v0ud 53 (i) watchdog timer two watchdog timer channels are provided on chip to detect program loops and system abnormalities. watchdog timer 1 can be used as an interval timer. when used as a watchdog timer, it generates a non- maskable interrupt request signal (intwdt1) or system reset signal (wdtres1) after an overflow occurs. when used as an interval timer, it generates a maskable interrupt request signal (intwdtm1) after an overflow occurs. watchdog timer 2 operates by default following reset release. it generates a non-maskable interrupt request signal (intwdt2) or system reset signal (wdtres2) after an overflow occurs. (j) serial interface (sio) the v850es/kj1 includes four kinds of serial interfaces: an asynchronous serial interface (uartn), a clocked serial interface (csi0n), a clocked serial interface (with an automatic transmit/receive function) (csiam), and an i 2 c bus interface (i 2 cm). the pd703216, 703217, and 70f3217 can simultaneously use up to eight channels, and the pd703216y, 703217y, and 70f3217y up to nine channels. for uartn, data is transferred via the txdn and rxdn pins. for csi0n, data is transferred via the so0n, si0n, and sck0n pins. for csiam, data is transferred via the soam, siam, and sckam pins. for i 2 cm, data is transferred via the sdam and sclm pins. i 2 cm is provided only for the pd703216y, 703217y, and 70f3217y. for uart, a dedicated baud rate generator is provided on chip. remark n = 0 to 2 m = 0, 1 (k) a/d converter this high-speed, high-resolution 10-bit a/d converter includes 16 analog input pins. conversion is performed using the successive approximation method. (l) d/a converter two 8-bit resolution d/a converter channels are included on chip. it uses the r-2r ladder method. (m) rom correction this function is used to replace part of a program in the mask rom with that contained in the internal ram. up to four correction addresses can be specified. (n) key interrupt function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the eight key input pins. (o) real-time output function this function transfers 6-bit data set beforehand to output latches upon occurrence of an external trigger signal or a timer compare register match signal. for the v850es/kj1, a 2-channel 6-bit data real-time output function is provided on chip. chapter 1 introduction user ? s manual u15862ej3v0ud 54 (p) ports as shown below, the following ports have general-purpose port functions and control pin functions. port i/o port function control function p0 7-bit i/o nmi, external interrupt, timer output p1 2-bit i/o d/a converter analog output p3 10-bit i/o serial interface, timer i/o p4 3-bit i/o serial interface p5 6-bit i/o serial interface, timer i/o, key interrupt function, real-time output function p6 16-bit i/o serial interface, timer i/o, real-time output function p7 16-bit input a/d converter analog input p8 2-bit i/o serial interface p9 16-bit i/o external address bus, serial interface, timer output, external interrupt, key interrupt function pcd 4-bit i/o ? pcm 6-bit i/o external bus interface pcs 8-bit i/o chip select output pct 8-bit i/o external bus interface pdh 8-bit i/o external address bus pdl 16-bit i/o general-purpose port external address/data bus user?s manual u15862ej3v0ud 55 chapter 2 pin functions the names and functions of the pins of the v850es/kf1, v850es/kg1, and v850es/kj1 are described below, divided into port pins and non-port pins. the pin i/o buffer power supplies are divided into three systems; av ref0 /av ref1 , bv dd , and ev dd . the relationship between these power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies power supply corresponding pin av ref0 port 7 av ref1 port 1 bv dd port cd, port cm, port cs, port ct, port dh, port dl ev dd port 0, port 3, port 4, port 5, port 6, port 8, port 9, reset 2.1 list of pin functions (1) port pins (1/4) pin name i/o pull-up resistor function alternate function products p00 toh0 p01 toh1 p02 nmi p03 intp0 p04 intp1 p05 intp2 p06 i/o yes port 0 i/o port input/output can be specified in 1-bit units. intp3 all products p10 ano0 p11 i/o yes port 1 i/o port input/output can be specified in 1-bit units. ano1 kg1, kj1 p30 txd0 p31 rxd0 p32 asck0 p33 ti000/to00 p34 ti001 p35 yes ti010/to01 all products p36 ? p37 ? kg1, kj1 p38 sda0 note 2 p39 i/o no note 1 port 3 i/o port input/output can be specified in 1-bit units. scl0 note 2 all products notes 1. an on-chip pull-up resistor can be provided by a mask option (only for the mask rom versions). 2. only for products with an i 2 c bus remark kg1: v850es/kg1, kj1: v850es/kj1 chapter 2 pin functions user?s manual u15862ej3v0ud 56 (2/4) pin name i/o pull-up resistor function alternate function products p40 si00 p41 so00 p42 i/o yes port 4 i/o port input/output can be specified in 1-bit units. sck00 all products p50 ti011/rtp00/kr0 p51 ti50/rtp01/kr1 p52 to50/rtp02/kr2 p53 sia0/rtp03/kr3 p54 soa0/rtp04/kr4 p55 i/o yes port 5 i/o port input/output can be specified in 1-bit units. scka0/rtp05/kr5 all products p60 rtp10 p61 rtp11 p62 rtp12 p63 rtp13 p64 rtp14 p65 rtp15 p66 si02 p67 so02 p68 sck02 p69 ti040 p610 ti041 p611 to04 p612 ti050 p613 yes ti051/to05 p614 ? p615 i/o no note port 6 i/o port input/output can be specified in 1-bit units. ? kj1 p70 ani0 p71 ani1 p72 ani2 p73 ani3 p74 ani4 p75 ani5 p76 ani6 p77 ani7 all products p78 ani8 p79 ani9 p710 ani10 p711 ani11 p712 input no port 7 input port ani12 kj1 note an internal pull-up resistor can be provided by a mask option (only for the mask rom versions). remark kj1: v850es/kj1 chapter 2 pin functions user?s manual u15862ej3v0ud 57 (3/4) pin name i/o pull-up resistor function alternate function products p713 ani13 p714 ani14 p715 input no port 7 input port ani15 kj1 p80 rxd2/sda1 note p81 i/o yes port 8 i/o port input/output can be specified in 1-bit units. txd2/scl1 note kj1 p90 a0/txd1/kr6 p91 a1/rxd1/kr7 all products p92 a2/ti020/to02 p93 a3/ti021 p94 a4/ti030/to03 p95 a5/ti031 kg1, kj1 p96 a6/ti51/to51 p97 a7/si01 p98 a8/so01 p99 a9/sck01 all products p910 a10/sia1 p911 a11/soa1 p912 a12/scka1 kg1, kj1 p913 a13/intp4 p914 a14/intp5 p915 i/o yes port 9 i/o port input/output can be specified in 1-bit units. a15/intp6 all products pcd0 ? pcd1 ? pcd2 ? pcd3 i/o no port cd i/o port input/output can be specified in 1-bit units. ? kj1 pcm0 wait pcm1 clkout pcm2 hldak pcm3 hldqr all products pcm4 ? pcm5 i/o no port cm i/o port input/output can be specified in 1-bit units. ? kj1 pcs0 cs0 pcs1 cs1 all products pcs2 cs2 pcs3 cs3 pcs4 ? pcs5 ? pcs6 ? pcs7 i/o no port cs i/o port input/output can be specified in 1-bit units. ? kj1 note only for the pd703216y, 703217y, and 70f3217y remarks 1. kg1: v850es/kg1, kj1: v850es/kj1 2. the a0 to a15 pins are not provided in the v850es/kf1. chapter 2 pin functions user?s manual u15862ej3v0ud 58 (4/4) pin name i/o pull-up resistor function alternate function products pct0 wr0 pct1 wr1 all products pct2 ? pct3 ? kj1 pct4 rd all products pct5 ?kj1 pct6 astb all products pct7 i/o no port ct i/o port input/output can be specified in 1-bit units. ?kj1 pdh0 a16 pdh1 a17 pdh2 a18 pdh3 a19 pdh4 a20 pdh5 a21 kg1, kj1 pdh6 a22 pdh7 i/o no port dh i/o port input/output can be specified in 1-bit units. a23 kj1 pdl0 ad0 pdl1 ad1 pdl2 ad2 pdl3 ad3 pdl4 ad4 pdl5 ad5 pdl6 ad6 pdl7 ad7 pdl8 ad8 pdl9 ad9 pdl10 ad10 pdl11 ad11 pdl12 ad12 pdl13 ad13 pdl14 ad14 pdl15 i/o no port dl i/o port input/output can be specified in 1-bit units. ad15 all products remark kg1: v850es/kg1, kj1: v850es/kj1 chapter 2 pin functions user?s manual u15862ej3v0ud 59 (2) non-port pins (1/5) pin name i/o pull-up resistor function alternate function products a0 p90/tdx1/kr6 a1 p91/rxd1/kr7 a2 p92/ti020/to2 a3 p93/ti021 a4 p94/ti030/to3 a5 p95/ti031 a6 p96/ti51/to51 a7 p97/si01 a8 p98/so01 a9 p99/sck01 a10 p910/sia1 a11 p911/soa1 a12 p912/scka1 a13 p913/intp4 a14 p914/intp5 a15 output yes address bus for external memory (when using a separate bus) p915/intp6 kg1, kj1 a16 pdh0 a17 pdh1 a18 pdh2 a19 pdh3 a20 pdh4 a21 pdh5 kg1, kj1 a22 pdh6 a23 output no address bus for external memory pdh7 kj1 ad0 pdl0 ad1 pdl1 ad2 pdl2 ad3 pdl3 ad4 pdl4 ad5 pdl5 ad6 pdl6 ad7 pdl7 ad8 pdl8 ad9 pdl9 ad10 pdl10 ad11 pdl11 ad12 pdl12 ad13 pdl13 ad14 pdl14 ad15 i/o no address/data bus for external memory pdl15 all products remark kg1: v850es/kg1, kj1: v850es/kj1 chapter 2 pin functions user?s manual u15862ej3v0ud 60 (2/5) pin name i/o pull-up resistor function alternate function products ani0 p70 ani1 p71 ani2 p72 ani3 p73 ani4 p74 ani5 p75 ani6 p76 ani7 p77 all products ani8 p78 ani9 p79 ani10 p710 ani11 p711 ani12 p712 ani13 p713 ani14 p714 ani15 input no analog voltage input for a/d converter p715 kj1 ano0 p10 ano1 output yes analog voltage output for d/a converter p11 kg1, kj1 asck0 input yes uart0 serial clock input p32 all products astb output no address strobe signal output for external memory pct6 all products av ref0 ? ? reference voltage for a/d converter ? all products av ref1 ? ? reference voltage for d/a converter ? kg1, kj1 av ss ?? ground potential for a/d and d/a converters ? all products bv dd ?? positive power supply for bus interface and alternate-function ports ? kg1, kj1 bv ss ? ? ground potential for bus interface and alternate-function ports ? kg1, kj1 clkout output no internal system clock output pcm1 all products cs0 pcs0 cs1 pcs1 all products cs2 pcs2 cs3 output no chip select output pcs3 kj1 ev dd ? ? positive power supply for external ? all products ev ss ? ? ground potential for external ? all products hldak output no bus hold acknowledge output pcm2 all products hldrq input no bus hold request input pcm3 all products ic note ? ? internally connected ? all products intp0 p03 intp1 p04 intp2 p05 intp3 p06 intp4 p913/a13 intp5 p914/a14 intp6 input yes external interrupt request input (maskable, analog noise elimination) p915/a15 all products note only for the mask rom versions remark kg1: v850es/kg1, kj1: v850es/kj1 chapter 2 pin functions user?s manual u15862ej3v0ud 61 (3/5) pin name i/o pull-up resistor function alternate function products kr0 p50/ti011/rtp00 kr1 p51/ti50/rtp01 kr2 p52/to50/rtp02 kr3 p53/sia0/rtp03 kr4 p54/soa0/rtp04 kr5 p55/scka0/rtp05 kr6 p90/a0/txd1 kr7 input yes key return input p91/a1/rxd1 all products nmi input yes external interrupt input (non-maskable, analog noise elimination) p02 all products rd output no read strobe signal output for external memory pct4 all products regc ? ? connecting capacitor for regulator output stabilization ? all products reset input ? system reset input ? all products rtp00 p50/ti011/kr0 rtp01 p51/ti50/kr1 rtp02 p52/to50/kr2 rtp03 p53/sia0/kr3 rtp04 p54/soa0/kr4 rtp05 p55/scka0/kr5 all products rtp10 p60 rtp11 p61 rtp12 p62 rtp13 p63 rtp14 p64 rtp15 output yes real-time output port p65 kj1 rxd0 serial receive data input for uart0 p31 rxd1 serial receive data input for uart1 p91/a1/kr7 all products rxd2 input yes serial receive data input for uart2 p80/sda1 note 1 kj1 sck00 serial clock i/o for csi00 p42 sck01 serial clock i/o for csi01 p99/a9 all products sck02 serial clock i/o for csi02 p68 kj1 scka0 serial clock i/o for csia0 p55/rtp05/kr5 all products scka1 i/o yes serial clock i/o for csia1 p912/a12 kg1, kj1 scl0 note 1 no note 2 p39 all products scl1 note 3 i/o yes serial clock i/o for i 2 c0, i 2 c1 p81/txd2 kj1 sda0 note 1 no note 2 p38 all products sda1 note 3 i/o yes serial transmit/receive data i/o for i 2 c0, i 2 c1 p80/rxd2 kj1 notes 1. only for products with an i 2 c bus 2. an on-chip pull-up resistor can be provided by a mask option (only for the mask rom and i 2 c bus versions). 3. only for the pd703216y, 703217y, and 70f3217y remark kg1: v850es/kg1, kj1: v850es/kj1 chapter 2 pin functions user?s manual u15862ej3v0ud 62 (4/5) pin name i/o pull-up resistor function alternate function products si00 serial receive data input for csi00 p40 si01 serial receive data input for csi01 p97/a7 all products si02 serial receive data input for csi02 p66 kj1 sia0 serial receive data input for csia0 p53/rtp03/kr3 all products sia1 input yes serial receive data input for csia1 p910/a10 kg1, kj1 so00 serial transmit data output for csi00 p41 so01 serial transmit data output for csi01 p98/a8 all products so02 serial transmit data output for csi02 p67 kj1 soa0 serial transmit data output for csia0 p54/rtp04/kr4 all products soa1 output yes serial transmit data output for csia1 p911/a11 kg1, kj1 ti000 external event/clock input for tm00 p33/to00 ti001 external event/clock input for tm00 p34 ti010 external event/clock input for tm01 p35/to01 ti011 external event/clock input for tm01 p50/rtp00/kr0 all products ti020 external event/clock input for tm02 p92/a2/to02 ti021 external event/clock input for tm02 p93/a3 ti030 external event/clock input for tm03 p94/a4/to03 ti031 external event/clock input for tm03 p95/a5 kg1, kj1 ti040 external event/clock input for tm04 p69 ti041 external event/clock input for tm04 p610 ti050 external event/clock input for tm05 p612 ti051 external event/clock input for tm05 p613/to05 kj1 ti50 external event/clock input for tm50 p51/rtp01/kr1 ti51 input yes external event/clock input for tm51 p96/a6/to51 all products to00 timer output for tm00 p33/ti000 to01 timer output for tm01 p35/ti010 all products to02 timer output for tm02 p92/a2/ti020 to03 timer output for tm03 p94/a4/ti030 kg1, kj1 to04 timer output for tm04 p611 to05 timer output for tm05 p613/ti051 kj1 to50 timer output for tm50 p52/rtp02/kr2 to51 timer output for tm51 p96/a6/ti51 toh0 timer output for tmh0 p00 toh1 output yes timer output for tmh1 p01 all products txd0 serial transmit data output for uart0 p30 txd1 serial transmit data output for uart1 p90/a0/kr6 all products txd2 output yes serial transmit data output for uart2 p81/scl1 note 1 kj1 v dd ? ? positive power supply pin for internal ? all products v pp ?? high-voltage application pin for program write/verify ? all products note 2 v ss ? ? ground potential for internal ? all products notes 1. only for the pd703216y, 703217y, and 70f3217y 2. only for products with flash memory remark kg1: v850es/kg1, kj1: v850es/kj1 chapter 2 pin functions user?s manual u15862ej3v0ud 63 (5/5) pin name i/o pull-up resistor function alternate function products wait input no external wait input pcm0 all products wr0 write strobe for external memory (lower 8 bits) pct0 all products wr1 output no write strobe for external memory (higher 8 bits) pct1 all products x1 input no ? all products x2 ? no connecting resonator for main clock ? all products xt1 input no ? all products xt2 ? no connecting resonator for subclock ? all products chapter 2 pin functions user?s manual u15862ej3v0ud 64 2.2 pin status the address bus becomes undefined during accesses to the internal ram and rom. the data bus goes into the high-impedance state without data output. the external bus control signal becomes inactive. during peripheral i/o access, the address bus outputs the addresses of the on-chip peripheral i/os that are accessed. the data bus goes into the high-impedance state without data output. the external bus control signal becomes inactive. table 2-2. pin operation status in operation modes of v850es/kf1 operating status pin reset note 1 halt mode idle mode/ stop mode idle state note 2 bus hold ad0 to ad15 (pdl0 to pdl15) hi-z operating hi-z held hi-z wait (pcm0) hi-z operating ? ? ? clkout (pcm1) hi-z operating l operating operating cs0, cs1 (pcs0, pcs1) hi-z operating h held hi-z wr0, wr1 (pct0, pct1) hi-z operating h h hi-z rd (pct4) hi-z operating h h hi-z astb (pct6) hi-z operating h h hi-z hldak (pcm2) hi-z operating h h l hldrq (pcm3) hi-z operating ? ? operating notes 1. since the bus control pin is also used as a port pin, it is initialized to the port mode (input) after reset. 2. the pin statuses in the idle state inserted after the t3 state are listed. remark hi-z: high impedance h: high-level output l: low-level output ?: input without sampling (input acknowledgement not possible) chapter 2 pin functions user?s manual u15862ej3v0ud 65 table 2-3. pin operation status in operation modes of v850es/kg1 operating status pin reset note 1 halt mode idle mode/ stop mode idle state note 2 bus hold ad0 to ad15 (pdl0 to pdl15) hi-z operating hi-z held hi-z a0 to a15 (p90 to p915) hi-z operating hi-z held hi-z a16 to a21 (pdh0 to pdh5) hi-z operating hi-z held hi-z wait (pcm0) hi-z operating ? ? ? clkout (pcm1) hi-z operating l operating operating cs0, cs1 (pcs0, pcs1) hi-z operating h held hi-z wr0, wr1 (pct0, pct1) hi-z operating h h hi-z rd (pct4) hi-z operating h h hi-z astb (pct6) hi-z operating h h hi-z hldak (pcm2) hi-z operating h h l hldrq (pcm3) hi-z operating ? ? operating notes 1. since the bus control pin is also used as a port pin, it is initialized to the port mode (input) after reset. 2. the pin statuses in the idle state inserted after the t3 state in the multiplex mode and after the t2 state in the separate mode are listed. remark hi-z: high impedance h: high-level output l: low-level output ?: input without sampling (input acknowledgement not possible) table 2-4. pin operation status in operation modes of v850es/kj1 operating status pin reset note 1 halt mode idle mode/ stop mode idle state note 2 bus hold ad0 to ad15 (pdl0 to pdl15) hi-z operating hi-z held hi-z a0 to a15 (p90 to p915) hi-z operating hi-z held hi-z a16 to a23 (pdh0 to pdh7) hi-z operating hi-z held hi-z wait (pcm0) hi-z operating ? ? ? clkout (pcm1) hi-z operating l operating operating cs0 to cs3 (pcs0 to pcs3) hi-z operating h held hi-z wr0, wr1 (pct0, pct1) hi-z operating h h hi-z rd (pct4) hi-z operating h h hi-z astb (pct6) hi-z operating h h hi-z hldak (pcm2) hi-z operating h h l hldrq (pcm3) hi-z operating ? ? operating notes 1. since the bus control pin is also used as a port pin, it is initialized to the port mode (input) after reset. 2. the pin statuses in the idle state inserted after the t3 state in the multiplex mode and after the t2 state in the separate mode are listed. remark hi-z: high impedance h: high-level output l: low-level output ?: input without sampling (input acknowledgement not possible) chapter 2 pin functions user?s manual u15862ej3v0ud 66 2.3 description of pin functions 2.3.1 v850es/kf1 (1) p00 to p06 (port 0) ... i/o port 0 is a 7-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p00 to p06 can also be used for nmi input, external interrupt request input, and timer h output in the control mode. the port mode and control mode (alternate functions) can be selected as the operation mode for each bit, and are specified by the port 0 mode control register (pmc0). (a) port mode p00 to p06 can be set to input or output in 1-bit units by the port 0 mode register (pm0). (b) control mode (alternate function) p00 to p06 can be set to the port mode or control mode in 1-bit units by the port 0 mode control register (pmc0). (i) nmi (non-maskable interrupt request) ... input this is a non-maskable interrupt request input pin. (ii) intp0 to intp3 (interrupt request from peripherals) ... input these are external interrupt request input pins. (iii) toh0, toh1 (timer output) ... output these are timer h pulse signal output pins. (2) p30 to p35, p38, p39 (port 3) ... i/o port 3 is an 8-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p30 to p35, p38, and p39 can also be used for serial interface (uart0, i 2 c0) i/o and 16-bit timer input in control mode 1, and for 16-bit timer output in control mode 2. the port mode and control mode can be selected as the operation mode for each bit, and are specified by the port 3 mode control register (pmc3). p33 and p35 can be set to control mode 1 and control mode 2 in 1-bit units by the port 3 function control register (pfc3). when used as outputs, p38 and p39 are fixed to n-ch open-drain output. (a) port mode p30 to p35, p38, and p39 can be set to input or output in 1-bit units by the port 3 mode register (pm3). (b) control mode p30 to p35, p38, and p39 can be set to the port mode or control mode in 1-bit units by the port 3 mode control register (pmc3). p33 and p35 can be set to control mode 1 and control mode 2 in 1-bit units by the port 3 function control register (pfc3). (i) txd0 (transmit data) ... output this is the serial transmit data output pin for uart0. chapter 2 pin functions user?s manual u15862ej3v0ud 67 (ii) rxd0 (receive data) ... input this is the serial receive data input pin for uart0. (iii) asck0 (asynchronous serial clock) ... input this is the serial baud rate clock input pin for uart0. (iv) ti000, ti001, ti010 (timer input) ... input these are the external count clock input pins for the 16-bit timer. (v) to00, to01 (timer output) ... output these are the pulse signal output pins for the 16-bit timer. (vi) sda0 (serial data) ... i/o this is the serial transmit/receive data i/o pin for i 2 c0 (only for the pd703208y, 703209y, 703210y, and 70f3210y). (vii) scl0 (serial clock) ... i/o this is the serial clock i/o pin for i 2 c0 (only for the pd703208y, 703209y, 703210y, and 70f3210y). (3) p40 to p42 (port 4) ... i/o port 4 is a 3-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p40 to p42 can also be used for serial interface (csi00) i/o in the control mode. the port mode and control mode can be selected as the operation mode for each bit, and are specified by the port 4 mode control register (pmc4). normal output and n-ch open-drain output can be selected for p41 and p42. (a) port mode p40 to p42 can be set to input or output in 1-bit units by the port 4 mode register (pm4). (b) control mode p40 to p42 can be set to the port mode or control mode in 1-bit units by the pmc4 register. (i) so00 (serial output) ... output this is the serial transmit data output pin for csi00. (ii) si00 (serial input) ... input this is the serial receive data input pin for csi00. (iii) sck00 (serial clock) ... i/o this is the serial clock i/o pin for csi00. chapter 2 pin functions user?s manual u15862ej3v0ud 68 (4) p50 to p55 (port 5) ... i/o port 5 is a 6-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p50 to p55 can also be used as 16-bit timer input, 8-bit timer i/o, and serial interface (csia0) i/o pins in control mode 1, and as real-time output port pins in control mode 2. they can also be used as key interrupt inputs by setting key return mode register krm while in the input port mode. the port mode and control mode (alternate functions) can be selected as the operation mode in 1-bit units, and are specified by the port 5 mode control register (pmc5). p50 to p55 can be set to control mode 1 or control mode 2 in 1-bit units by the port 5 function control register (pfc5). normal output and n-ch open-drain output can be selected for p54 and p55. (a) port mode p50 to p55 can be set to input or output in 1-bit units by the port 5 mode register (pm5). (b) control mode (alternate function) p50 to p55 can be set to the port mode or control mode in 1-bit units by the port 5 mode control register (pmc5). (i) ti011 (timer input) ... input this is the external count clock input pin for the 16-bit timer. (ii) ti50 (timer input) ... input this is the external count clock input pin for the 8-bit timer. (iii) to50 (timer output) ... output this is the pulse signal output pin for the 8-bit timer. (iv) soa0 (serial output) ... output this is the csia0 serial transmit data output pin. (v) sia0 (serial input) ... input this is the csia0 serial receive data input pin. (vi) scka0 (serial clock) ... i/o this is the csia0 serial clock i/o pin. (vii) rtp00 to rtp05 (real-time output port) ... output these pins operate as a real-time output port. (viii) kr0 to kr5 (key return) ... input these are the key interrupt input pins. their operation is specified by the key return mode register (krm) in the input port mode. chapter 2 pin functions user?s manual u15862ej3v0ud 69 (6) p70 to p77 (port 7) ... input port 7 is an 8-bit input-only port in which all the pins are fixed to input. in addition to functioning as input ports pins, p70 to p77 can also be used for a/d converter (adc) analog input in the control mode. normally, when port and function pins are shared, their operation can be selected by the port mode control register, but in the case of p70 to p77, such a register does not exist. therefore, these pins cannot be switched between input port and analog input pins for the a/d converter (adc). for the state of each pin, read the port. (a) port mode p70 to p77 are input-only pins. (b) control mode (alternate function) p70 to p77 are shared with ani0 to ani7, but switching is not possible. (i) ani0 to ani7 (analog input) ... input these are the analog input pins to the a/d converter (adc). (7) p90, p91, p96 to p99, p913 to p915 (port 9) ... i/o port 9 is a 9-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p90, p91, p96 to p99, and p913 to p915 can also be used for serial interface (uart1, csi01) i/o, 16-bit timer i/o, 8-bit timer output, and external interrupt request input in the control mode. moreover, they can also function as 16-bit timer inputs, 8-bit timer inputs, and key interrupts in the input port mode. the port mode and control mode can be selected as the operation mode for each bit, and are specified by the port 9 mode control register (pmc9). p90, p91, p96 to p99, and 913 to p915 can be set to control mode 2 in 1-bit units by the port 9 function control register (pfc9). (there is no control mode 1 for these pins. setting to control mode 1 (pmc9n bit of port 9 mode control register (pmc9) = 1 and pfc9n bit of pfc9 register = 0) is prohibited since output is undefined.) (n = 0, 1, 6 to 9, 13 to 15) normal output or n-ch open-drain output can be selected for p98 and p99. (a) port mode p90, p91, p96 to p99, and p913 to p915 can be set to input or output in 1-bit units by the port 9 mode register (pm9). (b) control mode (alternate function) p90, p91, p96 to p99, and p913 to p915 can be set to the port mode or control mode in 1-bit units by the port 9 mode control register (pmc9). (i) txd1 (transmit data) ... output this is the serial transmit data output pin for uart1. (ii) rxd1 (receive data) ... input this is the serial receive data input pin for uart1. (iii) ti51 (timer input) ... input this is the external count clock input pin for the 8-bit timer. chapter 2 pin functions user?s manual u15862ej3v0ud 70 (iv) to51 (timer output) ... output this is the pulse signal output pin for the 8-bit timer. (v) so01 (serial output) ... output this is the serial transmit data output pin for csi01. (vi) si01 (serial input) ... input this is the serial receive data input pin for csi01. (vii) sck01 (serial clock) ... i/o this is the serial clock i/o pin for csi01. (viii) intp4 to intp6 (interrupt request from peripherals) ... input these are the external interrupt request input pins. (ix) kr6, kr7 (key return) ... input these are the key interrupt input pins. their operations are specified by the key return mode register (krm) in the input port mode. (8) pcm0 to pcm3 (port cm) ... i/o port cm is a 4-bit i/o port for which input or output can be set in 1-bit units. in addition to functioning as a port, these pins can also be used for wait insertion signal input, internal system clock output, and bus hold control signal i/o in the control mode. the port mode and control mode can be selected as the operation mode for each bit, and are specified by the port cm mode control register (pmccm). (a) port mode pcm0 to pcm3 can be set to input or output in 1-bit units by the port cm mode register (pmcm). (b) control mode pcm0 to pcm3 can be set to the port mode or control mode in 1-bit units by the pmccm register. (i) wait (wait) ... input this is a control signal input pin that inserts data waits in a bus cycle. this pin supports asynchronous input for clkout. sampling starts at the falling edge of the clkout signal in the t2 and tw states of the bus cycle. if the setup/hold times in the sampling timing are not satisfied, wait insertion may not be performed. (ii) clkout (clock output) ... output this is the internal system clock output pin. since, in the single-chip mode, it is in the port mode during the reset period, output is not performed from clkout. to perform clkout output, set this pin to the control mode by the port cm mode control register (pmccm). (iii) hldak (hold acknowledge) ... output this is the output pin for the acknowledge signal that indicates that the v850es/kf1 has received a bus hold request and set the external address/data bus and the strobe pins to high impedance. when this signal is active, the external address/data bus and the strobe pins are in high impedance, and the bus mastership is handed to the external bus master. chapter 2 pin functions user?s manual u15862ej3v0ud 71 (iv) hldrq (hold request) ... input this is the input pin by which an external device requests the v850es/kf1 to release the external address/data bus and strobe pins. this pin supports asynchronous input for clkout. when this pin is active, the external address/data bus and strobe pins are set to high impedance either when the v850es/kf1 completes execution of the current bus cycle, or immediately if no bus cycle is being executed. the hldak signal is then made active and the bus is released. to ensure that the bus hold state is entered, keep the hldrq signal active until the hldak signal is output. (9) pcs0, pcs1 (port cs) ... i/o port cs is a 2-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as a port, pcs0 and pcs1 can also be used for chip select signal output when the memory is expanded externally in the control mode. the port mode and control mode can be selected as the operation mode for each bit, and are specified by the port cs mode control register (pmccs). (a) port mode pcs0 and pcs1 can be set to input or output in 1-bit units by the port cs mode register (pmcs). (b) control mode pcs0 and pcs1 can be set to the port mode or control mode in 1-bit units by the pmccs register. (i) cs0, cs1 (chip select) ... output these are the chip select signals for external memory and external peripheral i/os. signal csn is allocated to memory block n (n = 0, 1). these pins become active when a bus cycle for accessing the corresponding memory block is started. in the idle state (ti), these pins are inactive. (10) pct0, pct1, pct4, pct6 (port ct) ... i/o port ct is a 4-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as a port, pct0, pct1, pct4, and pct6 can also be used for control signal output when the memory is expanded externally in the control mode. the port mode and control mode can be selected as the operation mode for each bit, and are specified by the port ct mode control register (pmcct). (a) port mode pct0, pct1, pct4, and pct6 can be set to input or output in 1-bit units by the port ct mode register (pmct). (b) control mode pct0, pct1, pct4, and pct6 can be set to the port mode or control mode in 1-bit units by the pmcct register. (i) wr0 (lower byte write strobe) ... output this is the write strobe signal output pin for the lower data of the external 16-bit data bus. chapter 2 pin functions user?s manual u15862ej3v0ud 72 (ii) wr1 (upper byte write strobe) ... output this is the write strobe signal output pin for the higher data of the external 16-bit data bus. (iii) rd (read strobe) ... output this is the strobe signal that indicates that the bus cycle currently being executed is a read cycle for the external memory or external peripheral i/o. in the idle state (ti), this pin is inactive. (iv) astb (address strobe) ... output this is the latch strobe signal output pin for the external address bus. the output becomes low level in synchronization with the falling edge of the clock in the t1 state of the bus cycle, and becomes high level in synchronization with the falling edge of the clock in the t3 state. (11) pdl0 to pdl15 (port dl) ... i/o port dl is a 16-bit i/o port that can be set to input or output in 1-bit units. in addition to functioning as a port, pdl0 to pdl15 can also be used as an address/data bus (ad0 to ad15) when the memory is expanded externally in the control mode (external expansion mode). the port mode and control mode can be selected as the operation mode for each bit note , and are specified by the port dl mode control register (pmcdl). note when specifying the port mode/control mode (alternate function) for each bit, pay careful attention to the operation of the alternate functions. (a) port mode pdl0 to pdl15 can be set to input or output in 1-bit units by the port dl mode register (pmdl). (b) control mode pdl0 to pdl15 can be used as ad0 to ad15 with the pmcdl register. (i) ad0 to ad15 (address/data bus) ... i/o this is a multiplexed address/data bus during external access. in the address timing (t1 state), these pins function as 16-bit address a0 to a15 output pins, and in the data timing (t2, tw, and t3), they function as data i/o bus pins. (12) reset (reset) ... input reset input is an asynchronous input, and when a signal that has a certain low-level width is input, regardless of the operation clock, system reset is executed with priority over all other actions. in addition to normal initialize and start, reset can also be used to release the standby mode (halt, idle, and stop). (13) regc (regulator control) ... input this is the pin for connecting a capacitor for the regulator. (14) x1, x2 (crystal for main clock) these pins are used to connect the resonator that generates the main clock. an external clock can also be input. (15) xt1, xt2 (crystal for subclock) these pins are used to connect the resonator that generates the subclock. chapter 2 pin functions user?s manual u15862ej3v0ud 73 (16) av ss (ground for analog) this is the ground pin for the a/d converter. (17) av ref0 (analog reference voltage) ... input this is the pin for supplying the reference voltage for the a/d converter. (18) ev dd (power supply for ports) these are the positive power supply pins for the peripheral interface. (19) ev ss (ground for ports) this is the ground pin for the peripheral interface. (20) v dd (power supply) these are the positive power supply pins. connect all v dd pins to a positive power supply. (21) v pp (programming power supply) this is a positive power supply pin for the flash memory programming mode. it is provided for products with flash memory. during normal mode operation, connect this pin to v ss . (22) v ss (ground) these are the ground pins. connect all v ss pins to a positive power supply. (23) ic (internally connected) this is an internally connected pin. connect this pin directly to v ss in the normal operation mode. chapter 2 pin functions user?s manual u15862ej3v0ud 74 2.3.2 v850es/kg1 (1) p00 to p06 (port 0) ... i/o port 0 is a 7-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p00 to p06 can also be used for nmi input, external interrupt request input, and timer h output in the control mode. the port mode and control mode (alternate functions) can be selected as the operation mode for each bit, and are specified by the port 0 mode control register (pmc0). (a) port mode p00 to p06 can be set to input or output in 1-bit units by the port 0 mode register (pm0). (b) control mode (alternate function) p00 to p06 can be set to the port mode or control mode in 1-bit units by the port 0 mode control register (pmc0). (i) nmi (non-maskable interrupt request) ... input this is a non-maskable interrupt request input pin. (ii) intp0 to intp3 (interrupt request from peripherals) ... input these are external interrupt request input pins. (iii) toh0, toh1 (timer output) ... output these are timer h pulse signal output pins. (2) p10, p11 (port 1) ... i/o port 1 is a 2-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p10 and p11 can also be used for d/a converter analog output. the port mode and control mode cannot be selected as the operation mode for each bit. to use these pins as d/a converter analog output pins, set the port 1 mode register (pm1) to output (03h). (a) port mode p10 and p11 can be set to input or output in 1-bit units by the port 1 mode register (pm1). (i) ano0, ano1 (analog output) ... output these are analog output pins to the d/a converter (dac). (3) p30 to p39 (port 3) ... i/o port 3 is a 10-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p30 to p39 can also be used for serial interface (uart0, i 2 c0) i/o and 16-bit timer input in control mode 1, and for 16-bit timer output in control mode 2. the port mode and control mode can be selected as the operation mode for each bit, and are specified by the port 3 mode control register (pmc3). p33 and p35 can be set to control mode 1 or control mode 2 in 1-bit units by the port 3 function control register (pfc3). when used as outputs, p36 to p39 are fixed to n-ch open-drain output. (a) port mode p30 to p39 can be set to input or output in 1-bit units by the port 3 mode register (pm3). chapter 2 pin functions user?s manual u15862ej3v0ud 75 (b) control mode p30 to p39 can be set to the port mode or control mode in 1-bit units by the port 3 mode control register (pmc3). p33 and p35 can be set to control mode 1 or control mode 2 in 1-bit units by the port 3 function control register (pfc3). (i) txd0 (transmit data) ... output this is the serial transmit data output pin for uart0. (ii) rxd0 (receive data) ... input this is the serial receive data input pin for uart0. (iii) asck0 (asynchronous serial clock) ... input this is the serial baud rate clock input pin for uart0. (iv) ti000, ti001, ti010 (timer input) ... input these are the external count clock input pins for the 16-bit timer. (v) to00, to01 (timer output) ... output these are the pulse signal output pins for the 16-bit timer. (vi) sda0 (serial data) ... i/o this is the serial transmit/receive data i/o pin for i 2 c0 (only for the pd703212y, 703213y, 703214y, and 70f3214y). (vii) scl0 (serial clock) ... i/o this is the serial clock i/o pin for i 2 c0 (only for the pd703212y, 703213y, 703214y, and 70f3214y). (4) p40 to p42 (port 4) ... i/o port 4 is a 3-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p40 to p42 can also be used for serial interface (csi00) i/o in the control mode. the port mode and control mode can be selected as the operation mode for each bit, and are specified by the port 4 mode control register (pmc4). normal output and n-ch open-drain output can be selected for p41 and p42. (a) port mode p40 to p42 can be set to input or output in 1-bit units by the port 4 mode register (pm4). (b) control mode p40 to p42 can be set to the port mode or control mode in 1-bit units by the pmc4 register. (i) so00 (serial output) ... output this is the serial transmit data output pin for csi00. (ii) si00 (serial input) ... input this is the serial receive data input pin for csi00. chapter 2 pin functions user?s manual u15862ej3v0ud 76 (iii) sck00 (serial clock) ... i/o this is the serial clock i/o pin for csi00. (5) p50 to p55 (port 5) ... i/o port 5 is a 6-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p50 to p55 can also be used as 16-bit timer input, 8-bit timer i/o, and serial interface (csia0) i/o pins in control mode 1, and as real-time output port pins in control mode 2. they can also be used for key interrupt input by setting key return mode register krm while in the input port mode. the port mode and control mode (alternate functions) can be selected as the operation mode in 1-bit units, and are specified by the port 5 mode control register (pmc5). p50 to p55 can be set to control mode 1 or control mode 2 in 1-bit units by the port 5 function control register (pfc5). normal output and n-ch open-drain output can be selected for p54 and p55. (a) port mode p50 to p55 can be set to input or output in 1-bit units by the port 5 mode register (pm5). (b) control mode (alternate function) p50 to p55 can be set to the port mode or control mode in 1-bit units by the port 5 mode control register (pmc5). (i) ti011 (timer input) ... input this is the external count clock input pin for the 16-bit timer. (ii) ti50 (timer input) ... input this is the external count clock input pin for the 8-bit timer. (iii) to50 (timer output) ... output this is the pulse signal output pin for the 8-bit timer. (iv) soa0 (serial output) ... output this is the csia0 serial transmit data output pin. (v) sia0 (serial input) ... input this is the csia0 serial receive data input pin. (vi) scka0 (serial clock) ... i/o this is the csia0 serial clock i/o pin. (vii) rtp00 to rtp05 (real-time output port) ... output these pins operate as a real-time output port. (viii) kr0 to kr5 (key return) ... input these are the key interrupt input pins. their operation is specified by the key return mode register (krm) in the input port mode. chapter 2 pin functions user?s manual u15862ej3v0ud 77 (6) p70 to p77 (port 7) ... input port 7 is an 8-bit input-only port in which all the pins are fixed to input. in addition to functioning as input ports pins, p70 to p77 can also be used for a/d converter (adc) analog input in the control mode. normally, when port and function pins are shared, their operation can be selected by the port mode control register, but in the case of p70 to p77, such a register does not exist. therefore, these pins cannot be switched between input port and analog input pins for the a/d converter (adc). for the state of each pin, read the port. (a) port mode p70 to p77 are input-only pins. (b) control mode (alternate function) p70 to p77 are shared with ani0 to ani7, but switching is not possible. (i) ani0 to ani7 (analog input) ... input these are the analog input pins to the a/d converter (adc). (7) p90 to p915 (port 9) ... i/o port 9 is a 16-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p90 to p915 can also be used for lower 16-bit address output within a 22-bit address on the address bus during external access in control mode 1, and for serial interface (uart1, csi01, csia1) i/o, 16-bit timer i/o, 8-bit timer output, and external interrupt request input in control mode 2. moreover, they can also function as 16-bit timer inputs, 8-bit timer inputs, and key interrupts in the input port mode. the port mode and control mode (alternate functions) can be selected as the operation mode for each bit, and are specified by the port 9 mode control register (pmc9). p90 to p915 can be set to control mode 1 or control mode 2 in 1-bit units by the port 9 function control register (pfc9). normal output or n-ch open-drain output can be selected for p98, p99, p911, and p912. (a) port mode p90 to p915 can be set to input or output in 1-bit units by the port 9 mode register (pm9) (when used as the a0 to a15 pins, mode switching in 16-bit units is necessary). (b) control mode (alternate function) p90 to p915 can be set to the port mode or control mode in 1-bit units by the port 9 mode control register (pmc9). (i) a0 to a15 (address bus) ... output these are the lower 16-bit address output pins within a 22-bit address on the address bus during external access. (ii) txd1 (transmit data) ... output this is the serial transmit data output pin for uart1. (iii) rxd1 (receive data) ... input this is the serial receive data input pin for uart1. chapter 2 pin functions user?s manual u15862ej3v0ud 78 (iv) ti020, ti021, ti030, ti031 (timer input) ... input these are the external count clock input pins for the 16-bit timer. (v) to02, to03 (timer output) ... output these are the pulse signal output pins for the 16-bit timer. (vi) ti51 (timer input) ... input this is the external count clock input pin for the 8-bit timer. (vii) to51 (timer output) ... output this is the pulse signal output pin for the 8-bit timer. (viii) so01, soa1 (serial output) ... output these are the serial transmit data output pins for csi01 and csia1. (ix) si01, sia1 (serial input) ... input these are the serial receive data input pins for csi01 and csia1. (x) csk01, scka1 (serial clock) ... i/o these are the serial clock i/o pins for csi01 and csia1. (ix) intp4 to intp6 (interrupt request from peripherals) ... input these are the external interrupt request input pins. (iix) kr6, kr7 (key return) ... input these are the key interrupt input pins. their operation is specified by the key return mode register (krm) in the input port mode. (8) pcm0 to pcm3 (port cm) ... i/o port cm is a 4-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, pcm0 to pcm3 can also be used for wait insertion signal input, internal system clock output, and bus hold control signal i/o in the control mode. the port mode and control mode can be selected as the operation mode for each bit, and are specified by the port cm mode control register (pmccm). (a) port mode pcm0 to pcm3 can be set to input or output in 1-bit units by the port cm mode register (pmcm). (b) control mode pcm0 to pcm3 can be set to the port mode or control mode in 1-bit units by the pmccm register. (i) wait (wait) ... input this is a control signal input pin that inserts data waits in a bus cycle. this pin supports asynchronous input for clkout. in the multiplex mode, sampling starts at the falling edge of the clkout signal in the t2 and tw states of the bus cycle. in the separate mode, sampling starts at the rising edge of the clkout signal in the t1 and tw states of the bus cycle. if the setup/hold times in the sampling timing are not satisfied, wait insertion may not be performed. chapter 2 pin functions user?s manual u15862ej3v0ud 79 (ii) clkout (clock output) ... output this is the internal system clock output pin. since it is in the port mode during the reset period, output is not performed from the clkout pin. to perform clkout output, set this pin to the control mode with the port cm mode control register (pmccm). (iii) hldak (hold acknowledge) ... output this is the output pin for the acknowledge signal that indicates that the v850es/kg1 has received a bus hold request and set the external address/data bus and the strobe pins to high impedance. when this signal is active, the external address/data bus and the strobe pins are in high impedance, and the bus mastership is handed to the external bus master. (iv) hldrq (hold request) ... input this is the input pin by which an external device requests the v850es/kg1 to release the external address/data bus and strobe pins. this pin supports asynchronous input for clkout. when this pin is active, the external address/data bus and strobe pins are set to high impedance either when the v850es/kg1 completes execution of the current bus cycle, or immediately if no bus cycle is being executed. the hldak signal is then made active and the bus is released. to ensure that the bus hold state is entered, keep the hldrq signal active until the hldak signal is output. (9) pcs0, pcs1 (port cs) ... i/o port cs is a 2-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as a port, pcs0 and pcs1 can also be used for chip select signal output when the memory is expanded externally in the control mode. the port mode and control mode can be selected as the operation mode for each bit, and are specified by the port cs mode control register (pmccs). (a) port mode pcs0 and pcs1 can be set to input or output in 1-bit units by the port cs mode register (pmcs). (b) control mode pcs0 and pcs1 can be set to the port mode or control mode in 1-bit units by the pmccs register. (i) cs0, cs1 (chip select) ... output these are the chip select signals for external memory and external peripheral i/os. signal csn is allocated to memory block n (n = 0, 1). these pins become active when a bus cycle for accessing the corresponding memory block is started. in the idle state (ti), these pins are inactive. (10) pct0, pct1, pct4, pct6 (port ct) ... i/o port ct is a 4-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as a port, pct0, pct1, pct4, and pct6 can also be used for control signal output when the memory is expanded externally in the control mode. the port mode and control mode can be selected as the operation mode for each bit, and are specified by the port ct mode control register (pmcct). chapter 2 pin functions user?s manual u15862ej3v0ud 80 (a) port mode pct0, pct1, pct4, and pct6 can be set to input or output in 1-bit units by the port ct mode register (pmct). (b) control mode pct0, pct1, pct4, and pct6 can be set to the port mode or control mode in 1-bit units by the pmcct register. (i) wr0 (lower byte write strobe) ... output this is the write strobe signal output pin for the lower data of the external 16-bit data bus. (ii) wr1 (upper byte write strobe) ... output this is the write strobe signal output pin for the higher data of the external 16-bit data bus. (iii) rd (read strobe) ... output this is the strobe signal that indicates that the bus cycle currently being executed is a read cycle for the external memory or external peripheral i/o. in the idle state (ti), this pin is inactive. (iv) astb (address strobe) ... output this is the latch strobe signal output pin for the external address bus. the output becomes low level in synchronization with the falling edge of the clock in the t1 state of the bus cycle, and becomes high level in synchronization with the falling edge of the clock in the t3 state. (11) pdh0 to pdh5 (port dh) ... i/o port dh is a 6-bit i/o port that can be set to input or output in 1-bit units. in addition to functioning as a port, pdh0 to pdh5 can also be used as an address bus (a16 to a21) when the memory is expanded externally in the control mode (external expansion mode). the port mode and control mode can be selected as the operation mode for each bit note , and are specified by the port dh mode control register (pmcdh). note when specifying the port mode/control mode (alternate function) for each bit, pay careful attention to the operation of the alternate functions. (a) port mode pdh0 to pdh5 can be set to input or output in 1-bit units by the port dh mode register (pmdh). (b) control mode pdh0 to pdh5 can be used as a16 to a21 by the pmcdh register. (i) a16 to a21 (address bus) ... output these are the higher 6-bit address output pins within a 22-bit address on the address bus during external access. (12) pdl0 to pdl15 (port dl) ... i/o port dl is a 16-bit i/o port that can be set to input or output in 1-bit units. chapter 2 pin functions user?s manual u15862ej3v0ud 81 in addition to functioning as a port, pdl0 to pdl15 can also be used as an address/data bus in the multiplex mode and as a data bus in the separate mode when the memory is expanded externally in the control mode (external expansion mode). the port mode and control mode can be selected as the operation mode for each bit note , and are specified by the port dl mode control register (pmcdl). note when specifying the port mode/control mode (alternate function) for each bit, pay careful attention to the operation of the alternate functions. (a) port mode pdl0 to pdl15 can be set to input or output in 1-bit units by the port dl mode register (pmdl). (b) control mode pdl0 to pdl15 can be used as ad0 to ad15 by the pmcdl register. (i) ad0 to ad15 (address/data bus) ... i/o this is a multiplexed address/data bus during external access. in the address timing (t1 state), these pins function as 22-bit address a0 to a15 output pins, and in the data timing (t2, tw, and t3), they function as 16-bit data i/o bus pins. (13) reset (reset) ... input reset input is an asynchronous input, and when a signal that has a certain low-level width is input, regardless of the operation clock, system reset is executed with priority over all other actions. in addition to normal initialize and start, reset can also be used to release the standby mode (halt, idle, and stop). (14) regc (regulator control) ... input this is the pin for connecting a capacitor for the regulator. (15) x1, x2 (crystal for main clock) these pins are used to connect the resonator that generates the main clock. an external clock can also be input. (16) xt1, xt2 (crystal for subclock) these pins are used to connect the resonator that generates the subclock. (17) av ss (ground for analog) this is the ground pin for the a/d converter and d/a converter. (18) av ref0 (analog reference voltage) ... input this is the pin for supplying the reference voltage for the a/d converter. (19) av ref1 (analog reference voltage) ... input this is the pin for supplying the reference voltage for the d/a converter. (20) bv dd (power supply for bus interface) this is the positive power supply pin for the bus interface. chapter 2 pin functions user?s manual u15862ej3v0ud 82 (21) bv ss (ground for bus interface) this is the ground pin for the bus interface. (22) ev dd (power supply for ports) this is the power supply pin for the peripheral interface. (23) ev ss (ground for ports) this is the ground pin for the peripheral interface. (24) v dd (power supply) these are the positive power supply pins. all v dd pins should be connected to a positive power supply. (25) v pp (programming power supply) this is the positive power supply pin used for the flash memory programming mode. it is provided for products with flash memory. during normal mode operation, connect this pin to v ss . (26) v ss (ground) these are the ground pins. connect all v ss pins to a positive power supply. (27) ic (internally connected) this is an internally connected pin. connect this pin directly to v ss in the normal operation mode. chapter 2 pin functions user?s manual u15862ej3v0ud 83 2.3.3 v850es/kj1 (1) p00 to p06 (port 0) ... i/o port 0 is a 7-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p00 to p06 can also be used for nmi input, external interrupt request input, and timer h output in the control mode. the port mode and control mode (alternate functions) can be selected as the operation mode for each bit, and are specified by the port 0 mode control register (pmc0). (a) port mode p00 to p06 can be set to input or output in 1-bit units by the port 0 mode register (pm0). (b) control mode (alternate function) p00 to p06 can be set to the port mode or control mode in 1-bit units by the port 0 mode control register (pmc0). (i) nmi (non-maskable interrupt request) ... input this is a non-maskable interrupt request input pin. (ii) intp0 to intp3 (interrupt request from peripherals) ... input these are external interrupt request input pins. (iii) toh0, toh1 (timer output) ... output these are timer h pulse signal output pins. (2) p10, p11 (port 1) ... i/o port 1 is a 2-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p10 and p11 can also be used for d/a converter analog output. the port mode and control mode cannot be selected as the operation mode for each bit. to use these pins as d/a converter analog output pins, set the port 1 mode register (pm1) to output (03h). (a) port mode p10 and p11 can be set to input or output in 1-bit units by the port 1 mode register (pm1). (i) ano0, ano1 (analog output) ... output these are analog output pins to the d/a converter (dac). (3) p30 to p39 (port 3) ... i/o port 3 is a 10-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p30 to p39 can also be used for serial interface (uart0, i 2 c0) i/o and 16-bit timer input in control mode 1, and for 16-bit timer output in control mode 2. the port mode and control mode can be selected as the operation mode for each bit, and are specified by the port 3 mode control register (pmc3). p33 and p35 can be set to control mode 1 or control mode 2 in 1-bit units by the port 3 function control register (pfc3). when used as outputs, p36 to p39 are fixed to n-ch open-drain output. (a) port mode p30 to p39 can be set to input or output in 1-bit units by the port 3 mode register (pm3). chapter 2 pin functions user?s manual u15862ej3v0ud 84 (b) control mode p30 to p39 can be set to the port mode or control mode in 1-bit units by the port 3 mode control register (pmc3). p33 and p35 can be set to control mode 1 or control mode 2 in 1-bit units by the port 3 function control register (pfc3). (i) txd0 (transmit data) ... output this is the serial transmit data output pin for uart0. (ii) rxd0 (receive data) ... input this is the serial receive data input pin for uart0. (iii) asck0 (asynchronous serial clock) ... input this is the serial baud rate clock input pin for uart0. (iv) ti000, ti001, ti010 (timer input) ... input these are the external count clock input pins for the 16-bit timer. (v) to00, to01 (timer output) ... output these are the pulse signal output pins for the 16-bit timer. (vi) sda0 (serial data) ... i/o this is the serial transmit/receive data i/o pin for i 2 c0 (only for the pd703216y, 703217y, and 70f3217y). (vii) scl0 (serial clock) ... i/o this is the serial clock i/o pin for i 2 c0 (only for the pd703216y, 703217y, and 70f3217y). (4) p40 to p42 (port 4) ... i/o port 4 is a 3-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p40 to p42 can also be used for serial interface (csi00) i/o in the control mode. the port mode and control mode can be selected as the operation mode for each bit, and are specified by the port 4 mode control register (pmc4). normal output and n-ch open-drain output can be selected for p41 and p42. (a) port mode p40 to p42 can be set to input or output in 1-bit units by the port 4 mode register (pm4). (b) control mode p40 to p42 can be set to the port mode or control mode in 1-bit units by the pmc4 register. (i) so00 (serial output) ... output this is the serial transmit data output pin for csi00. (ii) si00 (serial input) ... input this is the serial receive data input pin for csi00. chapter 2 pin functions user?s manual u15862ej3v0ud 85 (iii) sck00 (serial clock) ... i/o this is the serial clock i/o pin for csi00. (5) p50 to p55 (port 5) ... i/o port 5 is a 6-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p50 to p55 can also be used as 16-bit timer input, 8-bit timer i/o, and serial interface (csia0) i/o pins in control mode 1, and as real-time output port pins in control mode 2. they can also be used for key interrupt input by setting key return mode register (krm) while in the input port mode. the port mode and control mode (alternate functions) can be selected as the operation mode in 1-bit units, and are specified by the port 5 mode control register (pmc5). p50 to p55 can be set to control mode 1 or control mode 2 in 1-bit units by the port 5 function control register (pfc5). normal output and n-ch open-drain output can be selected for p54 and p55. (a) port mode p50 to p55 can be set to input or output in 1-bit units by the port 5 mode register (pm5). (b) control mode (alternate function) p50 to p55 can be set to the port mode or control mode in 1-bit units by the port 5 mode control register (pmc5). (i) ti011 (timer input) ... input this is the external count clock input pin for the 16-bit timer. (ii) ti50 (timer input) ... input this is the external count clock input pin for the 8-bit timer. (iii) to50 (timer output) ... output this is the pulse signal output pin for the 8-bit timer. (iv) soa0 (serial output) ... output this is the csia0 serial transmit data output pin. (v) sia0 (serial input) ... input this is the csia0 serial receive data input pin. (vi) scka0 (serial clock) ... i/o this is the csia0 serial clock i/o pin. (vii) rtp00 to rtp05 (real-time output port) ... output these pins operate as a real-time output port. (viii) kr0 to kr5 (key return) ... input these are the key interrupt input pins. their operation is specified by the key return mode register (krm) in the input port mode. chapter 2 pin functions user?s manual u15862ej3v0ud 86 (6) p60 to p615 (port 6) ... i/o port 6 is a 16-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p60 to p615 can also be used for real-time output port function, serial interface (csi02) i/o, and 16-bit timer i/o in control mode 1, and for 16-bit timer output in control mode 2. the port mode and control mode (alternate functions) can be selected as the operation mode for each bit, and are specified by the port 6 mode control register (pmc6). p613 can be set to control mode 1 or control mode 2 in 1-bit units by the port 6 function control register (pfc6). normal output or n-ch open-drain output can be selected for p67 and p68. (a) port mode p60 to p615 can be set to input or output in 1-bit units by the port 6 mode register (pm6). (b) control mode (alternate function) p60 to p615 can be set to the port mode or control mode in 1-bit units by the port 6 mode control register (pmc6). (i) rtp10 to rtp15 (real-time output port) ... output these pins operate as a real-time output port. (ii) so02 (serial output) ... output this is the serial transmit data output pin for csi02. (iii) si02 (serial input) ... input this is the serial receive data input pin for csi02. (iv) sck02 (serial clock) ... i/o this is the serial clock i/o pin for csi02. (v) ti040, ti041, ti050, ti051 (timer input) ... input these are the external count clock input pins for the 16-bit timer. (vi) to04, to05 (timer output) ... output these are the pulse signal output pins for the 16-bit timer. (7) p70 to p715 (port 7) ... input port 7 is a 16-bit input-only port in which all the pins are fixed to input. in addition to functioning as an input port, p70 to p715 can also be used as a/d converter (adc) analog input pins in the control mode. normally, when port and function pins are shared, their operation can be selected by the port mode control register, but in the case of p70 to p715, such a register does not exist. therefore, these pins cannot be switched between input port and analog input pins for the a/d converter (adc). for the state of each pin, read the port. (a) port mode p70 to p715 are input-only pins. chapter 2 pin functions user?s manual u15862ej3v0ud 87 (b) control mode (alternate function) p70 to p715 are shared with ani0 to ani15, but switching is not possible. (i) ani0 to ani15 (analog input) ... input these are the analog input pins to the a/d converter (adc). (8) p80, p81 (port 8) ... input port 8 is a 2-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p80 and p81 can also be used for serial interface (uart2) i/o in control mode 1, and for serial interface (i 2 c1) i/o in control mode 2. the port mode and control mode (alternate functions) can be selected as the operation mode for each bit, and are specified by the port 8 mode control register (pmc8). p80 and p81 can be set to control mode 1 or control mode 2 in 1-bit units by the port 8 function control register (pfc8). (a) port mode p80 and p81 can be set to input or output in 1-bit units by the port 8 mode register (pm8). (b) control mode (alternate function) p80 and p81 can be set to the port mode or control mode in 1-bit units by the port 8 mode control register (pmc8). (i) txd2 (transmit data) ... output this is the serial transmit data output pin for uart2. (ii) rxd2 (receive data) ... input this is the serial receive data input pin for uart2. (iii) sda1 (serial data) ... i/o this is the serial transmit/receive data i/o pin for i 2 c1 (only for the pd703216y, 703217y, and 70f3217y). (iv) scl1 (serial clock) ... i/o this is the serial clock i/o pin for i 2 c1 (only for the pd703216y, 703217y, and 70f3217y). (9) p90 to p915 (port 9) ... i/o port 9 is a 16-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, p90 to p915 can also be used for lower 16-bit address output within a 24-bit address on the address bus during external access in control mode 1, and for serial interface (uart1, csi01, csia1) i/o, 16-bit timer i/o, 8-bit timer output, and external interrupt request input in control mode 2. moreover, they can also function as 16-bit timer inputs, 8-bit timer inputs, and key interrupt inputs in the input port mode. the port mode and control mode (alternate functions) can be selected as the operation mode for each bit, and are specified by the port 9 mode control register (pmc9). p90 to p915 can be set to control mode 1 or control mode 2 in 1-bit units by the port 9 function control register (pfc9). normal output or n-ch open-drain output can be selected for p98, p99, p911, and p912. chapter 2 pin functions user?s manual u15862ej3v0ud 88 (a) port mode p90 to p915 can be set to input or output in 1-bit units by the port 9 mode register (pm9). (b) control mode (alternate function) p90 to p915 can be set to the port mode or control mode in 1-bit units by the port 9 mode control register (pmc9) (when used as the a0 to a15 pins, mode switching in 16-bit units is necessary). (i) a0 to a15 (address bus) ... output these are the lower 16-bit address output pins within a 24-bit address on the address bus during external access. (ii) txd1 (transmit data) ... output this is the serial transmit data output pin for uart1. (iii) rxd1 (receive data) ... input this is the serial receive data input pin for uart1. (iv) ti020, ti021, ti030, ti031 (timer input) ... input these are the external count clock input pins for the 16-bit timer. (v) to02, to03 (timer output) ... output these are the pulse signal output pins for the 16-bit timer. (vi) ti51 (timer input) ... input this is the external count clock input pin for the 8-bit timer. (vii) to51 (timer output) ... output this is the pulse signal output pin for the 8-bit timer. (viii) so01, soa1 (serial output) ... output these are the serial transmit data output pins for csi01 and csia1. (ix) si01, sia1 (serial input) ... input these are the serial receive data input pins for csi01 and csia1. (x) csk01, scka1 (serial clock) ... i/o these are the serial clock i/o pins for csi01 and csia1. (ix) intp4 to intp6 (interrupt request from peripherals) ... input these are the external interrupt request input pins. (iix) kr6, kr7 (key return) ... input these are the key interrupt input pins. their operation is specified by the key return mode register (krm) in the input port mode. chapter 2 pin functions user?s manual u15862ej3v0ud 89 (10) pcd0 to pcd3 (port cd) ... i/o port cd is a 4-bit i/o port for which input and output can be set in 1-bit units. pcd0 to pcd3 operate as an i/o port. (a) port mode pcd0 to pcd3 can be set to input or output in 1-bit units by the port cd mode register (pmcd). (11) pcm0 to pcm5 (port cm) ... i/o port cm is a 6-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as an i/o port, pcm0 to pcm5 can also be used for wait insertion signal input, internal system clock output, and bus hold control signal i/o in the control mode. the port mode and control mode can be selected as the operation mode for each bit, and are specified by the port cm mode control register (pmccm). (a) port mode pcm0 to pcm5 can be set to input or output in 1-bit units by the port cm mode register (pmcm). (b) control mode pcm0 to pcm5 can be set to the port mode or control mode in 1-bit units by the pmccm register. (i) wait (wait) ... input this is a control signal input pin that inserts data waits in a bus cycle. this pin supports asynchronous input for clkout. in the multiplex mode, sampling starts at the falling edge of the clkout signal in the t2 and tw states of the bus cycle. in the separate mode, sampling starts at the rising edge of the clkout signal in the t1 and tw states of the bus cycle. if the setup/hold times in the sampling timing are not satisfied, wait insertion may not be performed. (ii) clkout (clock output) ... output this is the internal system clock output pin. since it is in the port mode during the reset period, output is not performed from the clkout pin. to perform clkout output, set this pin to the control mode by the port cm mode control register (pmccm). (iii) hldak (hold acknowledge) ... output this is the output pin for the acknowledge signal that indicates that the v850es/kj1 has received a bus hold request and set the external address/data bus and the strobe pins to high impedance. when this signal is active, the external address/data bus and the strobe pins are in high impedance, and the bus mastership is handed to the external bus master. (iv) hldrq (hold request) ... input this is the input pin by which an external device requests the v850es/kj1 to release the external address/data bus and strobe pins. this pin supports asynchronous input for clkout. when this pin is active, the external address/data bus and strobe pins are set to high impedance either when the v850es/kj1 completes execution of the current bus cycle, or immediately if no bus cycle is being executed. the hldak signal is then made active and the bus is released. to ensure that the bus hold state is entered, keep the hldrq signal active until the hldak signal is output. chapter 2 pin functions user?s manual u15862ej3v0ud 90 (12) pcs0 to pcs7 (port cs) ... i/o port cs is an 8-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as a port, pcs0 to pcs7 can also be used for chip select signal output when the memory is expanded externally in the control mode. the port mode and control mode can be selected as the operation mode for each bit, and are specified by the port cs mode control register (pmccs). (a) port mode pcs0 to pcs7 can be set to input or output in 1-bit units by the port cs mode register (pmcs). (b) control mode pcs0 to pcs7 can be set to the port mode or control mode in 1-bit units by the pmccs register. (i) cs0 to cs3 (chip select) ... output these are the chip select signals for external memory and external peripheral i/os. signal csn is allocated to memory block n (n = 0 to 3). these pins become active when a bus cycle for accessing the corresponding memory block is started. in the idle state (ti), these pins are inactive. (13) pct0 to pct7 (port ct) ... i/o port ct is an 8-bit i/o port for which input and output can be set in 1-bit units. in addition to functioning as a port, pct0 to pct7 can also be used for control signal output when the memory is expanded externally in the control mode. the port mode and control mode can be selected as the operation mode for each bit, and are specified by the port ct mode control register (pmcct). (a) port mode pct0 to pct7 can be set to input or output in 1-bit units by the port ct mode register (pmct). (b) control mode pct0 to pct7 can be set to the port mode or control mode in 1-bit units by the pmcct register. (i) wr0 (lower byte write strobe) ... output this is the write strobe signal output pin for the lower data of the external 16-bit data bus. (ii) wr1 (upper byte write strobe) ... output this is the write strobe signal output pin for the higher data of the external 16-bit data bus. (iii) rd (read strobe) ... output this is the strobe signal that indicates that the bus cycle currently being executed is a read cycle for the external memory or external peripheral i/o. in the idle state (ti), this pin is inactive. (iv) astb (address strobe) ... output this is the latch strobe signal output pin for the external address bus. the output becomes low level in synchronization with the falling edge of the clock in the t1 state of the bus cycle, and becomes high level in synchronization with the falling edge of the clock in the t3 state. chapter 2 pin functions user?s manual u15862ej3v0ud 91 (14) pdh0 to pdh7 (port dh) ... i/o port dh is an 8-bit i/o port that can be set to input or output in 1-bit units. in addition to functioning as a port, pdh0 to pdh7 can also be used as an address bus (a16 to a23) when the memory is expanded externally in the control mode (external expansion mode). the port mode and control mode can be selected as the operation mode for each bit note , and are specified by the port dh mode control register (pmcdh). note when specifying the port mode/control mode (alternate function) for each bit, pay careful attention to the operation of the alternate functions. (a) port mode pdh0 to pdh7 can be set to input or output in 1-bit units by the port dh mode register (pmdh). (b) control mode pdh0 to pdh7 can be used as a16 to a23 by the pmcdh register. (i) a16 to a23 (address bus) ... output these are the higher 8-bit address output pins within a 24-bit address on the address bus during external access. (15) pdl0 to pdl15 (port dl) ... i/o port dl is a 16-bit i/o port that can be set to input or output in 1-bit units. in addition to functioning as a port, pdl0 to pdl15 can also be used as an address/data bus in the multiplex mode and as a data bus in the separate mode when the memory is expanded externally in the control mode (external expansion mode). the port mode and control mode can be selected as the operation mode for each bit note , and are specified by the port dl mode control register (pmcdl). note when specifying the port mode/control mode (alternate function) for each bit, pay careful attention to the operation of the alternate functions. (a) port mode pdl0 to pdl15 can be set to input or output in 1-bit units by the port dl mode register (pmdl). (b) control mode pdl0 to pdl15 can be used as ad0 to ad15 by the pmcdl register. (i) ad0 to ad15 (address/data bus) ... i/o this is a multiplexed address/data bus during external access. in the address timing (t1 state), these pins function as 24-bit address a0 to a15 output pins, and in the data timing (t2, tw, and t3), they function as 16-bit data i/o bus pins. (16) reset (reset) ... input reset input is an asynchronous input, and when a signal that has a certain low-level width is input, regardless of the operation clock, system reset is executed with priority over all other actions. in addition to normal initialize and start, reset can also be used to release the standby mode (halt, idle, and stop). chapter 2 pin functions user?s manual u15862ej3v0ud 92 (17) regc (regulator control) ... input this is the pin for connecting a capacitor for the regulator. (18) x1, x2 (crystal for main clock) these pins are used to connect the resonator that generates the main clock. an external clock can also be input. (19) xt1, xt2 (crystal for subclock) these pins are used to connect the resonator that generates the subclock. (20) av ss (ground for analog) this is the ground pin for the a/d converter and d/a converter. (21) av ref0 (analog reference voltage) ... input this is the pin for supplying the reference voltage for the a/d converter. (22) av ref1 (analog reference voltage) ... input this is the pin for supplying the reference voltage for the d/a converter. (23) bv dd (power supply for bus interface) this is the positive power supply pin for the bus interface. (24) bv ss (ground for bus interface) this is the ground pin for the bus interface. (25) ev dd (power supply for ports) this is the power supply pin for the peripheral interface. (26) ev ss (ground for ports) this is the ground pin for the peripheral interface. (27) v dd (power supply) these are the positive power supply pins. all v dd pins should be connected to a positive power supply. (28) v pp (programming power supply) this is the positive power supply pin used for the flash memory programming mode. it is provided for products with flash memory. during normal mode operation, connect this pin to v ss . (29) v ss (ground) these are the ground pins. connect all v ss pins to a positive power supply. (30) ic (internally connected) this is an internally connected pin. connect this pin directly to v ss in the normal operation mode. chapter 2 pin functions user?s manual u15862ej3v0ud 93 2.4 pin i/o circuits and recommended connection of unused pins (1/3) pin alternate function i/o circuit type recommended connection product p00 toh0 p01 toh1 5-a p02 nmi p03 to p06 intp0 to intp3 5-w input: independently connect to ev dd or ev ss via a resistor. output: leave open. all products p10 ano0 p11 ano1 12-b input: independently connect to av ref1 or av ss via a resistor. output: leave open. kg1, kj1 p30 txd0 5-a p31 rxd0 p32 asck0 p33 ti000/to00 p34 ti001 p35 ti010/to01 5-w all products p36, p37 ? 13-b kg1, kj1 p38 sda0 note p39 scl0 note 13-ae all products p40 si00 5-w p41 so00 10-e p42 sck00 10-f all products p50 ti011/rtp00/kr0 p51 ti50/rtp01/kr1 p52 to50/rtp02/kr2 p53 sia0/rtp03/kr3 8-a p54 soa0/rtp04/kr4 p55 scka0/rtp05/kr5 10-a all products p60 to p65 rtp10 to rtp15 5-a p66 si02 5-w p67 so02 10-e p68 sck02 10-f p69 ti040 p610 ti041 5-w p611 to04 5-a p612 ti050 p613 ti051/to05 5-w p614, p615 ? 13-b input: independently connect to ev dd or ev ss via a resistor. output: leave open kj1 p70 to p77 ani0 to ani7 all products p78 to p715 ani8 to ani15 9-c connect to av ref0 or av ss . kj1 note only for products with an i 2 c bus. remark kg1: v850es/kg1, kj1: v850es/kj1 chapter 2 pin functions user?s manual u15862ej3v0ud 94 (2/3) pin alternate function i/o circuit type recommended connection product p80 rxd2/sda1 note p81 txd2/scl1 note 10-f kj1 p90 a0/txd1/kr6 p91 a1/rxd1/kr7 all products p92 a2/ti020/to02 8-a p93 a3/ti021 5-w p94 a4/ti030/to03 8-a p95 a5/ti031 5-w kg1, kj1 p96 a6/ti51/to51 8-a p97 a7/si01 5-w p98 a8/so01 10-e p99 a9/sck01 10-f all products p910 a10/sia1 5-w p911 a11/soa1 10-e p912 a12/scka1 10-f kg1, kj1 p913 a13/intp4 5-w p914, p915 a14/intp5, a15/intp6 8-a input: independently connect to ev dd or ev ss via a resistor. output: leave open. all products pcd0 to pcd3 ? 5 kj1 pcm0 wait pcm1 clkout pcm2 hldak pcm3 hldrq all products pcm4,pcm5 ? 5 kj1 pcs0, pcs1 cs0, cs1 all products pcs2, pcs3 cs2, cs3 pcs4 to pcs7 ? 5 kj1 pct0 wr0 pct1 wr1 all products pct2,pct3 ? kj1 pct4 rd all products pct5 ? kj1 pct6 astb all products pct7 ? 5 kj1 pdl0 to pdl15 ad0 to ad15 5 all products pdh0 to pdh5 a16 to a21 kg1, kj1 pdh6, pdh7 a22, a23 5 input: independently connect to bv dd or bv ss via a resistor. (for the v850es/kf1, independently connect to ev dd or ev ss via a resistor.) output: leave open kj1 av ref0 ? ? directly connect to v dd . all products av ref1 ? ? directly connect to v dd . kg1, kj1 av ss ? ? ? all products note only for the pd703216y, 703217y, and 70f3217y remark kg1: v850es/kg1, kj1: v850es/kj1 chapter 2 pin functions user?s manual u15862ej3v0ud 95 (3/3) pin alternate function i/o circuit type recommended connection target product bv dd ?? ? kg1, kj1 bv ss ?? ? kg1, kj1 ev dd ? ? ? all products ev ss ? ? ? all products ic note 1 ?? directly connect to ev ss or v ss or pull down with a 10 k ? resistor. all products reset ? 2 ? all products v pp note 2 ? ? directly connect to ev ss or v ss or pull down with a 10 k ? resistor. all products v dd ? ? ? all products v ss ? ? ? all products x1 ? ? ? all products x2 ? ? ? all products xt1 ? 16 directly connect to v ss . all products xt2 ? 16 leave open. all products notes 1. only for products with a mask rom 2. only for products with flash memory remark kg1: v850es/kg1, kj1: v850es/kj1 chapter 2 pin functions user?s manual u15862ej3v0ud 96 2.5 pin i/o circuits (1/2) type 2 type 8-a type 5 type 9-c type 5-a type 10-a type 5-w type 10-e schmitt-triggered input with hysteresis characteristics in data output disable p-ch in/out v dd n-ch input enable data output disable p-ch in/out v dd n-ch input enable p-ch v dd pullup enable in comparator + ? av ref0 (threshold voltage) p-ch n-ch input enable pullup enable data output disable v dd p-ch v dd p-ch in/out n-ch pullup enable data output disable input enable v dd p-ch v dd p-ch in/out n -ch data output disable v dd p-ch in/out n-ch open drain pullup enable v dd p-ch data output disable v dd p-ch in/out n-ch open drain input enable pullup enable v dd p-ch chapter 2 pin functions user ? s manual u15862ej3v0ud 97 (2/2) type 10-f type 13-b type 12-b type 13-ae type 16 output disable in/out n-ch data medium-voltage input buffer mask option v dd v dd p-ch rd v ss p-ch feedback cut-off xt1 xt2 data output disable v dd p-ch in/out n-ch open drain input enable pullup enable v dd p-ch pullup enable data output disable input enable av ref1 p-ch av ref1 p-ch in/out n-ch p-ch n-ch analog output voltage av ss data output disable input enable in/out n -ch v ss mask option v dd user?s manual u15862ej3v0ud 98 chapter 3 cpu functions the cpu of the v850es/kf1, v850es/kg1, and v850es/kj1 is based on the risc architecture and executes most instructions in one clock cycle by using a 5-stage pipeline control. 3.1 features { number of instructions: 83 { minimum instruction execution time: 50.0 ns (@ 20 mhz operation, 4.5 to 5.5 v, not using regulator) 62.5 ns (@ 16 mhz operation, 4.0 to 5.5 v, using regulator) 100 ns (@ 10 mhz operation: 2.7 to 5.5 v, not using regulator) { memory space program space: 64 mb linear data space: 4 gb linear ? memory block division function: 2 mb, 64 kb/total of 2 blocks (v850es/kf1) : 2 mb, 2 mb/total of 2 blocks (v850es/kg1) : 2 mb, 2 mb, 4 mb, 8 mb/total of 4 blocks (v850es/kj1) { general-purpose registers: 32 bits 32 { internal 32-bit architecture { 5-stage pipeline control { multiply/divide instructions { saturated operation instructions { 32-bit shift instruction: 1 clock { load/store instruction with long/short format { four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1 chapter 3 cpu functions user?s manual u15862ej3v0ud 99 3.2 cpu register set the cpu registers of the v850es/kf1, v850es/kg1 and v850es/kj1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. all the registers have 32-bit width. for details, refer to the v850es architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (nmi status saving register) (nmi status saving register) eipc eipsw (interrupt status saving register) (interrupt status saving register) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (exception/debug trap status saving register) (exception/debug trap status saving register) ctpc ctpsw (callt execution status saving register) (callt execution status saving register) chapter 3 cpu functions user ? s manual u15862ej3v0ud 100 3.2.1 program register set the program register set includes general-purpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are available. all of these registers can be used as a data variable or address variable. however, r0 and r30 are implicitly used by instructions and care must be exercised when using these registers. r0 always holds 0 and is used for operations that use 0 and offset 0 addressing. r30 is used as a base pointer when performing memory access with the sld and sst instructions. also, r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. therefore, before using these registers, their contents must be saved so that they are not lost, and they must be restored to the registers after the registers have been used. there are cases when r2 is used by the real-time os. if r2 is not used by the real-time os, r2 can be used as a variable register. table 3-1. program registers name usage operation r0 zero register always holds 0 r1 assembler-reserved register working register for generating 32-bit immediate r2 address/data variable register (when r2 is not used by the real-time os to be used) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to access global variable in data area r5 text pointer register to indicate the start of the text area (area for placing program code) r6 to r29 address/data variable register r30 element pointer base pointer when memory is accessed r31 link pointer used by compiler when calling function pc program counter holds instruction address during program execution (2) program counter (pc) this register holds the address of the instruction under execution. the lower 26 bits of this register are valid, and bits 31 to 26 are fixed to 0. if a carry occurs from bit 25 to bit 26, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. 31 26 25 1 0 pc fixed to 0 instruction address under execution 0 after reset 00000000h chapter 3 cpu functions user ? s manual u15862ej3v0ud 101 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (ldsr, stsr instructions). table 3-2. system register numbers operand specification enabled register no. system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 yes yes 1 interrupt status saving register (eipsw) note 1 yes yes 2 nmi status saving register (fepc) note 1 yes yes 3 nmi status saving register (fepsw) note 1 yes yes 4 interrupt source register (ecr) no yes 5 program status word (psw) yes yes 6 to 15 reserved numbers for future function expansion (the operation is not guaranteed if accessed.) no no 16 callt execution status saving register (ctpc) yes yes 17 callt execution status saving register (ctpsw) yes yes 18 exception/debug trap status saving register (dbpc) yes note 2 yes 19 exception/debug trap status saving register (dbpsw) yes note 2 yes 20 callt base pointer (ctbp) yes yes 21 to 31 reserved numbers for future function expansion (the operation is not guaranteed if accessed.) no no notes 1. since only one set of these registers is available, the contents of this register must be saved by the program when multiple interrupt servicing is enabled. 2. can be accessed only during dbtrap instruction execution. caution even if bit 0 of eipc, fepc, or ctpc is set to (1) by the ldsr instruction, bit 0 is ignored during return with the reti instruction following interrupt servicing (because bit 0 of pc is fixed to 0). if setting a value to eipc, fepc, and ctpc, set an even number (bit 0 = 0). chapter 3 cpu functions user ? s manual u15862ej3v0ud 102 (1) interrupt status saving registers (eipc, eipsw) there are two interrupt status saving registers, eipc and eipsw. upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (pc) are saved to eipc and the contents of the program status word (psw) are saved to eipsw (upon occurrence of a non-maskable interrupt (nmi), the contents are saved to the nmi status saving registers (fepc, fepsw)). the address of the next instruction following the instruction executed when a software exception or maskable interrupt occurs is saved to eipc, except for some instructions. the current psw contents are saved to eipsw. since there is only one set of interrupt status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are reserved (fixed to 0) for future function expansion. 31 0 eipc (pc contents) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (psw contents) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 chapter 3 cpu functions user ? s manual u15862ej3v0ud 103 (2) nmi status saving registers (fepc, fepsw) there are two nmi status saving registers, fepc and fepsw. upon occurrence of a non-maskable interrupt (nmi), the contents of the program counter (pc) are saved to fepc and the contents of the program status word (psw) are saved to fepsw. the address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to fepc, except for some instructions. the current psw contents are saved to fepsw. since there is only one set of nmi status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is performed. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are reserved (fixed to 0) for future function expansion. 31 0 fepc (pc contents) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (psw contents) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 (3) interrupt source register (ecr) upon occurrence of an interrupt or an exception, the interrupt source register (ecr) holds the source of an interrupt or an exception. the value held by ecr is the exception code coded for each interrupt source. this register is a read-only register, and thus data cannot be written to it using the ldsr instruction. 31 0 ecr fecc eicc after reset 00000000h 16 15 bit position bit name description 31 to 16 fecc non-maskable interrupt (nmi) exception code 15 to 0 eicc exception, maskable interrupt exception code chapter 3 cpu functions user ? s manual u15862ej3v0ud 104 (4) program status word (psw) a program status word (psw) is a collection of flags that indicate the program status (instruction execution result) and the cpu status. when the contents of this register are changed using the ldsr instruction, the new contents become valid immediately following completion of the ldsr instruction execution. however, if the id flag is set to 1, interrupt request acknowledgement during ldsr instruction execution is prohibited. bits 31 to 8 are reserved (fixed to 0) for future function expansion. (1/2) 31 0 psw rfu after reset 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name description 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that non-maskable interrupt (nmi) servicing is in progress. this flag is set to 1 when an nmi request is acknowledged, and disables multiple interrupts. 0: nmi servicing not in progress 1: nmi servicing in progress 6 ep indicates that exception processing is in progress. this flag is set to 1 when an exception occurs. moreover, interrupt requests can be acknowledged even when this bit is set. 0: exception processing not in progress 1: exception processing in progress 5 id indicates whether maskable interrupt request acknowledgment is enabled. 0: interrupt enabled 1: interrupt disabled 4 sat note indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. since this is a cumulative flag, it is set to 1 when the result of a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do not become saturated. this flag is neither set nor cleared when arithmetic operation instructions are executed. 0: not saturated 1: saturated 3cy indicates whether carry or borrow occurred as the result of an operation. 0: no carry or borrow occurred 1: carry or borrow occurred 2ov note indicates whether overflow occurred during an operation. 0: no overflow occurred 1: overflow occurred. 1s note indicates whether the result of an operation is negative. 0: operation result is positive or 0. 1: operation result is negative. 0 z indicates whether operation result is 0. 0: operation result is not 0. 1: operation result is 0. remark note is explained on the following page. chapter 3 cpu functions user ? s manual u15862ej3v0ud 105 (2/2) note during saturated operation, the saturated operation results are determined by the contents of the ov flag and s flag. the sat flag is set to 1 only when the ov flag is set to 1 during saturated operation. flag status operation result status sat ov s saturated operation result maximum positive value exceeded 1 1 0 7fffffffh maximum negative value exceeded 1 1 1 80000000h positive (maximum value not exceeded) 0 negative (maximum value not exceeded) holds value before operation 0 1 actual operation result (5) callt execution status saving registers (ctpc, ctpsw) there are two callt execution status saving registers, ctpc and ctpsw. when the callt instruction is executed, the contents of the program counter (pc) are saved to ctpc, and the program status word (psw) contents are saved to ctpsw. the contents saved to ctpc consist of the address of the next instruction after the callt instruction. the current psw contents are saved to ctpsw. bits 31 to 26 ctpc and bits 31 to 8 of ctpsw are reserved (fixed to 0) for future function expansion. 31 0 ctpc (pc contents) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (psw contents) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 chapter 3 cpu functions user ? s manual u15862ej3v0ud 106 (6) exception/debug trap status saving registers (dbpc, dbpsw) there are two exception/debug trap status saving registers, dbpc and dbpsw. upon occurrence of an exception trap or debug trap, the contents of the program counter (pc) are saved to dbpc, and the program status word (psw) contents are saved to dbpsw. the contents saved to dbpc consist of the address of the next instruction after the instruction executed when an exception trap or debug trap occurs. the current psw contents are saved to dbpsw. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are reserved (fixed to 0) for future function expansion. 31 0 dbpc (pc contents) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (psw contents) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify table addresses and generate target addresses (bit 0 is fixed to 0). bits 31 to 26 are reserved (fixed to 0) for future function expansion. 31 0 ctbp (base address) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0 chapter 3 cpu functions user ? s manual u15862ej3v0ud 107 3.3 operation modes the v850es/kf1, v850es/kg1, and v850es/kj1 have the following operating modes. (1) normal operating mode after the system has been released from the reset state, the pins related to the bus interface are set to the port mode, execution branches to the reset entry address of the internal rom, and instruction processing is started. an external device can be connected to the external memory area by setting the pmcdh, pmcdl, pmccm, pmccs, and pmcct registers to the control mode via software. (2) flash memory programming mode pd70f3210, 70f3210y: v850es/kf1 pd70f3214, 70f3214y: v850es/kg1 pd70f3217, 70f3217y: v850es/kj1 the internal flash memory can be written or erased when 10 v 0.3 v is applied to the v pp pin. v pp operating mode 0 normal operation mode 10 0.3 v flash memory programming mode v dd setting prohibited chapter 3 cpu functions user ? s manual u15862ej3v0ud 108 3.4 address space 3.4.1 cpu address space the cpu of the v850es/kf1, v850es/kg1, and v850es/kj1 uses a 32-bit architecture and supports up to 4 gb of linear address space (data space) during operand addressing (data access). when addressing instruction addresses, a linear address space (program space) of up to 64 mb is supported. however, both the program and data spaces include areas whose use is prohibited. for details, refer to figure 3-2 . figure 3-1 shows the cpu address space. figure 3-1. cpu address space ffffffffh 04000000h 03ffffffh 00000000h data area (4 gb linear) program area (64 mb linear) cpu address space chapter 3 cpu functions user ? s manual u15862ej3v0ud 109 3.4.2 image up to 16 mb of external memory area in a linear address space (program area) of up to 16 mb, internal rom area, and internal ram area are supported for instruction address addressing. during operand addressing (data access), up to 4 gb of linear address space (data space) is supported. however, the 4 gb address space is viewed as 64 images of a 64 mb physical address space. in other words, the same 64 mb physical address space is accessed regardless of the value of bits 31 to 26. figure 3-2. address space image program space internal ram area access-prohibited area reserved area external memory area internal rom area (external memory) data space image 63 image 1 image 0 on-chip peripheral i/o area internal ram area access-prohibited area external memory area internal rom area (external memory) 16 mb 4 gb 64 mb 64 mb chapter 3 cpu functions user ? s manual u15862ej3v0ud 110 3.4.3 wraparound of cpu address space (1) program space of the 32 bits of the program counter (pc), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calculation, the higher 6 bits ignore this and remain 0. therefore, the lower-limit address of the program space, 00000000h, and the upper-limit address, 03ffffffh, are contiguous addresses, and the program space is wrapped around at the boundary of these addresses. caution no instructions can be fetched from the 4 kb area of 03fff000h to 03ffffffh because this area is an on-chip peripheral i/o area. therefore, do not execute any branch operation instructions in which the destination address will reside in any part of this area. 03fffffeh 03ffffffh 00000000h 00000001h program space program space (+) direction ( ? ) direction (2) data space the result of an operand address calculation that exceeds 32 bits is ignored. therefore, the lower-limit address of the data space, address 00000000h, and the upper-limit address, ffffffffh, are contiguous addresses, and the data space is wrapped around at the boundary of these addresses. fffffffeh ffffffffh 00000000h 00000001h data space data space (+) direction ( ? ) direction chapter 3 cpu functions user ? s manual u15862ej3v0ud 111 3.4.4 memory map the v850es/kf1, v850es/kg1, and v850es/kj1 have reserved areas as shown below. figure 3-3. data memory map (physical addresses) 3ffffffh 3fec000h 3febfffh 1000000h 0ffffffh 0800000h 07fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h 01fffffh 0100000h 00fffffh 3fff000h 3ffefffh 3fff000h 3ffefffh 3ffffffh 0000000h 3fec000h (80 kb) access-prohibited area external memory area note 1 (8 mb) internal rom area note 3 (1 mb) external memory area (1 mb) note 2 internal ram area (60 kb) on-chip peripheral i/o area (4 kb) access-prohibited area external memory area note 1 (4 mb) external memory area (2 mb) note 2 (2 mb) cs0 cs1 cs2 cs3 notes 1. only for the v850es/kj1. access-prohibited area for the v850es/kf1 and v850es/kg1. 2. 64 kb for the v850es/kf1 3. fetch access and read access to addresses 0000000h to 00fffffh is performed for the internal rom area, but in the case of data write access, it is performed for an external memory area. chapter 3 cpu functions user ? s manual u15862ej3v0ud 112 figure 3-4. program memory map 3ff0000h 3feffffh 03fff000h 03ffefffh 03ffffffh 01000000h 00ffffffh 00800000h 007fffffh 00400000h 003fffffh 00100000h 000fffffh 00200000h 001fffffh 00000000h internal ram area (60 kb) access-prohibited area (program fetch disabled area) access-prohibited area (program fetch disabled area) external memory area note 1 (8 mb) external memory area note 1 (4 mb) external memory area (1 mb) note 2 external memory area (2 mb) note 2 internal rom area (1 mb) cs0 cs1 cs2 cs3 notes 1. only for the v850es/kj1. access-prohibited area for the v850es/kf1 and v850es/kg1. 2. 64 kb for the v850es/kf1 remark instruction execution for external memory areas without branching from the internal rom area to an external memory area can be performed. chapter 3 cpu functions user ? s manual u15862ej3v0ud 113 3.4.5 areas (1) internal rom area an area of 1 mb from 0000000h to 00fffffh is reserved for the internal rom area. (a) internal rom/internal flash memory (128 kb) a 128 kb area from 0000000h to 001ffffh is provided in the following products. addresses 0020000h to 00fffffh are an access-prohibited area. ? v850es/kf1 ( pd703210, 703210y, 70f3210, 70f3210y) ? v850es/kg1 ( pd703214, 703214y, 70f3214, 70f3214y) ? v850es/kj1 ( pd703217, 703217y, 70f3217, 70f3217y) figure 3-5. internal rom/internal flash memory area (128 kb) 00fffffh 0020000h 001ffffh 0000000h access-prohibited area internal rom area chapter 3 cpu functions user ? s manual u15862ej3v0ud 114 (b) internal rom/internal flash memory area (96 kb) a 96 kb area from 0000000h to 0017fffh is provided in the following products. addresses 0018000h to 00fffffh are an access-prohibited area. ? v850es/kf1 ( pd703209, 703209y) ? v850es/kg1 ( pd703213, 703213y) ? v850es/kj1 ( pd703216, 703216y) figure 3-6. internal rom area (96 kb) 00fffffh 0018000h 0017fffh 0000000h access-prohibited area internal rom area (c) internal rom/internal flash memory area (64 kb) a 64 kb area from 000000h to 000ffffh is provided in the following products. addresses 0010000 to 00fffffh are an access-prohibited area. ? v850es/kf1 ( pd703208, 703208y) ? v850es/kg1 ( pd703212, 703212y) figure 3-7. internal rom area (64 kb) 00fffffh 0010000h 000ffffh 0000000h access-prohibited area internal rom area chapter 3 cpu functions user ? s manual u15862ej3v0ud 115 ? interrupt/exception table the v850es/kf1, v850es/kg1, and v850es/kj1 increase the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. this group of handler addresses is called an interrupt/exception table. this table is located in the internal rom area. when an interrupt/exception request is acknowledged, execution jumps to the handler address and the program written in that memory is executed. table 3-3 lists the interrupt/exception sources and the corresponding addresses. table 3-3. interrupt/exception table start address of interrupt/ exception table interrupt/ exception source start address of interrupt/ exception table interrupt/ exception source 00000000h reset 000001b0h intsre1 00000010h nmi 000001c0h intsr1 00000020h intwdt1 000001d0h intst1 00000030h intwdt2 000001e0h inttmh0 00000040h trap0n (n = 0 to f) 000001f0h inttmh1 00000050h trap1n (n = 0 to f) 00000200h intcsia0 00000060h ilgop/dbg0 00000210h intiic0 note 1 00000080h intwdtm1 00000220h intad 00000090h intp0 00000230h intkr 000000a0h intp1 00000240h intwti 000000b0h intp2 00000250h intwt 000000c0h intp3 00000260h intbrg 000000d0h intp4 00000270h inttm020 note 2 000000e0h intp5 00000280h inttm021 note 2 000000f0h intp6 00000290h inttm030 note 2 00000100h inttm000 000002a0h inttm031 note 2 00000110h inttm001 000002b0h intcsia1 note 2 00000120h inttm010 000002c0h inttm040 note 3 00000130h inttm011 000002d0h inttm041 note 3 00000140h inttm50 000002e0h inttm050 note 3 00000150h inttm51 000002f0h inttm051 note 3 00000160h intcsi00 00000300h intcsi02 note 3 00000170h intcsi01 00000310h intsre2 note 3 00000180h intsre0 00000320h intsr2 note 3 00000190h intsr0 00000330h intst2 note 3 000001a0h intst0 00000340h intiic1 note 4 notes 1. only for products with an i 2 c bus 2. only for the v850es/kg1 and v850es/kj1 3. only for the v850es/kj1 4. only for the pd703216y, 703217y, and 70f3217y chapter 3 cpu functions user ? s manual u15862ej3v0ud 116 (2) internal ram area an area of 60 kb maximum from 3ff0000h to 3ffefffh is reserved for the internal ram area. (a) internal ram (6 kb) a 6 kb area from 3ffd800h to 3ffefffh is provided as physical internal ram. addresses 3ff0000h to 3ffd7ffh are an access-prohibited area. ? v850es/kf1 ( pd703210, 703210y, 70f3210, 70f3210y) ? v850es/kg1 ( pd703214, 703214y, 70f3214, 70f3214y) ? v850es/kj1 ( pd703216, 703216y, 703217, 703217y, 70f3217, 70f3217y) figure 3-8. internal ram area (6 kb) internal ram (6 kb) access-prohibited area 3ffefffh 3ffd800h 3ffd7ffh 3ff0000h chapter 3 cpu functions user ? s manual u15862ej3v0ud 117 (b) internal ram area (4 kb) a 4 kb area from 3ffe000h to 3ffefffh is provided as physical internal ram in the following products. addresses 3ff0000h to 3ffdfffh are an access-prohibited area. ? v850es/kf1 ( pd703218, 703218y, 703219, 703219y) ? v850es/kg1 ( pd703212, 703212y, 703213, 70f3213y) figure 3-9. internal ram area (4 kb) internal ram area (4 kb) access-prohibited area 3ffefffh 3ffe000h 3ffdfffh 3ff0000h chapter 3 cpu functions user ? s manual u15862ej3v0ud 118 (3) on-chip peripheral i/o area a 4 kb area from 3fff000h to 3ffffffh is reserved as the on-chip peripheral i/o area. figure 3-10. on-chip peripheral i/o area 3ffffffh 3fff000h on-chip peripheral i/o area (4 kb) peripheral i/o registers assigned with functions such as on-chip peripheral i/o operation mode specification and state monitoring are mapped to the on-chip peripheral i/o area. program fetches are not allowed in this area. cautions 1. if word access of a register is attempted, halfword access to the word area is performed twice, first for the lower bits, then for the higher bits, ignoring the lower 2 address bits. 2. if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits become undefined if the access is a read operation. if a write access is performed, only the data in the lower 8 bits is written to the register. 3. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. (4) external memory area 15 mb (0100000h to 0ffffffh) are provided as the external memory area. for details, refer to chapter 5 bus control function . chapter 3 cpu functions user ? s manual u15862ej3v0ud 119 3.4.6 peripheral i/o registers (1/12) operable bit address function register name symbol r/w 1816 after reset fffff004h port dl register pdl r/w undefined fffff004h port dl register l pdll r/w ? undefined fffff005h port dl register h pdlh r/w ? undefined fffff006h port dh register pdh note 1 r/w ? undefined fffff008h port cs register pcs r/w ? undefined fffff00ah port ct register pct r/w ? undefined fffff00ch port cm register pcm r/w ? undefined fffff00eh port cd register pcd note 2 r/w ? undefined fffff024h port dl mode register pmdl r/w ffffh fffff024h port dl mode register l pmdll r/w ? ffh fffff025h port dl mode register h pmdlh r/w ? ffh fffff026h port dh mode register pmdh note 1 r/w ? ffh fffff028h port cs mode register pmcs r/w ? ffh fffff02ah port ct mode register pmct r/w ? ffh fffff02ch port cm mode register pmcm r/w ? ffh fffff02eh port cd mode register pmcd note 2 r/w ? ffh fffff044h port dl mode control register pmcdl r/w 0000h fffff044h port dl mode control register l pmcdll r/w ? 00h fffff045h p ort dl mode control register h pmcdlh r/w ? 00h fffff046h port dh mode control register pmcdh note 1 r/w ? 00h fffff048h port cs mode control register pmccs r/w ? 00h fffff04ah port ct mode control register pmcct r/w ? 00h fffff04ch port cm mode control register pmccm r/w ? 00h fffff066h bus size configuration register bsc r/w 5555h fffff06eh system wait control register vswc r/w ? 77h fffff100h interrupt mask register 0 imr0 r/w ffffh fffff100h interrupt mask register 0l imr0l r/w ? ffh fffff101h interrupt mask register 0h imr0h r/w ? ffh fffff102h interrupt mask register 1 imr1 r/w ffffh fffff102h interrupt mask register 1l imr1l r/w ? ffh fffff103h interrupt mask register 1h imr1h r/w ? ffh fffff104h interrupt mask register 2 imr2 note 1 r/w ffffh fffff104h interrupt mask register 2l imr2l note 1 r/w ? ffh fffff105h interrupt mask register 2h imr2h note 1 r/w ? ffh fffff110h interrupt control register wdt1ic r/w ? 47h fffff112h interrupt control register pic0 r/w ? 47h fffff114h interrupt control register pic1 r/w ? 47h fffff116h interrupt control register pic2 r/w ? 47h notes 1. only for the v850es/kg1 and v850es/kj1 2. only for the v850es/kj1 chapter 3 cpu functions user ? s manual u15862ej3v0ud 120 (2/12) operable bit address function register name symbol r/w 1816 after reset fffff118h interrupt control register pic3 r/w ? 47h fffff11ah interrupt control register pic4 r/w ? 47h fffff11ch interrupt control register pic5 r/w ? 47h fffff11eh interrupt control register pic6 r/w ? 47h fffff120h interrupt control register tm0ic00 r/w ? 47h fffff122h interrupt control register tm0ic01 r/w ? 47h fffff124h interrupt control register tm0ic10 r/w ? 47h fffff126h interrupt control register tm0ic11 r/w ? 47h fffff128h interrupt control register tm5ic0 r/w ? 47h fffff12ah interrupt control register tm5ic1 r/w ? 47h fffff12ch interrupt control register csi0ic0 r/w ? 47h fffff12eh interrupt control register csi0ic1 r/w ? 47h fffff130h interrupt control register sreic0 r/w ? 47h fffff132h interrupt control register sric0 r/w ? 47h fffff134h interrupt control register stic0 r/w ? 47h fffff136h interrupt control register sreic1 r/w ? 47h fffff138h interrupt control register sric1 r/w ? 47h fffff13ah interrupt control register stic1 r/w ? 47h fffff13ch interrupt control register tmhic0 r/w ? 47h fffff13eh interrupt control register tmhic1 r/w ? 47h fffff140h interrupt control register csiaic0 r/w ? 47h fffff142h interrupt control register iicic0 note 1 r/w ? 47h fffff144h interrupt control register adic r/w ? 47h fffff146h interrupt control register kric r/w ? 47h fffff148h interrupt control register wtiic r/w ? 47h fffff14ah interrupt control register wtic r/w ? 47h fffff14ch interrupt control register brgic r/w ? 47h fffff14eh interrupt control register tm0ic20 note 2 r/w ? 47h fffff150h interrupt control register tm0ic21 note 2 r/w ? 47h fffff152h interrupt control register tm0ic30 note 2 r/w ? 47h fffff154h interrupt control register tm0ic31 note 2 r/w ? 47h fffff156h interrupt control register csiaic1 note 2 r/w ? 47h fffff158h interrupt control register tm0ic40 note 3 r/w ? 47h fffff15ah interrupt control register tm0ic41 note 3 r/w ? 47h fffff15ch interrupt control register tm0ic50 note 3 r/w ? 47h fffff15eh interrupt control register tm0ic51 note 3 r/w ? 47h fffff160h interrupt control register csi0ic2 note 3 r/w ? 47h fffff162h interrupt control register sreic2 note 3 r/w ? 47h fffff164h interrupt control register sric2 note 3 r/w ? 47h notes 1. only for products with an i 2 c bus 2. only for the v850es/kg1 and v850es/kj1 3. only for the v850es/kj1 chapter 3 cpu functions user ? s manual u15862ej3v0ud 121 (3/12) operable bit address function register name symbol r/w 1816 after reset fffff166h interrupt control register stic2 note 1 r/w ? 47h fffff168h interrupt control register iicic1 note 2 r/w ? 47h fffff1fah in-service priority register ispr r ? 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc r/w ? 00h fffff200h a/d converter mode register adm r/w ? 00h fffff201h analog input channel specification register ads r/w 00h fffff202h power fail comparison mode register pfm r/w ? 00h fffff203h power fail comparison threshold register pft r/w 00h fffff204h a/d conversion result register adcr r undefined fffff205h a/d conversion result register h adcrh r undefined fffff280h d/a conversion value setting register 0 dacs0 note 3 r/w 00h fffff282h d/a conversion value setting register 1 dacs1 note 3 r/w 00h fffff284h d/a converter mode register dam note 3 r/w ? 00h fffff300h key return mode register krm r/w ? 00h fffff400h port 0 register p0 r/w ? undefined fffff402h port 1 register p1 note 3 r/w ? undefined fffff406h port 3 register p3 r/w undefined fffff406h port 3 register l p3l r/w ? undefined fffff407h port 3 register h p3h r/w ? undefined fffff408h port 4 register p4 r/w ? undefined fffff40ah port 5 register p5 r/w ? undefined fffff40ch port 6 register p6 note 1 r/w undefined fffff40ch port 6 register l p6l note 1 r/w ? undefined fffff40dh port 6 register h p6h note 1 r/w ? undefined fffff40eh port 7 register p7 note 4 r undefined fffff40eh port 7 register p7 note 1 r undefined fffff40eh port 7 register l p7l note 1 r undefined fffff40fh port 7 register h p7h note 1 r undefined fffff410h port 8 register p8 note 1 r/w ? undefined fffff412h port 9 register p9 r/w undefined fffff412h port 9 register l p9l r/w ? undefined fffff413h port 9 register h p9h r/w ? undefined fffff420h port 0 mode register pm0 r/w ? ffh fffff422h port 1 mode register pm1 note 3 r/w ? ffh fffff426h port 3 mode register pm3 r/w ffffh fffff426h port 3 mode register l pm3l r/w ? ffh fffff427h port 3 mode register h pm3h r/w ? ffh notes 1. only for the v850es/kj1 2. only for the pd703216y, 703217y, and 70f3217y 3. only for the v850es/kg1 and v850es/kj1 4. only for the v850es/kf1 and v850es/kg1 chapter 3 cpu functions user ? s manual u15862ej3v0ud 122 (4/12) operable bit address function register name symbol r/w 1816 after reset fffff428h port 4 mode register pm4 r/w ? ffh fffff42ah port 5 mode register pm5 r/w ? ffh ffff42ch port 6 mode register pm6 note r/w ffffh fffff42ch port 6 mode register l pm6l note r/w ? ffh fffff42dh port 6 mode register h pm6h note r/w ? ffh fffff430h port 8 mode register pm8 note r/w ? ffh fffff432h port 9 mode register pm9 r/w ffffh fffff432h port 9 mode register l pm9l r/w ? ffh fffff433h port 9 mode register h pm9h r/w ? ffh fffff440h port 0 mode control register pmc0 r/w ? 00h fffff446h port 3 mode control register pmc3 r/w 0000h fffff446h port 3 mode control register l pmc3l r/w ? 00h fffff447h port 3 mode control register h pmc3h r/w ? 00h fffff448h port 4 mode control register pmc4 r/w ? 00h fffff44ah port 5 mode control register pmc5 r/w ? 00h fffff44ch port 6 mode control register pmc6 note r/w 0000h fffff44ch port 6 mode control register l pmc6l note r/w ? 00h fffff44dh port 6 mode control register h pmc6h note r/w ? 00h fffff450h port 8 mode control register pmc8 note r/w ? 00h fffff452h port 9 mode control register pmc9 r/w 0000h fffff452h port 9 mode control register l pmc9l r/w ? 00h fffff453h port 9 mode control register h pmc9h r/w ? 00h fffff466h port 3 function control register pfc3 r/w ? 00h fffff46ah port 5 function control register pfc5 r/w ? 00h fffff46dh port 6 function control register pfc6h note r/w ? 00h fffff470h port 8 function control register pfc8 note r/w ? 00h fffff472h port 9 function control register pfc9 r/w 0000h fffff472h port 9 function control register l pfc9l r/w ? 00h fffff473h port 9 function control register h pfc9h r/w ? 00h fffff484h data wait control register 0 dwc0 r/w 7777h fffff488h address wait control register awc r/w ffffh fffff48ah bus cycle control register bcc r/w aaaah fffff580h 8-bit timer h mode register 0 tmhmd0 r/w ? 00h fffff581h 8-bit timer h carrier control register 0 tmcyc0 r/w ? 00h fffff582h 8-bit timer h compare register 00 cmp00 r/w 00h fffff583h 8-bit timer h compare register 01 cmp01 r/w 00h fffff590h 8-bit timer h mode register 1 tmhmd1 r/w ? 00h fffff591h 8-bit timer h carrier control register 1 tmcyc1 r/w ? 00h fffff592h 8-bit timer h compare register 10 cmp10 r/w 00h fffff593h 8-bit timer h compare register 11 cmp11 r/w 00h note only for the v850es/kj1 chapter 3 cpu functions user ? s manual u15862ej3v0ud 123 (5/12) operable bit address function register name symbol r/w 1816 after reset fffff5c0h 16-bit timer counter 5 tm5 r 0000h fffff5c0h 8-bit timer counter 50 tm50 r 00h fffff5c1h 8-bit timer counter 51 tm51 r 00h fffff5c2h 16-bit timer compare register 5 cr5 r/w 0000h fffff5c2h 8-bit timer compare register 50 cr50 r/w 00h fffff5c3h 8-bit timer compare register 51 cr51 r/w 00h fffff5c4h timer clock selection register 5 tcl5 r/w 0000h fffff5c4h timer clock selection register 50 tcl50 r/w ? 00h fffff5c5h timer clock selection register 51 tcl51 r/w ? 00h fffff5c6h 16-bit timer mode control register 5 tmc5 r/w 0000h fffff5c6h 8-bit timer mode control register 50 tmc50 r/w ? 00h fffff5c7h 8-bit timer mode control register 51 tmc51 r/w ? 00h fffff600h 16-bit timer counter 00 tm00 r 0000h fffff602h 16-bit timer capture/compare register 000 cr000 r/w 0000h fffff604h 16-bit timer capture/compare register 001 cr001 r/w 0000h fffff606h 16-bit timer mode control register 00 tmc00 r/w ? 00h fffff607h prescaler mode register 00 prm00 r/w ? 00h fffff608h capture/compare control register 00 crc00 r/w ? 00h fffff609h 16-bit timer output control register 00 toc00 r/w 00h fffff610h 16-bit timer counter 01 tm01 r 0000h fffff612h 16-bit timer capture/compare register 010 cr010 r/w 0000h fffff614h 16-bit timer capture/compare register 011 cr011 r/w 0000h fffff616h 16-bit timer mode control register 01 tmc01 r/w ? 00h fffff617h prescaler mode register 01 prm01 r/w ? 00h fffff618h capture/compare control register 01 crc01 r/w ? 00h fffff619h 16-bit timer output control register 01 toc01 r/w 00h fffff620h 16-bit timer counter 02 tm02 note r 0000h fffff622h 16-bit timer capture/compare register 020 cr020 note r/w 0000h fffff624h 16-bit timer capture/compare register 021 cr021 note r/w 0000h fffff626h 16-bit timer mode control register 02 tmc02 note r/w ? 00h fffff627h prescaler mode register 02 prm02 note r/w ? 00h fffff628h capture/compare control register 02 crc02 note r/w ? 00h fffff629h 16-bit timer output control register 02 toc02 note r/w 00h fffff630h 16-bit timer counter 03 tm03 note r 0000h fffff632h 16-bit timer capture/compare register 030 cr030 note r/w 0000h fffff634h 16-bit timer capture/compare register 031 cr031 note r/w 0000h fffff636h 16-bit timer mode control register 03 tmc03 note r/w ? 00h fffff637h prescaler mode register 03 prm03 note r/w ? 00h fffff638h capture/compare control register 03 crc03 note r/w ? 00h fffff639h 16-bit timer output control register 03 toc03 note r/w 00h note only for the v850es/kg1 and v850es/kj1 chapter 3 cpu functions user ? s manual u15862ej3v0ud 124 (6/12) operable bit address function register name symbol r/w 1 8 16 43 after reset fffff640h 16-bit timer counter 04 tm04 note r 0000h fffff642h 16-bit timer capture/compare register 040 cr040 note r/w 0000h fffff644h 16-bit timer capture/compare register 041 cr041 note r/w 0000h fffff646h 16-bit timer mode control register 04 tmc04 note r/w ? 00h fffff647h prescaler mode register 04 prm04 note r/w ? 00h fffff648h capture/compare control register 04 crc04 note r/w ? 00h fffff649h 16-bit timer output control register 04 toc04 note r/w 00h fffff650h 16-bit timer counter 05 tm05 note r 0000h fffff652h 16-bit timer capture/compare register 050 cr050 note r/w 0000h fffff654h 16-bit timer capture/compare register 051 cr051 note r/w 0000h fffff656h 16-bit timer mode control register 05 tmc05 note r/w ? 00h fffff657h prescaler mode register 05 prm05 note r/w ? 00h fffff658h capture/compare control register 05 crc05 note r/w ? 00h fffff659h 16-bit timer output control register 05 toc05 note r/w 00h fffff680h watch timer operation mode register wtm r/w ? 00h fffff6c0h oscillation stabilization time select register osts r/w 01h fffff6c1h watchdog timer clock selection register wdcs r/w 00h fffff6c2h watchdog timer mode register 1 wdtm1 r/w ? 00h fffff6d0h watchdog timer mode register 2 wdtm2 r/w 67h fffff6d1h watchdog timer enable register wdte r/w 9ah fffff6e0h real-time output buffer register l0 rtbl0 r/w ? 00h fffff6e2h real-time output buffer register h0 rtbh0 r/w ? 00h fffff6e4h real-time output port mode register 0 rtpm0 r/w ? 00h fffff6e5h real-time output port control register 0 rtpc0 r/w ? 00h fffff6f0h real-time output buffer register l1 rtbl1 note r/w ? 00h fffff6f2h real-time output buffer register h1 rtbh1 note r/w ? 00h fffff6f4h real-time output port mode register 1 rtpm1 note r/w ? 00h fffff6f5h real-time output port control register 1 rtpc1 note r/w ? 00h fffff802h system status register sys r/w ? 00h fffff806h pll control register pllctl r/w ? 01h fffff820h power save mode register psmr r/w ? 00h fffff828h processor clock control register pcc r/w ? 03h fffff840h correction address register 0 corad0 r/w 00000000h fffff840h correction address register 0l corad0l r/w 0000h fffff842h correction address register 0h corad0h r/w 0000h fffff844h correction address register 1 corad1 r/w 00000000h fffff844h correction address register 1l corad1l r/w 0000h fffff846h correction address register 1h corad1h r/w 0000h fffff848h correction address register 2 corad2 r/w 00000000h fffff848h correction address register 2l corad2l r/w 0000h fffff84ah correction address register 2h corad2h r/w 0000h note only for the v850es/kj1 chapter 3 cpu functions user ? s manual u15862ej3v0ud 125 (7/12) operable bit address function register name symbol r/w 1 8 16 43 after reset fffff84ch correction address register 3 corad3 r/w 00000000h fffff84ch correction address register 3l corad3l r/w 0000h fffff84eh correction address register 3h corad3h r/w 0000h fffff880h correction control register corcn r/w ? 00h fffff8b0h prescaler mode register prsm r/w 00h fffff8b1h prescaler compare register prscm r/w 00h fffffa00h asynchronous serial interface mode register 0 asim0 r/w ? 01h fffffa02h receive buffer register 0 rxb0 r ffh fffffa03h asynchronous serial interface status register 0 asis0 r 00h fffffa04h transmit buffer register 9 txb0 r/w ffh fffffa05h asynchronous serial interface transmission status register 0 asif0 r 00h fffffa06h clock selection register 0 cksr0 r/w ? 00h fffffa07h baud rate generator control register 0 brgc0 r/w ? ffh fffffa10h asynchronous serial interface mode register 1 asim1 r/w ? 01h fffffa12h receive buffer register 1 rxb1 r ffh fffffa13h asynchronous serial interface status register 1 asis1 r 00h fffffa14h transmit buffer register 1 txb1 r/w ffh fffffa15h asynchronous serial interface transmission status register 1 asif1 r 00h fffffa16h clock selection register 1 cksr1 r/w ? 00h fffffa17h baud rate generator control register 1 brgc1 r/w ? ffh fffffa20h asynchronous serial interface mode register 2 asim2 note 1 r/w ? 01h fffffa22h receive buffer register 2 rxb2 note 1 r ffh fffffa23h asynchronous serial interface status register 2 asis2 note 1 r 00h fffffa24h transmit buffer register 2 txb2 note 1 r/w ffh fffffa25h asynchronous serial interface transmission status register 2 asif2 note 1 r 00h fffffa26h clock selection register 2 cksr2 note 1 r/w ? 00h fffffa27h baud rate generator control register 2 brgc2 note 1 r/w ? ffh fffffc00h external interrupt falling edge specification register 0 intf0 r/w ? 00h fffffc13h external interrupt falling edge specification register 9h intf9h r/w ? 00h fffffc20h external interrupt rising edge specification register 0 intr0 r/w ? 00h fffffc33h external interrupt rising edge specification register 9h intr9h r/w ? 00h fffffc40h pull-up resistor option register 0 pu0 r/w ? 00h fffffc42h pull-up resistor option register 1 pu1 note 2 r/w ? 00h fffffc46h pull-up resistor option register 3 pu3 r/w ? 00h fffffc48h pull-up resistor option register 4 pu4 r/w ? 00h fffffc4ah pull-up resistor option register 5 pu5 r/w ? 00h notes 1. only for the v850es/kj1 2. only for the v850es/kg1 and v850es/kj1 chapter 3 cpu functions user ? s manual u15862ej3v0ud 126 (8/12) operable bit address function register name symbol r/w 1816 after reset fffffc4ch pull-up resistor option register 6 pu6 note r/w 0000h fffffc4ch pull-up resistor option register 6l pu6l note r/w ? 00h fffffc4dh pull-up resistor option register 6h pu6h note r/w ? 00h fffffc50h pull-up resistor option register 8 pu8 note r/w ? 00h fffffc52h pull-up resistor option register 9 pu9 r/w 0000h fffffc52h pull-up resistor option register 9l pu9l r/w ? 00h fffffc53h pull-up resistor option register 9h pu9h r/w ? 00h fffffc67h port 3 function register h pf3h r/w ? 00h fffffc68h port 4 function register pf4 r/w ? 00h fffffc6ah port 5 function register pf5 r/w ? 00h fffffc6ch port 6 function register pf6 note r/w 0000h fffffc6ch port 6 function register l pf6l note r/w ? 00h fffffc6dh port 6 function register h pf6h note r/w ? 00h fffffc70h port 8 function register pf8 note r/w ? 00h fffffc73h port 9 function register h pf9h r/w ? 00h fffffd00h clocked serial interface mode register 00 csim00 r/w ? 00h fffffd01h clocked serial interface clock selection register 0 csic0 r/w ? 00h fffffd02h clocked serial interface receive buffer register 0 sirb0 r 0000h fffffd02h clocked serial interface receive buffer register 0l sirb0l r 00h fffffd04h clocked serial interface transmit buffer register 0 sotb0 r/w 0000h fffffd04h clocked serial interface transmit buffer register 0l sotb0l r/w 00h fffffd06h clocked serial interface read-only receive buffer register 0 sirbe0 r 0000h fffffd06h clocked serial interface read-only receive buffer register 0l sirbe0l r 00h fffffd08h clocked serial interface first-stage transmit buffer register 0 sotbf0 r/w 0000h fffffd08h clocked serial interface first-stage transmit buffer register 0l sotbf0l r/w 00h fffffd0ah serial i/o shift register 0 sio00 r/w 00h fffffd0ah serial i/o shift register 0l sio00l r/w 0000h fffffd10h clocked serial interface mode register 01 csim01 r/w ? 00h fffffd11h clocked serial interface clock selection register 1 csic1 r/w ? 00h fffffd12h clocked serial interface receive buffer register 1 sirb1 r 0000h fffffd12h clocked serial interface receive buffer register 1l sirb1l r 00h fffffd14h clocked serial interface transmit buffer register 1 sotb1 r/w 0000h fffffd14h clocked serial interface transmit buffer register 1l sotb1l r/w 00h fffffd16h clocked serial interface read-only receive buffer register 1 sirbe1 r 0000h fffffd16h clocked serial interface read-only receive buffer register 1l sirbe1l r 00h fffffd18h clocked serial interface first-stage transmit buffer register 1 sotbf1 r/w 0000h fffffd18h clocked serial interface first-stage transmit buffer register 1l sotbf1l r/w 00h fffffd1ah serial i/o shift register 1 sio01 r/w 00h fffffd1ah serial i/o shift register 1l sio1l r/w 0000h fffffd20h clocked serial interface mode register 02 csim02 note r/w ? 00h fffffd21h clocked serial interface clock selection register 2 csic2 note r/w ? 00h note only for the v850es/kj1 chapter 3 cpu functions user ? s manual u15862ej3v0ud 127 (9/12) operable bit address function register name symbol r/w 1816 after reset fffffd22h clocked serial interface receive buffer register 2 sirb2 note 1 r 0000h fffffd22h clocked serial interface receive buffer register 2l sirb2l note 1 r 00h fffffd24h clocked serial interface transmit buffer register 2 sotb2 note 1 r/w 0000h fffffd24h clocked serial interface transmit buffer register 2l sotb2l note 1 r/w 00h fffffd26h clocked serial interface read-only receive buffer register 2 sirbe2 note 1 r 0000h fffffd26h clocked serial interface read-only receive buffer register 2l sirbe2l note 1 r 00h fffffd28h clocked serial interface first-stage transmit buffer register 2 sotbf2 note 1 r/w 0000h fffffd28h clocked serial interface first-stage transmit buffer register 2l sotbf2l note 1 r/w 00h fffffd2ah serial i/o shift register 2 sio02 note 1 r/w 00h fffffd2ah serial i/o shift register 2l sio02l note 1 r/w 0000h fffffd40h serial operation mode specification register 0 csima0 r/w ? 00h fffffd41h serial status register 0 csis0 r/w ? 00h fffffd42h serial trigger register 0 csit0 r/w ? 00h fffffd43h division value selection register 0 brgca0 r/w 03h fffffd44h automatic data transfer address point specification register 0 adtp0 r/w 00h fffffd45h automatic data transfer interval specification register 0 adti0 r/w 00h fffffd46h serial i/o shift register a0 sioa0 r/w ? 00h fffffd47h automatic data transfer address count register 0 adtc0 r ? 00h fffffd50h serial operation mode specification register 1 csima1 note 2 r/w ? 00h fffffd51h serial status register 1 csis1 note 2 r/w ? 00h fffffd52h serial trigger register 1 csit1 note 2 r ? 00h fffffd53h division value selection register 1 brgca1 note 2 r/w 03h fffffd54h automatic data transfer address point specification register 1 adtp1 note 2 r/w 00h fffffd55h automatic data transfer interval specification register 1 adti1 note 2 r/w 00h fffffd56h serial i/o shift register a1 sioa1 note 2 r/w ? 00h fffffd57h automatic data transfer address count register 1 adtc1 note 2 r ? 00h fffffd80h iic shift register 0 iic0 note 3 r/w 00h fffffd82h iic control register 0 iicc0 note 3 r/w ? 00h fffffd83h slave address register 0 sva0 note 3 r/w 00h fffffd84h iic clock selection register 0 iiccl0 note 3 r/w ? 00h fffffd85h iic function expansion register 0 iicx0 note 3 r/w ? 00h fffffd86h iic status register 0 iics0 note 3 r ? 00h fffffd8ah iic flag register 0 iicf0 note 3 r/w ? 00h fffffd90h iic shift register 1 iic1 note 4 r/w 00h fffffd92h iic control register 1 iicc01 note 4 r/w ? 00h fffffd93h slave address register 1 sva01 note 4 r/w 00h fffffd94h iic clock selection register 1 iiccl01 note 4 r/w ? 00h fffffd95h iic function expansion register 1 iicx1 note 4 r/w ? 00h notes 1. only for the v850es/kj1 2. only for the v850es/kg1 and v850es/kj1 3. only for products with an i 2 c bus 4. only for the pd703216y, 703217y, and 70f3217y chapter 3 cpu functions user ? s manual u15862ej3v0ud 128 (10/12) operable bit address function register name symbol r/w 1816 after reset fffffd96h iic status register 1 iics01 note r ? 00h fffffd9ah iic flag register 1 iicf1 note r/w ? 00h fffffe00h csia0 buffer ram 0 csia0b0 r/w undefined fffffe00h csia0 buffer ram 0l csia0b0l r/w undefined fffffe01h csia0 buffer ram 0h csia0b0h r/w undefined fffffe02h csia0 buffer ram 1 csia0b1 r/w undefined fffffe02h csia0 buffer ram 1l csia0b1l r/w undefined fffffe03h csia0 buffer ram 1h csia0b1h r/w undefined fffffe04h csia0 buffer ram 2 csia0b2 r/w undefined fffffe04h csia0 buffer ram 2l csia0b2l r/w undefined fffffe05h csia0 buffer ram2h csia0b2h r/w undefined fffffe06h csia0 buffer ram 3 csia0b3 r/w undefined fffffe06h csia0 buffer ram 3l csia0b3l r/w undefined fffffe07h csia0 buffer ram 3h csia0b3h r/w undefined fffffe08h csia0 buffer ram 4 csia0b4 r/w undefined fffffe08h csia0 buffer ram 4l csia0b4l r/w undefined fffffe09h csia0 buffer ram 4h csia0b4h r/w undefined fffffe0ah csia0 buffer ram 5 csia0b5 r/w undefined fffffe0ah csia0 buffer ram 5l csia0b5l r/w undefined fffffe0bh csia0 buffer ram 5h csia0b5h r/w undefined fffffe0ch csia0 buffer ram 6 csia0b6 r/w undefined fffffe0ch csia0 buffer ram 6l csia0b6l r/w undefined fffffe0dh csia0 buffer ram 6h csia0b6h r/w undefined fffffe0eh csia0 buffer ram 7 csia0b7 r/w undefined fffffe0eh csia0 buffer ram 7l csia0b7l r/w undefined fffffe0fh csia0 buffer ram 7h csia0b7h r/w undefined fffffe10h csia0 buffer ram 8 csia0b8 r/w undefined fffffe10h csia0 buffer ram 8l csia0b8l r/w undefined fffffe11h csia0 buffer ram 8h csia0b8h r/w undefined fffffe12h csia0 buffer ram 9 csia0b9 r/w undefined fffffe12h csia0 buffer ram 9l csia0b9l r/w undefined fffffe13h csia0 buffer ram 9h csia0b9h r/w undefined fffffe14h csia0 buffer ram a csia0ba r/w undefined fffffe14h csia0 buffer ram al csia0bal r/w undefined fffffe15h csia0 buffer ram ah csia0bah r/w undefined fffffe16h csia0 buffer ram b csia0bb r/w undefined fffffe16h csia0 buffer ram bl csia0bbl r/w undefined fffffe17h csia0 buffer ram bh csia0bbh r/w undefined fffffe18h csia0 buffer ram c csia0bc r/w undefined fffffe18h csia0 buffer ram cl csia0bcl r/w undefined fffffe19h csia0 buffer ram ch csia0bch r/w undefined note only for the pd703216y, 703217y, and 70f3217y chapter 3 cpu functions user ? s manual u15862ej3v0ud 129 (11/12) operable bit address function register name symbol r/w 1816 after reset fffffe1ah csia0 buffer ram d csia0bd r/w undefined fffffe1ah csia0 buffer ram dl csia0bdl r/w undefined fffffe1bh csia0 buffer ram dh csia0bdh r/w undefined fffffe1ch csia0 buffer ram e csia0be r/w undefined fffffe1ch csia0 buffer ram el csia0bel r/w undefined fffffe1dh csia0 buffer ram eh csia0beh r/w undefined fffffe1eh csia0 buffer ram f csia0bf r/w undefined fffffe1eh csia0 buffer ram fl csia0bfl r/w undefined fffffe1fh csia0 buffer ram fh csia0bfh r/w undefined fffffe20h csia1 buffer ram 0 csia1b0 note r/w undefined fffffe20h csia1 buffer ram 0l csia1b0l note r/w undefined fffffe21h csia1 buffer ram 0h csia1b0h note r/w undefined fffffe22h csia1 buffer ram 1 csia1b1 note r/w undefined fffffe22h csia1 buffer ram 1l csia1b1l note r/w undefined fffffe23h csia1 buffer ram 1h csia1b1h note r/w undefined fffffe24h csia1 buffer ram 2 csia1b2 note r/w undefined fffffe24h csia1 buffer ram 2l csia1b2l note r/w undefined fffffe25h csia1 buffer ram 2h csia1b2h note r/w undefined fffffe26h csia1 buffer ram 3 csia1b3 note r/w undefined fffffe26h csia1 buffer ram 3l csia1b3l note r/w undefined fffffe27h csia1 buffer ram 3h csia1b3h note r/w undefined fffffe28h csia1 buffer ram 4 csia1b4 note r/w undefined fffffe28h csia1 buffer ram 4l csia1b4l note r/w undefined fffffe29h csia1 buffer ram 4h csia1b4h note r/w undefined fffffe2ah csia1 buffer ram 5 csia1b5 note r/w undefined fffffe2ah csia1 buffer ram 5l csia1b5l note r/w undefined fffffe2bh csia1 buffer ram 5h csia1b5h note r/w undefined fffffe2ch csia1 buffer ram 6 csia1b6 note r/w undefined fffffe2ch csia1 buffer ram 6l csia1b6l note r/w undefined fffffe2dh csia1 buffer ram 6h csia1b6h note r/w undefined fffffe2eh csia1 buffer ram 7 csia1b7 note r/w undefined fffffe2eh csia1 buffer ram 7l csia1b7l note r/w undefined fffffe2fh csia1 buffer ram 7h csia1b7h note r/w undefined fffffe30h csia1 buffer ram 8 csia1b8 note r/w undefined fffffe30h csia1 buffer ram 8l csia1b8l note r/w undefined fffffe31h csia1 buffer ram 8h csia1b8h note r/w undefined fffffe32h csia1 buffer ram 9 csia1b9 note r/w undefined fffffe32h csia1 buffer ram 9l csia1b9l note r/w undefined fffffe33h csia1 buffer ram 9h csia1b9h note r/w undefined fffffe34h csia1 buffer ram a csia1ba note r/w undefined fffffe34h csia1 buffer ram al csia1bal note r/w undefined fffffe35h csia1 buffer ram ah csia1bah note r/w undefined note only for the v850es/kg1 and v850es/kj1 chapter 3 cpu functions user ? s manual u15862ej3v0ud 130 (12/12) operable bit address function register name symbol r/w 1816 after reset fffffe36h csia1 buffer ram b csia1bb note r/w undefined fffffe36h csia1 buffer ram bl csia1bbl note r/w undefined fffffe37h csia1 buffer ram bh csia1bbh note r/w undefined fffffe38h csia1 buffer ram c csia1bc note r/w undefined fffffe38h csia1 buffer ram cl csia1bcl note r/w undefined fffffe39h csia1 buffer ram ch csia1bch note r/w undefined fffffe3ah csia1 buffer ram d csia1bd note r/w undefined fffffe3ah csia1 buffer ram dl csia1bdl note r/w undefined fffffe3bh csia1 buffer ram dh csia1bdh note r/w undefined fffffe3ch csia1 buffer ram e csia1be note r/w undefined fffffe3ch csia1 buffer ram el csia1bel note r/w undefined fffffe3dh csia1 buffer ram eh csia1beh note r/w undefined fffffe3eh csia1 buffer ram f csia1bf note r/w undefined fffffe3eh csia1 buffer ram fl csia1bfl note r/w undefined fffffe3fh csia1 buffer ram fh csia1bfh note r/w undefined ffffffbeh external bus interface mode control register eximc note r/w ? 00h note only for the v850es/kg1 and v850es/kj1 chapter 3 cpu functions user ? s manual u15862ej3v0ud 131 3.4.7 special registers special registers are registers that prevent invalid data from being written when an inadvertent program loop occurs. the v850es/kf1, v850es/kg1, and v850es/kj1 have the following three special registers. ? power save control register (psc) ? processor clock control register (pcc) ? watchdog timer mode register (wdtm1) moreover, there is also a command register (prcmd), which is a protection register for write operations to the special registers that prevents the application system from unexpectedly stopping due to an inadvertent program loop. write access to the special registers is performed with a special sequence and illegal store operations are notified to the system status register (sys). (1) setting data to special registers setting data to a special registers is done in the following sequence. <1> prepare the data to be set to the special register in a general-purpose register. <2> write the data prepared in step <1> to the prcmd register. <3> write the setting data to the special register (using following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <4> to <8> insert nop instructions (5 instructions) note . [description example] when using psc register (standby mode setting) st.b r11,psmr[r0] ; psmr register setting (idle, stop mode setting) <1> mov 0x02,r10 <2> st.b r10,prcmd[r0] ; prcmd register write <3> st.b r10,psc[r0] ; psc register setting <4> nop note ; dummy instruction <5> nop note ; dummy instruction <6> nop note ; dummy instruction <7> nop note ; dummy instruction <8> nop note ; dummy instruction (next instruction) no special sequence is required to read special registers. note when switching to the idle mode or the stop mode (stp bit of psc register = 1), 5 nop instructions must be inserted immediately after switching is performed. chapter 3 cpu functions user ? s manual u15862ej3v0ud 132 cautions 1. interrupts are not acknowledged for the store instruction for the prcmd register. this is because continuous execution of store instructions by the program in steps <3> and <4> above is assumed. if another instruction is placed between step <3> and <4>, the above sequence may not be realized when an interrupt is acknowledged for that instruction, which may cause malfunction. 2. the data written to the prcmd register is dummy data, but use the same register as the general-purpose register used for setting data to the special register (step <4>) when writing to the prcmd register (step <3>). the same applies to when using a general- purpose register for addressing. (2) command register (prcmd) the prcmd register is an 8-bit register used to prevent data from being written to registers that may have a large influence on the system, possibly causing the application system to unexpectedly stop, when an inadvertent program loop occurs. only the first write operation to the special register following the execution of a previously executed write operation to the prcmd register, is valid. as a result, register values can be overwritten only using a preset sequence, preventing invalid write operations. this register can only be written in 8-bit units (if it is read, an undefined value is returned). 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch (3) system status register (sys) this register is allocated with status flags showing the operating state of the entire system. this register can be read or written in 8-bit or 1-bit units. 0 protection error has not occurred protection error has occurred prerr 0 1 detection of protection error sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h < > chapter 3 cpu functions user ? s manual u15862ej3v0ud 133 the operation conditions of the prerr flag are described below. (a) set conditions (prerr = 1) (i) when a write operation to the special register takes place without write operation being performed to the prcmd register (when step <4> is performed without performing step <3> as described in 3.4.7 (1) setting data to special registers ). (ii) when a write operation (including bit manipulation instruction) to an on-chip peripheral i/o register other than a special register is performed following write to the prcmd register (when <4> in 3.4.7 (1) setting data to special registers is not a special register). remark regarding the special registers other than the wdtm register (pcc and psc registers), even if on-chip peripheral i/o register read (except bit manipulation instruction) (internal ram access, etc.) is performed in between write to the prcmd register and write to a special register, the prerr flag is not set and setting data can be written to the special register. (b) clear conditions (prerr = 0) (i) when 0 is written to the prerr flag of the sys register (ii) when system reset is performed cautions 1. if 0 is written to the prerr bit of the sys register that is not a special register immediately following write to the prcmd register, the prerr bit becomes 0 (write priority). 2. if data is written to the prcmd register that is not a special register immediately following write to the prcmd register, the prerr bit becomes 1. chapter 3 cpu functions user ? s manual u15862ej3v0ud 134 3.4.8 cautions be sure to set the following register before using the v850es/kf1, v850es/kg1 and v850es/kj1. ? system wait control register (vswc) after setting the vswc register, set the other registers as required. when using an external bus, set the vswc register and then set the various pins to the control mode by setting the port-related registers. (1) system wait control register (vswc) the system wait control register (vswc) controls the bus access wait time for the on-chip peripheral i/o registers. access to the on-chip peripheral i/o register lasts 3 clocks (during no wait), but in the v850es/kf1, v850es/kg1 and v850es/kj1, waits are required according to the operation frequency. set the values shown below to the vswc register according to the operation frequency that is used. this register can be read or written in 8-bit units (address: fffff06eh, after reset: 77h). operation conditions operation frequency (f clk ) vswc setting 8 mhz f clk < 16.6 mhz 00h regc = v dd = 5 v10%, in pll mode (osc = 2 to 5 mhz) 16.6 mhz f clk 20 mhz 01h 2 mhz f clk < 8.3 mhz 00h regc = capacity, v dd = 4.0 to 5.5 v regc = v dd = 2.7 to 4.0 v 8.3 mhz f clk 16 mhz 01h other than above (regc = v dd = 4.0 to 5.5 v) f clk 16 mhz 00h (2) access to special on-chip peripheral i/o register this product has two types of internal system buses. one type is for the cpu bus and the other is for the peripheral bus to interface with low-speed peripheral hardware. since the cpu bus clock and peripheral bus clock are asynchronous, if a conflict occurs during access between the cpu and peripheral hardware, illegal data may be passed unexpectedly. therefore, when accessing peripheral hardware that may cause a conflict, the number of access cycles is changed so that the data is received/passed correctly in the cpu. as a result, the cpu does not shift to the next instruction processing and enters the wait status. when this wait status occurs, the number of execution clocks of the instruction is increased by the number of wait clocks. note this with caution when performing real-time processing. when accessing a special on-chip peripheral i/o register, additional waits may be required further to the waits set by the vswc register. the access conditions at that time and the method to calculate the number of waits to be inserted (number of cpu clocks) are shown below. chapter 3 cpu functions user ? s manual u15862ej3v0ud 135 peripheral function register name access k wdtm1 write 2 to 4 watchdog timer 1 (wdt1) chapter 3 cpu functions user ? s manual u15862ej3v0ud 136 remark in the calculation for the number of waits: f cpu : cpu clock frequency m: set value of bits 2 to 0 of the vswc register f clk : internal system clock when f clk < 16.6 mhz: 0 when f clk 16.6 mhz: 1 the digits below the decimal point are truncated if less than (1/ f cpu )/(2 + m) or rounded up if larger than (1/ f cpu )/(2 + m) when multiplied by (1/ f cpu ). user?s manual u15862ej3v0ud 137 chapter 4 port functions 4.1 features 4.1.1 v850es/kf1 { input-only ports: 8 pins { i/o ports: 59 pins { shared with i/o pins of other peripheral functions { input/output can be specified in 1-bit units 4.1.2 v850es/kg1 { input-only ports: 8 pins { i/o ports: 76 pins { shared with i/o pins of other peripheral functions { input/output can be specified in 1-bit units 4.1.3 v850es/kj1 { input-only ports: 16 pins { i/o ports: 112 pins { shared with i/o pins of other peripheral functions { input/output can be specified in 1-bit units chapter 4 port functions user?s manual u15862ej3v0ud 138 4.2 basic port configuration 4.2.1 v850es/kf1 the v850es/kf1 incorporates a total of 67 i/o port pins consisting of ports 0, 3 to 5, 7, 9, cm, cs, ct, and dl (including 8 input-only port pins). the port configuration is shown below. p00 p06 port 0 p90 p91 p96 p99 p913 p915 port 9 pct0 pct1 pct4 pct6 port ct pcm0 pcm3 port cm pcs0 pcs1 port cs pdl0 pdl15 port dl p30 p35 p38 p39 port 3 p40 p42 port 4 p50 p55 port 5 p70 p77 port 7 chapter 4 port functions user ? s manual u15862ej3v0ud 139 4.2.2 v850es/kg1 the v850es/kg1 incorporates a total of 84 i/o port pins consisting of ports 0, 1, 3 to 5, 7, 9, cm, cs, ct, dh, and dl (including 8 input-only port pins). the port configuration is shown below. p00 p06 port 0 p90 p915 port 9 pcm0 pcm3 port cm pcs0 pcs1 port cs pct0 pct1 pct4 pct6 port ct pdh0 pdh5 port dh pdl0 pdl15 port dl p10 p11 port 1 p30 p39 port 3 p40 p42 port 4 p50 p55 port 5 p70 p77 port 7 chapter 4 port functions user ? s manual u15862ej3v0ud 140 4.2.3 v850es/kj1 the v850es/kj1 incorporates a total of 128 i/o port pins consisting of ports 0, 1, 3 to 9, cd, cm, cs, ct, dh, and dl (including 16 input-only port pins). the port configuration is shown below. p00 p06 port 0 p90 p915 port 9 pcd0 pcd3 port cd pcm0 pcm5 port cm pcs0 pcs7 port cs pct0 pct7 port ct pdh0 pdh7 port dh pdl0 pdl15 port dl p30 p39 port 3 p40 p42 port 4 p50 p55 port 5 p60 p615 port 6 p70 p715 port 7 p80 p81 port 8 p10 p11 port 1 chapter 4 port functions user ? s manual u15862ej3v0ud 141 4.3 port configuration table 4-1. port configuration (v850es/kf1) item configuration control register port mode registers pmn (n = 0, 3 to 5, 7, 9, cm, cs, ct, dl) pull-up resistor option registers pun (n = 0, 3 to 5, 9) ports i/o: 67 pins pull-up resistors software control: 31 table 4-2. port configuration (v850es/kg1) item configuration control register port mode registers pmn (n = 0, 1, 3 to 5, 7, 9, cm, cs, ct, dh, dl) pull-up resistor option registers pun (n = 0, 1, 3 to 5, 9) ports i/o: 84 pins pull-up resistors software control: 40 table 4-3. port configuration (v850es/kj1) item configuration control register port mode registers pmn (n = 0, 1, 3 to 9, cd, cm, cs, ct, dh, dl) pull-up resistor option registers pun (n = 0, 1, 3 to 6, 8, 9) ports i/o: 128 pins pull-up resistors software control: 56 chapter 4 port functions user ? s manual u15862ej3v0ud 142 4.3.1 port 0 input/output for port 0 can be controlled in 1-bit units. the v850es/kf1, v850es/kg1, and v850es/kj1 have the same number of i/o port pins for port 0. product i/o port pin count v850es/kf1 7-bit i/o port v850es/kg1 7-bit i/o port v850es/kj1 7-bit i/o port (1) port 0 functions { port input/output data can be specified in 1-bit units. specification is made by the port 0 register (p0). { port input/output can be specified in 1-bit units. specification is made by the port 0 mode register (pm0). { port mode/control mode (alternate function) can be specified in 1-bit units. specification is made by the port 0 mode control register (pmc0). { on-chip pull-up resistor connection can be specified in 1-bit units. specification is made by pull-up resistor option register 0 (pu0). { the valid edge of external interrupts (alternate function) can be specified in 1-bit units. the falling edge and the rising edge of the external interrupt are specified by falling edge specification register 0 (intf0) and rising edge specification register 0 (intr0), respectively. port 0 includes the following alternate functions. table 4-4. alternate-function pins of port 0 pin name alternate function i/o pull note remark p00 toh0 p01 toh1 ? p02 nmi p03 intp0 p04 intp1 p05 intp2 port 0 p06 intp3 i/o yes analog noise elimination note software pull-up function chapter 4 port functions user ? s manual u15862ej3v0ud 143 (2) registers (a) port 0 register (p0) the port 0 register (p0) is an 8-bit register that controls pin level read and output level write. this register can be read/written in 8-bit or 1-bit units. 0 output 0 output 1 p0n 0 1 control of output data (in output mode) (n = 0 to 6) p0 p06 p05 p04 p03 p02 p01 p00 after reset: undefined r/w address: fffff400h remark in input mode: when read, port 0 (p0) returns the current pin level. when written to, the data written to p0 is written. this has no influence on the input pins. in output mode: when read, port 0 (p0) returns the p0 value. when written to, the value is written to p0 and the written value is immediately output. (b) port 0 mode register (pm0) this is an 8-bit register that specifies the input mode/output mode. this register can be read/written in 8-bit or 1-bit units. 1 output mode input mode pm0n 0 1 control of i/o mode pm0 pm06 pm05 pm04 pm03 pm02 pm01 pm00 after reset: ffh r/w address: fffff420h chapter 4 port functions user ? s manual u15862ej3v0ud 144 (c) port 0 mode control register (pmc0) this is an 8-bit register that specifies the port mode or control mode. this register can be read/written in 8-bit or 1-bit units. 0 pmc0 pmc06 pmc05 pmc04 pmc03 pmc02 pmc01 pmc00 i/o port intp3 input pmc06 0 1 specification of p06 pin operation mode i/o port intp2 input pmc05 0 1 specification of p05 pin operation mode i/o port intp1 input pmc04 0 1 specification of p04 pin operation mode i/o port intp0 input pmc03 0 1 specification of p03 pin operation mode i/o port nmi input pmc02 0 1 specification of p02 pin operation mode i/o port toh1 output pmc01 0 1 specification of p01 pin operation mode i/o port toh0 output pmc00 0 1 specification of p00 pin operation mode after reset: 00h r/w address: fffff440h chapter 4 port functions user ? s manual u15862ej3v0ud 145 (d) pull-up resistor option register 0 (pu0) this is an 8-bit register that specifies the connection of an on-chip pull-up resistor. this register can be read/written in 8-bit or 1-bit units. 0 not connected connected pu0n 0 1 control of on-chip pull-up resistor connection (n = 0 to 6) pu0 pu06 pu05 pu04 pu03 pu02 pu01 pu00 after reset: 00h r/w address: fffffc40h (e) external interrupt falling edge specification register 0 (intf0) this is an 8-bit register that specifies the falling edge as the detection edge for the external interrupt pin. this register can be read/written in 8-bit or 1-bit units. caution when switching from the external interrupt function (alternate function) to the port function, edge detection may be performed. therefore, set the port mode after setting intf0n bit = intr0n bit = 0. 0 intf0 intf06 intf05 intf04 intf03 intf02 0 0 after reset: 00h r/w address: fffffc00h remark for specification of the valid edge, refer to table 4-5 . chapter 4 port functions user ? s manual u15862ej3v0ud 146 (f) external interrupt rising edge specification register 0 (intr0) this is an 8-bit register that specifies the rising edge as the detection edge for the external interrupt pin. this register can be read/written in 8-bit or 1-bit units. caution when switching from the external interrupt function (alternate function) to the port function, edge detection may be performed. therefore, set the port mode after setting intf0n bit = intr0n bit = 0. 0 intr0 intr06 intr05 intr04 intr03 intr02 0 0 after reset: 00h r/w address: fffffc20h remark for specification of the valid edge, refer to table 4-5 . table 4-5. valid edge specification intf0n intr0n valid edge specification (n = 2 to 6) 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 2: control of nmi pin n = 3 to 6: control of intp0 to intp3 pins chapter 4 port functions user ? s manual u15862ej3v0ud 147 (3) block diagram (port 0) figure 4-1. block diagram of p00 and p01 internal bus wr pmc rd address tohn output wr port p00/toh0, p01/toh1 pmc0n pmc0 output latch (p0n) selector selector selector wr pu pu0n pu0 wr pm pm0n pm0 ev dd p-ch remarks 1. pu0: pull-up resistor option register 0 pm0: port 0 mode register pmc0: port 0 mode control register rd: port 0 read signal wr: port 0 write signal 2. n = 0, 1 chapter 4 port functions user ? s manual u15862ej3v0ud 148 figure 4-2. block diagram of p02 to p06 internal bus wr pmc rd address nmi, intp0 to intp3 input wr port p02/nmi, p03/intp0, p04/intp1, p05/intp2, p06/intp3 pmc0n pmc0 wr intf intf0n intf0 selector selector wr pu pu0n pu0 wr pm pm0n pm0 noise eliminator edge detector wr intr intr0n intr0 ev dd p-ch output latch (p0n) remarks 1. pu0: pull-up resistor option register 0 pm0: port 0 mode register pmc0: port 0 mode control register intf0: external interrupt falling edge specification register 0 intr0: external interrupt rising edge specification register 0 rd: port 0 read signal wr: port 0 write signal 2. n = 2 to 6 chapter 4 port functions user ? s manual u15862ej3v0ud 149 4.3.2 port 1 port 1 can control input/output in 1-bit units. the number of i/o port pins for port 1 differs according to the product. product i/o port pin count v850es/kf1 ? v850es/kg1 2-bit i/o port v850es/kj1 2-bit i/o port (1) port 1 functions (v850es/kg1, v850es/kj1) { port input/output data can be specified in 1-bit units. specification is made by the port 1 register (p1). { port input/output can be specified in 1-bit units. specification is made by the port 1 mode register (pm1). { on-chip pull-up resistor connection can be specified in 1-bit units. specification is made by pull-up resistor option register 1 (pu1). port 1 includes the following alternate functions. table 4-6. alternate-function pins of port 1 (v850es/kg1, v850es/kj1) pin name alternate function i/o pull note remark p10 ano0 port 1 p11 ano1 i/o yes ? note software pull-up function chapter 4 port functions user ? s manual u15862ej3v0ud 150 (2) registers (a) port 1 register (p1) port 1 register (p1) is an 8-bit register that controls pin level read and output level write. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kg1, v850es/kj1 0 outputs 0 outputs 1 p1n 0 1 control of output data (in output mode) (n = 0, 1) p1 0 0 0 0 0 p11 p10 after reset: undefined r/w address: fffff402h remark in input mode: when read, port 1 (p1) returns the current pin level. when written to, the data written to p1 is written. this has no influence on the input pins. in output mode: when read, port 1 (p1) returns the p1 value. when written to, the value is written to p1 and the written value is immediately output. (b) port 1 mode register (pm1) this is an 8-bit register that specifies the input mode/output mode. this register can be read/written in 8-bit or 1-bit units. caution when used as the ano0 and ano1 pins, set pm1 = ffh at one time. (i) v850es/kg1, v850es/kj1 1 output mode input mode pm1n 0 1 control of i/o mode (n = 0, 1) pm1 1 1 1 1 1 pm11 pm10 after reset: ffh r/w address: fffff422h chapter 4 port functions user ? s manual u15862ej3v0ud 151 (c) pull-up resistor option register 1 (pu1) this is an 8-bit register that specifies the connection of an on-chip pull-up resistor. this register can be read/written in 8-bit or 1-bit units. (i) 850es/kg1, v850es/kj1 0 not connected connected pu1n 0 1 control of on-chip pull-up resistor connection (n = 0, 1) pu1 0 0 0 0 0 pu11 pu10 after reset: 00h r/w address: fffffc42h chapter 4 port functions user ? s manual u15862ej3v0ud 152 (3) block diagram (port 1) figure 4-3. block diagram of p10 and p11 internal bus wr pm rd address wr port p10/ano0, p11/ano1 pm1n pm1 selector selector p-ch n-ch anon output output latch (p1n) pu1n pu1 wr pu ev dd p-ch remarks 1. pm1: port 1 mode register rd: port 1 read signal wr: port 1 write register 2. n = 0, 1 chapter 4 port functions user ? s manual u15862ej3v0ud 153 4.3.3 port 3 port 3 can control input/output in 1-bit units. the number of i/o port pins differs according to the product. product i/o port pin count v850es/kf1 8-bit i/o port v850es/kg1 10-bit i/o port v850es/kj1 10-bit i/o port (1) port 3 functions (v850es/kf1, v850es/kg1, v850es/kj1) { port input/output data can be specified in 1-bit units. specification is made by the port 3 register (p3). { port input/output can be specified in 1-bit units. specification is made by the port 3 mode register (pm3). { port mode/control mode (alternate functions) can be specified in 1-bit units. specification is made by the port 3 mode control register (pmc3). { n-ch open-drain specification can be done in 1-bit units. specification is made by the port 3 function register h (pf3h). { control mode 1/control mode 2 specification can be done in 1-bit units. specification is made by the port 3 function control register (pfc3). { on-chip pull-up resistor connection can be specified in 1-bit units. specification is made by pull-up resistor option register 3 (pu3). chapter 4 port functions user ? s manual u15862ej3v0ud 154 port 3 includes the following alternate functions. table 4-7. alternate-function pins of port 3 (v850es/kf1) pin name alternate function i/o pull note 1 remark p30 txd0 p31 rxd0 p32 asck0 p33 ti000/to00 p34 ti001 p35 ti010/to01 yes ? p38 sda0 note 2 port 3 p39 scl0 note 2 i/o no note 3 n-ch open-drain output notes 1. software pull-up function 2. only for products with an i 2 c bus 3. an on-chip pull-up resistor can be provided by a mask option (only for the mask rom version of the v850es/kf1). table 4-8. alternate-function pins of port 3 (v850es/kg1, v850es/kj1) pin name alternate function i/o pull note remark p30 txd0 p31 rxd0 p32 asck0 p33 ti000/to00 p34 ti001 p35 ti010/to01 yes ? p36 ? p37 ? p38 sda0 note 3 port 3 p39 scl0 note 3 i/o no note 2 n-ch open-drain output notes 1. software pull-up function 2. an on-chip pull-up resistor can be provided by a mask option (only for the mask rom versions of the v850es/kg1 and v850es/kj1). 3. only for products with an i 2 c bus chapter 4 port functions user ? s manual u15862ej3v0ud 155 (2) registers (a) port 3 register (p3) the port 3 register (p3) is a 16-bit register that controls pin level read and output level write. this register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the p3 register are used as the p3h register and as the p3l register, respectively, this register can be read/written in 8-bit or 1-bit units. (i) v850es/kf1 outputs 0 outputs 1 p3n 0 1 control of output data (in output mode) (n = 0 to 5, 8, 9) p3 (p3h note ) after reset: undefined r/w address: fffff406h (p3, p3l), fffff407h (p3h) 0 0 p35 p34 p33 p32 p31 p30 0 0 0 0 0 0 p39 p38 8 9 10 11 12 13 14 15 (p3l) (ii) v850es/kg1, v850es/kj1 outputs 0 outputs 1 p3n 0 1 control of output data (in output mode) (n = 0 to 9) p3 (p3h note ) after reset: undefined r/w address: fffff406h (p3, p3l), fffff407h (p3h) p37 p36 p35 p34 p33 p32 p31 p30 0 0 0 0 0 0 p39 p38 8 9 10 11 12 13 14 15 (p3l) note when reading from or writing to bits 8 to 15 of the p3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the p3h register. remark in input mode: when read, port 3 (p3) returns the current pin level. when written to, the data written to p3 is written. this has no influence on the input pins. in output mode: when read, port 3 (p3) returns the p3 value. when written to, the value is written to p3 and the written value is immediately output. chapter 4 port functions user ? s manual u15862ej3v0ud 156 (b) port 3 mode register (pm3) this is a 16-bit register that specifies the input mode/output mode. this register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the pm3 register are used as the pm3h register and as the pm3l register, respectively, this register can be read/written in 8-bit or 1-bit units. (i) v850es/kf1 1 output mode input mode pm3n 0 1 control of i/o mode (n = 0 to 5, 8, 9) 1 pm35 pm34 pm33 pm32 pm31 pm30 after reset: ffffh r/w address: fffff426h (pm3, pm3l), fffff427 (pm3h) 1 pm3 (pm3h note ) 1 1 1 1 1 pm39 pm38 8 9 10 11 12 13 14 15 (pm3l) (ii) v850es/kg1, v850es/kj1 pm37 output mode input mode pm3n 0 1 control of i/o mode (n = 0 to 9) pm36 pm35 pm34 pm33 pm32 pm31 pm30 after reset: ffffh r/w address: fffff426h (pm3, pm3l), fffff427 (pm3h) 1 pm3 (pm3h note ) 1 1 1 1 1 pm39 pm38 8 9 10 11 12 13 14 15 (pm3l) note when reading from or writing to bits 8 to 15 of the pm3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm3h register. chapter 4 port functions user ? s manual u15862ej3v0ud 157 (c) port 3 mode control register (pmc3) this is a 16-bit register that specifies the port mode/control mode. this register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the pmc3 register are used as the pmc3h register and as the pmc3l register, respectively, this register can be read/written in 8-bit or 1-bit units. (i) v850es/kf1, v850es/kg1, v850es/kj1 pmc3 (pmc3h note 1 ) i/o port scl0 i/o pmc39 0 1 specification of p39 pin operation mode i/o port sda0 i/o pmc38 0 1 specification of p38 pin operation mode i/o port ti010/to01 i/o pmc35 0 1 specification of p35 pin operation mode i/o port ti001 input pmc34 0 1 specification of p34 pin operation mode i/o port ti000/to00 i/o pmc33 0 1 specification of p33 pin operation mode i/o port asck0 input pmc32 0 1 specification of p32 pin operation mode i/o port rxd0 input pmc31 0 1 specification of p31 pin operation mode i/o port txd0 output pmc30 0 1 specification of p30 pin operation mode after reset: 0000h r/w address: fffff446h (pmc3, pmc3l), fffff447h (pmc3h) 0 0 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 00 00 00 pmc39 note pmc38 note 8 9 10 11 12 13 14 15 (pmc3l) notes 1. when reading from or writing to bits 8 to 15 of the pmc3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc3h register. 2. only for products with an i 2 c bus. for all other products, set this bit to 0. chapter 4 port functions user ? s manual u15862ej3v0ud 158 (d) port 3 function register h (pf3h) this is an 8-bit register that specifies n-ch open-drain output. this register can be read/written in 8-bit or 1-bit units. 0 n-ch open-drain output (when used as normal port) n-ch open-drain output (when used as alternate-function) pf3n 0 1 control of n-ch open-drain output (n = 8, 9) pf3h 0 0 0 0 0 pf39 pf38 after reset: 00h r/w address: fffffc67h caution when using p38 and p39 as n-ch open-drain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p3n bit = 1 pf3n bit = 1 pmc3n bit = 1 (e) port 3 function control register (pfc3) this is an 8-bit register that specifies control mode 1/control mode 2. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kf1, v850es/kg1, v850es/kj1 pfc3 ti010 input to01 output pfc35 0 1 specification of p35 pin operation mode in control mode ti000 input to00 output pfc33 0 1 specification of p33 pin operation mode in control mode after reset: 00h r/w address: fffff466h 0 0 pfc35 0 pfc33 0 0 0 caution always set pfc3 register bits 0 to 2, 4, 6, and 7 to 0. chapter 4 port functions user ? s manual u15862ej3v0ud 159 (f) pull-up resistor option register 3 (pu3) this is an 8-bit register that specifies the connection of an on-chip pull-up resistor. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kf1, v850es/kg1, v850es/kj1 0 not connected connected pu3n 0 1 control of on-chip pull-up resistor connection (n = 0 to 5) pu3 0 pu35 pu34 pu33 pu32 pu31 pu30 after reset: 00h r/w address: fffffc46h caution an on-chip pull-up resistor can be provided for p3n by a mask option. n = 8, 9: for the mask rom version of the v850es/kf1 n = 6 to 9: for the mask rom versions of the v850es/kg1 and v850es/kj1 chapter 4 port functions user ? s manual u15862ej3v0ud 160 (3) block diagram (port 3) figure 4-4. block diagram of p30 internal bus wr pmc rd address txd0 output wr port p30/txd0 pmc30 pmc3 selector selector selector wr pu pu30 pu3 wr pm pm30 pm3 ev dd p-ch output latch (p30) remark pu3: pull-up resistor option register 3 pm3: port 3 mode register pmc3: port 3 mode control register rd: port 3 read signal wr: port 3 write signal chapter 4 port functions user ? s manual u15862ej3v0ud 161 figure 4-5. block diagram of p31, p32, and p34 internal bus wr pmc rd address rxd0, asck0, ti001 input wr port p31/rxd0, p32/asck0, p34/ti001 pmc3n pmc3 selector selector wr pu pu3n pu3 wr pm pm3n pm3 ev dd p-ch output latch (p3n) remarks 1. pu3: pull-up resistor option register 3 pm3: port 3 mode register pmc3: port 3 mode control register rd: port 3 read signal wr: port 3 write signal 2. n = 1, 2, 4 chapter 4 port functions user ? s manual u15862ej3v0ud 162 figure 4-6. block diagram of p33 and p35 internal bus wr pmc rd address ti000, ti010 input to00, to01 output wr port p33/ti000/to00 p35/ti010/to01 pmc3n pmc3 selector selector selector wr pu pu3n pu3 wr pm pm3n pm3 wr pf pfc3n pfc3 ev dd p-ch output latch (p3n) remarks 1. pu3: pull-up resistor option register 3 pfc3: port 3 function control register pm3: port 3 mode register pmc3: port 3 mode control register rd: port 3 read signal wr: port 3 write signal 2. n = 3, 5 chapter 4 port functions user ? s manual u15862ej3v0ud 163 figure 4-7. block diagram of p36 and p37 internal bus rd address p36, p37 selector selector wr pm pm3n pm3 wr port ev dd ev dd p-ch medium-voltage input buffer ev ss n-ch mask option output latch (p3n) remarks 1. pm3: port 3 mode register rd: port 3 read signal wr: port 3 write signal 2. n = 6, 7 chapter 4 port functions user ? s manual u15862ej3v0ud 164 figure 4-8. block diagram of p38 and p39 internal bus wr pmc rd address sda0, scl0 output sda0, scl0 input wr port pmc3n pmc3 selector selector selector wr pf pf3n pf3h wr pm pm3n pm3 p38/sda0, p39/scl0 ev dd ev ss mask option n-ch output latch (p3n) remarks 1. pf3h: port 3 function register h pm3: port 3 mode register pmc3: port 3 mode control register rd: port 3 read signal wr: port 3 write signal 2. n = 8, 9 chapter 4 port functions user ? s manual u15862ej3v0ud 165 4.3.4 port 4 port 4 can control input/output in 1-bit units. the v850es/kf1, v850es/kg1, and v850es/kj1 have the same number of i/o port pins for port 4. product i/o port pin count v850es/kf1 3-bit i/o port v850es/kg1 3-bit i/o port v850es/kj1 3-bit i/o port (1) port 4 functions { port input/output data can be specified in 1-bit units. specification is made by the port 4 register (p4). { port input/output can be specified in 1-bit units. specification is made by the port 4 mode register (pm4). { port mode/control mode (alternate function) can be specified in 1-bit units. specification is made by the port 4 mode control register (pmc4). { n-ch open-drain can be specified in 1-bit units. specification is made by the port 4 function register (pf4). { on-chip pull-up resistor connection can be specified in 1-bit units. specification is made by pull-up resistor option register 4 (pu4). port 4 includes the following alternate functions. table 4-9. alternate-function pins of port 4 pin name alternate function i/o pull note remark p40 si00 ? p41 so00 port 4 p42 sck00 i/o yes n-ch open-drain output can be selected. note software pull-up function chapter 4 port functions user ? s manual u15862ej3v0ud 166 (2) registers (a) port 4 register (p4) the port 4 register (p4) is an 8-bit register that controls pin level read and output level write. this register can be read/written in 8-bit or 1-bit units. 0 output 0 output 1 p4n 0 1 control of output data (in output mode) (n = 0 to 2) p4 0 0 0 0 p42 p41 p40 after reset: undefined r/w address: fffff408h remark in input mode: when read, port 4 (p4) returns the current pin level. when written to, the data written to p4 is written. this has no influence on the input pins. in output mode: when read, port 4 (p4) returns the p4 value. when written to, the value is written to p4 and the written value is immediately output. (b) port 4 mode register (pm4) this is an 8-bit register that specifies the input mode/output mode. this register can be read/written in 8-bit or 1-bit units. 1 output mode input mode pm4n 0 1 control of i/o mode (n = 0 to 2) pm4 1 1 1 1 pm42 pm41 pm40 after reset: ffh r/w address: fffff428h chapter 4 port functions user ? s manual u15862ej3v0ud 167 (c) port 4 mode control register (pmc4) this is an 8-bit register that specifies the port mode/control mode. this register can be read/written in 8-bit or 1-bit units. 0 pmc4 0 0 0 0 pmc42 pmc41 pmc40 i/o port sck00 i/o pmc42 0 1 specification of p42 pin operation mode i/o port so00 output pmc41 0 1 specification of p41 pin operation mode i/o port si00 input pmc40 0 1 specification of p40 pin operation mode after reset: 00h r/w address: fffff448h (d) port 4 function register (pf4) this is an 8-bit register that specifies normal output/n-ch open-drain output. this register can be written in 8-bit or 1-bit units. 0 normal output n-ch open-drain output pf4n 0 1 control of normal output/n-ch open-drain output pf4 0 0 0 0 pf42 pf41 0 after reset: 00h r/w address: fffffc68h caution when using p41 and p42 as n-ch open-drain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p4n bit = 1 pf4n bit = 1 pmc4n bit = 1 chapter 4 port functions user ? s manual u15862ej3v0ud 168 (e) pull-up resistor option register 4 (pu4) this is an 8-bit register that specifies the connection of an on-chip pull-up resistor. this register can be read/written in 8-bit or 1-bit units. 0 not connected connected pu4n 0 1 control of on-chip pull-up resistor connection (n = 0 to 2) pu4 0 0 0 0 pu42 pu41 pu40 after reset: 00h r/w address: fffffc48h chapter 4 port functions user ? s manual u15862ej3v0ud 169 (3) block diagram (port 4) figure 4-9. block diagram of p40 internal bus wr pmc rd address si00 input wr port p40/si00 pmc40 pmc4 selector selector wr pu pu40 pu4 wr pm pm40 pm4 ev dd p-ch output latch (p40) remark pu4: pull-up resistor option register 4 pm4: port 4 mode register pmc4: port 4 mode control register rd: port 4 read signal wr: port 4 write signal chapter 4 port functions user ? s manual u15862ej3v0ud 170 figure 4-10. block diagram of p41 internal bus wr pmc rd address so00 output wr port p41/so00 pmc41 pmc4 selector selector selector wr pu pu41 pu4 wr pm pm41 pm4 wr pf pf41 pf4 ev dd p-ch ev dd ev ss p-ch n-ch output latch (p41) remark pu4: pull-up resistor option register 4 pf4: port 4 function register pm4: port 4 mode register pmc4: port 4 mode control register rd: port 4 read signal wr: port 4 write signal chapter 4 port functions user ? s manual u15862ej3v0ud 171 figure 4-11. block diagram of p42 internal bus wr pmc rd address sck00 output sck00 input csi00 input enable signal csi00 output enable signal wr port p42/sck00 pmc42 pmc4 selector selector selector wr pu pu42 pu4 wr pm pm42 pm4 wr pf pf42 pf4 ev dd p-ch ev dd ev ss p-ch n-ch output latch (p42) remark pu4: pull-up resistor option register 0 pf4: port 4 function register pm4: port 4 mode register pmc4: port 4 mode control register rd: port 4 read signal wr: port 4 write signal chapter 4 port functions user?s manual u15862ej3v0ud 172 4.3.5 port 5 port 5 can control input/output in 1-bit units. the v850es/kf1, v850es/kg1, and v850es/kj1 have the same number of i/o port pins for port 5. product i/o port pin count v850es/kf1 6-bit i/o port v850es/kg1 6-bit i/o port v850es/kj1 6-bit i/o port (1) port 5 functions { port input/output data can be specified in 1-bit units. specification is made by the port 5 register (p5). { port input/output can be specified in 1-bit units. specification is made by the port 5 mode register (pm5). { port mode/control mode (alternate function) can be specified in 1-bit units. specification is made by the port 5 mode control register (pmc5). { n-ch open-drain can be specified in 1-bit units. specification is made by the port 5 function register (pf5). { control mode 1/control mode 2 can be specified in 1-bit units. specification is made by the port 5 function control register (pfc5). { on-chip pull-up resistor connection can be specified in 1-bit units. specification is made by pull-up resistor option register 5 (pu5). port 5 includes the following alternate functions. table 4-10. alternate-function pins of port 5 pin name alternate function i/o pull note remark p50 ti011/rtp00/kr0 p51 ti50/rtp01/kr1 p52 to50/rtp02/kr2 p53 sia0/rtp03/kr3 ? p54 soa0/rtp04/kr4 port 5 p55 scka0/rtp05/kr5 i/o yes n-ch open-drain output can be selected. note software pull-up function chapter 4 port functions user?s manual u15862ej3v0ud 173 (2) registers (a) port 5 register (p5) the port 5 register (p5) is an 8-bit register that controls pin level read and output level write. this register can be read/written in 8-bit or 1-bit units. output 0 output 1 p5n 0 1 control of output data (in output mode) (n = 0 to 5) p5 after reset: undefined r/w address: fffff40ah 0 0 p55 p54 p53 p52 p51 p50 remark in input mode: when read, port 5 (p5) returns the current pin level. when written to, the data written to p5 is written. this has no influence on the input pins. in output mode: when read, port 5 (p5) returns the p5 value. when written to, the value is written to p5 and the written value is immediately output. (b) port 5 mode register (pm5) this is an 8-bit register that specifies the input mode/output mode. this register can be read in 8-bit or 1-bit units. 1 output mode input mode pm5n 0 1 control of i/o mode (n = 0 to 5) 1 pm55 pm54 pm53 pm52 pm51 pm50 after reset: ffh r/w address: fffff42ah pm5 chapter 4 port functions user ? s manual u15862ej3v0ud 174 (c) port 5 mode control register (pmc5) this is an 8-bit register that specifies the port mode/control mode. this register can be read/written in 8-bit or 1-bit units. i/o port/kr5 input scka0/rtp05 i/o pmc55 0 1 specification of p55 pin operation mode i/o port/kr4 input soa0/rtp04 output pmc54 0 1 specification of p54 pin operation mode 0 0 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 after reset: 00h r/w address: fffff44ah pmc5 i/o port/kr3 input sia0/rtp03 i/o pmc53 0 1 specification of p53 pin operation mode i/o port/kr2 input to50/rtp0 output pmc52 0 1 specification of p52 pin operation mode i/o port/kr1 input ti50/rtp01 i/o pmc51 0 1 specification of p51 pin operation mode i/o port/kr0 input ti011/rtp00 i/o pmc50 0 1 specification of p50 pin operation mode chapter 4 port functions user ? s manual u15862ej3v0ud 175 (d) port 5 function register 5 (pf5) this is an 8-bit register that specifies normal output/n-ch open-drain output. this register can be read/written in 8-bit or 1-bit units. 0 normal output n-ch open-drain output pf5n 0 1 control of normal output/n-ch open-drain output (n = 4, 5) pf5 0 pf55 pf54 0 0 0 0 after reset: 00h r/w address: fffffc6ah cautions 1. always set pf5 register bits 0 to 3, 6, and 7 to 0. 2. when using p54 and p55 as n-ch open-drain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p5n bit = 1 pf5n bit = 1 pmc5n bit = 1 chapter 4 port functions user ? s manual u15862ej3v0ud 176 (e) port 5 function control register (pfc5) this is an 8-bit register that specifies control mode 1/control mode 2. this register can be read/written in 8-bit or 1-bit units. pfc5 scka0 i/o rtp05 output pfc55 0 1 specification of p55 pin operation mode in control mode sia0 input rtp03 output pfc53 0 1 specification of p53 pin operation mode in control mode soa0 output rtp04 output pfc54 0 1 specification of p54 pin operation mode in control mode after reset: 00h r/w address: fffff46ah 0 0 pfc55 pfc54 pfc53 pfc52 pfc51 pfc50 to50 output rtp02 output pfc52 0 1 specification of p52 pin operation mode in control mode ti50 input rtp01 output pfc51 0 1 specification of p51 pin operation mode in control mode ti011 input rtp00 output pfc50 0 1 specification of p50 pin operation mode in control mode chapter 4 port functions user ? s manual u15862ej3v0ud 177 (f) pull-up resistor option register 5 (pu5) this is an 8-bit register that specifies the connection of an on-chip pull-up resistor. this register can be read/written in 8-bit or 1-bit units. 0 not connected connected pu5n 0 1 control of on-chip pull-up resistor connection (n = 0 to 5) 0 pu55 pu54 pu53 pu52 pu51 pu50 after reset: 00h r/w address: fffffc4ah pu5 chapter 4 port functions user ? s manual u15862ej3v0ud 178 (3) block diagram (port 5) figure 4-12. block diagram of p50, p51, and p53 internal bus wr pmc rd address krn input ti011, ti50, sia0 input rtp0n output wr port p50/ti011/rtp00/kr0, p51/ti50/rtp01/kr1, p53/sia0/rtp03/kr3 pmc5n pmc5 selector selector selector wr pu pu5n pu5 wr pm pm5n pm5 wr pfc pfc5n pfc5 ev dd p-ch output latch (p5n) remarks 1. pu5: pull-up resistor option register 5 pfc5: port 5 function control register pm5: port 5 mode register pmc5: port 5 mode control register rd: port 5 read signal wr: port 5 write signal 2. n = 0, 1, 3 chapter 4 port functions user ? s manual u15862ej3v0ud 179 figure 4-13. block diagram of p52 internal bus wr pmc rd address kr2 input to50 output rtp02 output wr port p52/to50/rtp02/kr2 pmc52 pmc5 selector selector selector selector wr pu pu52 pu5 wr pm pm52 pm5 wr pfc pfc52 pfc5 ev dd p-ch output latch (p52) remark pu5: pull-up resistor option register 5 pfc5: port 5 function control register pm5: port 5 mode register pmc5: port 5 mode control register rd: port 5 read signal wr: port 5 write signal chapter 4 port functions user ? s manual u15862ej3v0ud 180 figure 4-14. block diagram of p54 wr pmc rd address kr4 input rtp04 output soa0 output wr port p54/soa0/rtp04/kr4 pmc54 pmc5 wr pfc pfc54 pfc5 wr pu pu54 pu5 wr pm pm54 pm5 wr pf pf54 pf5 ev dd p-ch ev dd ev ss p-ch n-ch internal bus selector selector selector selector output latch (p54) remark pu5: pull-up resistor option register 5 pf5: port 5 function register pfc5: port 5 function control register pm5: port 5 mode register pmc5: port 5 mode control register rd: port 5 read signal wr: port 5 write signal chapter 4 port functions user ? s manual u15862ej3v0ud 181 figure 4-15. block diagram of p55 wr pmc rd address scka0 output rtp05 output scka0 input kr5 input csia0 output enable signal wr port p55/scka0/rtp05/kr5 pmc55 pmc5 wr pfc pfc55 pfc5 wr pu pu55 pu5 wr pm pm55 pm5 wr pf pf55 pf5 ev dd p-ch ev dd ev ss p-ch n-ch internal bus selector selector selector selector output latch (p55) remark pu5: pull-up resistor option register 5 pf5: port 5 function register pfc5: port 5 function control register pm5: port 5 mode register pmc5: port 5 mode control register rd: port 5 read signal wr: port 5 write signal chapter 4 port functions user ? s manual u15862ej3v0ud 182 4.3.6 port 6 port 6 can control input/output in 1-bit units. the number of i/o port pins for port 6 differs according to the product. product i/o port pin count v850es/kf1 ? v850es/kg1 ? v850es/kj1 16-bit i/o port (1) port 6 functions (v850es/kj1) { port input/output data can be specified in 1-bit units. specification is made by the port 6 register (p6). { port input/output can be specified in 1-bit units. specification is made by the port 6 mode register (pm6). { port mode/control mode (alternate functions) can be specified in 1-bit units. specification is made by the port 6 mode control register (pmc6). { n-ch open-drain can be specified in 1-bit units. specification is made by the port 6 function register (pf6). { control mode 1/control mode 2 can be specified in 1-bit units. specification is made by the port 6 function control register (pfc6h). { on-chip pull-up resistor connection can be specified in 1-bit units. specification is made by pull-up resistor option register 6 (pu6). port 6 includes the following alternate functions. table 4-11. alternate-function pins of port 6 (v850es/kj1) pin name alternate function i/o pull note remark p60 rtp10 p61 rtp11 p62 rtp12 p63 rtp13 p64 rtp14 p65 rtp15 p66 si02 ? p67 so02 p68 sck02 n-ch open-drain output p69 ti040 p610 ti041 p611 to04 p612 ti050 p613 ti051/to05 yes p614 ? port 6 p615 ? i/o no ? note software pull-up function chapter 4 port functions user ? s manual u15862ej3v0ud 183 (2) registers (a) port 6 register (p6) the port 6 register (p6) is a 16-bit register that controls pin level read and output level write. this register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the p6 register are used as the p6h register and as the p6l register, respectively, this register can be read/written in 8-bit or 1-bit units. (i) v850es/kj1 output 0 output 1 p6n 0 1 control of output data (in output mode) (n = 0 to 15) p6 (p6h note ) after reset: undefined r/w address: fffff40ch (p6, p6l), fffff40dh (p6h) p67 p66 p65 p64 p63 p62 p61 p60 p615 p614 p613 p612 p611 p610 p69 p68 8 9 10 11 12 13 14 15 (p6l) note when reading from or writing to bits 8 to 15 of the p6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the p6h register. remark in input mode: when read, port 6 (p6) returns the current pin level. when written to, the data written to p6 is written. this has no influence on the input pins. in output mode: when read, port 6 (p6) returns the p6 value. when written to, the value is written to p6 and the written value is immediately output. chapter 4 port functions user ? s manual u15862ej3v0ud 184 (b) port 6 mode register (pm6) this is a 16-bit register that specifies the input mode/output mode. this register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the pm6 register are used as the pm6h register and as the pm6l register, respectively, this register can be read/written in 8-bit or 1-bit units. (i) v850es/kj1 pm67 output mode input mode pm6n 0 1 control of i/o mode (n = 0 to 15) pm66 pm65 pm64 pm63 pm62 pm61 pm60 after reset: ffffh r/w address: fffff42ch (pm6, pm6l), fffff42d (pm6h) pm615 pm6 (pm6h note ) pm614 pm613 pm612 pm611 pm610 pm69 pm68 8 9 10 11 12 13 14 15 (pm6l) note when reading from or writing to bits 8 to 15 of the pm6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm6h register. chapter 4 port functions user ? s manual u15862ej3v0ud 185 (c) port 6 mode control register (pmc6) this is a 16-bit register that specifies the port mode/control mode. this register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the pmc6 register are used as the pmc6h register and as the pmc6l register, respectively, this register can be read/written in 8-bit or 1-bit units. (i) v850es/kj1 pmc6 (pmc6h note ) i/o port ti051/to05 i/o pmc613 0 1 specification of p613 pin operation mode i/o port ti041 input pmc610 0 1 specification of p610 pin operation mode i/o port ti040 input pmc69 0 1 specification of p69 pin operation mode i/o port sck02 i/o pmc68 0 1 specification of p68 pin operation mode i/o port so02 output pmc67 0 1 specification of p67 pin operation mode i/o port si02 input pmc66 0 1 specification of p66 pin operation mode i/o port rtp1n output pmc6n 0 1 specification of p6n pin operation mode (n = 0 to 5) after reset: 0000h r/w address: fffff44ch (pmc6, pmc6l), fffff44dh (pmc6h) pmc67 pmc66 pmc65 pmc64 pmc63 pmc62 pmc61 pmc60 0 0 pmc613 pmc612 pmc611 pmc610 pmc69 pmc68 8 9 10 11 12 13 14 15 i/o port ti050 input pmc612 0 1 specification of p612 pin operation mode i/o port to04 output pmc611 0 1 specification of p611 pin operation mode (pmc6l) note when reading from or writing to bits 8 to 15 of the pmc6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc6h register. chapter 4 port functions user ? s manual u15862ej3v0ud 186 (d) port 6 function register (pf6) this is a 16-bit register that specifies normal output/n-ch open-drain output. the pf6 register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the pf6 register are used as the pf6h register and as the pf6l register, respectively, this register can be read/written in 8-bit or 1-bit units. (i) v850es/kj1 normal output n-ch open-drain output pf6n 0 1 control of normal output/n-ch open-drain output (n = 7, 8) pf6 (pf6h note ) after reset: 0000h r/w address: fffffc6ch (pf6, ph6l), fffffc6dh (pf6h) pf67 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pf68 8 9 10 11 12 13 14 15 (pf6l) note when reading from or writing to bits 8 to 15 of the pf6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pf6h register. caution always set pf6 register bits 0 to 6 and 9 to 15 to 0. (e) port 6 function control register (pfc6h) this is an 8-bit register that specifies control mode 1/control mode 2. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kj1 pfc6h ti051 input to05 output pfc613 0 1 specification of p613 pin operation mode in control mode after reset: 00h r/w address: fffff46dh 0 0 pfc613 0 0 0 0 0 chapter 4 port functions user ? s manual u15862ej3v0ud 187 (f) pull-up resistor option register 6 (pu6) this is a 16-bit register that specifies the connection of an on-chip pull-up resistor. this register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the pu6 register are used as the pu6h register and as the pu6l register, respectively, this register can be read/written in 8-bit or 1-bit units. (i) v850es/kj1 not connected connected pu6n 0 1 control of on-chip pull-up resistor connection (n = 0 to 13) pu6 (pu6h note ) after reset: 0000h r/w address: fffffc4ch (pu6, pu6l), fffffc4dh (pu6h) pu67 pu66 pu65 pu64 pu63 pu62 pu61 pu60 0 0 pu613 pu612 pu611 pu610 pu69 pu68 8 9 10 11 12 13 14 15 (pu6l) note when reading from or writing to bits 8 to 15 of the pu6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pu6h register. caution an on-chip pull-up resistor can be provided for p614 and p615 (only for the mask rom version of the v850es/kj1). chapter 4 port functions user ? s manual u15862ej3v0ud 188 (3) block diagram (port 6) figure 4-16. block diagram of p60 to p65, and p611 internal bus wr pmc rd address rtp1n, to04 output wr port p60/rtp10, p61/rtp11, p62/rtp12, p63/rtp13, p64/rtp14, p65/rtp15, p611/to04 pmc6n, pmc611 pmc6 selector selector selector wr pu pu6n, pu611 pu6 wr pm pm6n, pm611 pm6 ev dd p-ch output latch (p6n, p611) remarks 1. pu6: pull-up resistor option register 6 pm6: port 6 mode register pmc6: port 6 mode control register rd: port 6 read signal wr: port 6 write signal 2. n = 0 to 5 chapter 4 port functions user ? s manual u15862ej3v0ud 189 figure 4-17. block diagram of p66, p69, p610, and p612 internal bus wr pmc rd address si02, ti040, ti041, ti050 input wr port p66/si02, p69/ti040, p610/ti041, p612/ti050 pmc6n pmc6 selector selector wr pu pu6n pu6 wr pm pm6n pm6 ev dd p-ch output latch (p6n) remarks 1. pu6: pull-up resistor option register 6 pm6: port 6 mode register pmc6: port 6 mode control register rd: port 6 read signal wr: port 6 write signal 2. n = 6, 9, 10, 12 chapter 4 port functions user ? s manual u15862ej3v0ud 190 figure 4-18. block diagram of p67 internal bus wr pmc rd address so02 output wr port p67/so02 pmc67 pmc6 selector selector selector wr pu pu67 pu6 wr pm pm67 pm6 wr pf pf67 pf6 ev dd p-ch ev dd ev ss p-ch n-ch output latch (p67) remark pu6: pull-up resistor option register 6 pf6: port 6 function register pm6: port 6 mode register pmc6: port 6 mode control register rd: port 6 read signal wr: port 6 write signal chapter 4 port functions user ? s manual u15862ej3v0ud 191 figure 4-19. block diagram of p68 internal bus wr pmc rd address sck02 output sck02 input csi02 input enable signal csi02 output enable signal wr port p68/sck02 pmc68 pmc6 selector selector selector wr pu pu68 pu6 wr pm pm68 pm6 wr pf pf68 pf6 ev dd p-ch ev dd ev ss p-ch n-ch output latch (p68) remark pu6: pull-up resistor option register 6 pf6: port 6 function register pm6: port 6 mode register pmc6: port 6 mode control register rd: port 6 read signal wr: port 6 write signal chapter 4 port functions user ? s manual u15862ej3v0ud 192 figure 4-20. block diagram of p613 internal bus wr pmc rd address ti051 input to05 output wr port p613/ti051/to05 pmc613 pmc6 selector selector selector wr pu pu613 pu6 wr pm pm613 pm6 wr pfc pfc613 pfc6 ev dd p-ch output latch (p613) remark pu6: pull-up resistor option register 6 pfc6: port 6 function control register pm6: port 6 mode register pmc6: port 6 mode control register rd: port 6 read signal wr: port 6 write signal chapter 4 port functions user ? s manual u15862ej3v0ud 193 figure 4-21. block diagram of p614 and p615 internal bus rd address p614, p615 selector selector wr pm pm61n pm6 wr port ev dd ev dd p-ch medium-voltage input buffer ev ss n-ch mask option output latch (p61n) remarks 1. pm6: port 6 mode register rd: port 6 read signal wr: port 6 write signal 2. n = 4, 5 chapter 4 port functions user ? s manual u15862ej3v0ud 194 4.3.7 port 7 all the pins of port 7 are fixed to input. the number of input port pins for port 7 differs according to the product. product input port pin count v850es/kf1 8-bit input port v850es/kg1 8-bit input port v850es/kj1 16-bit input port (1) port 7 functions { port input data read is possible in 1-bit units. specification is made by the port 7 register (p7). port 7 includes the following alternate functions. table 4-12. alternate-function pins of port 7 (v850es/kf1, v850es/kg1) pin name alternate function i/o pull note remark p70 ani0 p71 ani1 p72 ani2 p73 ani3 p74 ani4 p77 ani5 p76 ani6 port 7 p77 ani7 input no ? note software pull-up function chapter 4 port functions user ? s manual u15862ej3v0ud 195 table 4-13. alternate-function pins of port 7 (v850es/kj1) pin name alternate function i/o pull note remark p70 ani0 p71 ani1 p72 ani2 p73 ani3 p74 ani4 p77 ani5 p76 ani6 p77 ani7 p78 ani8 p79 ani9 p710 ani10 p711 ani11 p712 ani12 p713 ani13 p714 ani14 port 7 p715 ani15 input no ? note software pull-up function chapter 4 port functions user ? s manual u15862ej3v0ud 196 (2) registers (a) port 7 register (p7) the port 7 register (p7) of the v850es/kf1 and v850es/kg1 is an 8-bit register that reads the pin level. this register can be read in 8-bit units. the port 7 register (p7) of the v850es/kj1 is a 16-bit register that reads the pin level. this register can be read only in 16-bit units. however, when the higher 8 bits of the p7 register are used as the p7h register and the lower 8 bits as the p7l register, they can be read in 8-bit units. (i) v850es/kf1, v850es/kg1 input low level input high level p7n 0 1 input data read (n = 0 to 7) p7 after reset: undefined r address: fffff40eh p77 p76 p75 p74 p73 p72 p71 p70 (ii) v850es/kj1 p715 input low level input high level p7n 0 1 input data read (n = 0 to 12) p7 (p7h note ) p714 p713 p712 p711 p710 p79 p78 after reset: undefined r address: fffff40eh (p7, p7l), fffff40fh (p7h) p77 p76 p75 p74 p73 p72 p71 p70 8 9 10 11 12 13 14 15 (p7l) note when reading from or writing to bits 8 to 15 of the p7 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the p7h register. remark when port 7 (p7) is read, the current pin level is returned. chapter 4 port functions user ? s manual u15862ej3v0ud 197 (3) block diagram (port 7) figure 4-22. block diagram of p70 to p715 internal bus rd anin input p7n/anin remark n = 0 to 15 rd: port 7 read signal chapter 4 port functions user ? s manual u15862ej3v0ud 198 4.3.8 port 8 port 8 controls input/output in 1-bit units. the number of i/o port pins differs according to the product. product i/o port pin count v850es/kf1 ? v850es/kg1 ? v850es/kj1 2-bit i/o port (1) port 8 function (v850es/kj1) { port input/output data can be specified in 1-bit units. specification is made by the port 8 register (p8). { port input/output can be specified in 1-bit units. specification is made by the port 8 mode register (pm8). { port mode/control mode (alternate function) can be specified in 1-bit units. specification is made by the port 8 mode control register (pmc8). { n-ch open-drain can be specified in 1-bit units. specification is made by the port 8 function register (pf8). { control mode 1/control mode 2 can be specified in 1-bit units. specification is made by the port 8 function control register (pfc8). { on-chip pull-up resistor connection can be specified in 1-bit units. specification is made by pull-up resistor option register 8 (pu8). port 8 includes the following alternate functions. table 4-14. alternate-function pins of port 8 (v850es/kj1) pin name alternate function i/o pull note remark p80 rxd2/sda1 note 2 port 8 p81 txd2/scl1 note 2 input yes n-ch open-drain output can be selected. notes 1. software pull-up function 2. only for the pd703216y, 703217y, and 70f3217y chapter 4 port functions user ? s manual u15862ej3v0ud 199 (2) registers (a) port 8 register (p8) the port 8 register (pm8) is an 8-bit register that controls pin level read and output level write. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kj1 0 output 0 output 1 p8n 0 1 control of output data (in output mode) (n = 0, 1) p8 0 0 0 0 0 p81 p80 after reset: undefined r/w address: fffff410h remark in input mode: when read, port 8 (p8) returns the current pin level. when written to, the data written to p8 is written. this has no influence on the input pins. in output mode: when read, port 8 (p8) returns the p8 value. when written to, the value is written to p8 and the written value is immediately output. (b) port 8 mode register (pm8) this is an 8-bit register that specifies the input mode/output mode. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kj1 1 output mode input mode pm8n 0 1 control of i/o mode (n = 0, 1) 1 1 1 1 1 pm81 pm80 after reset: ffh r/w address: fffff430h pm8 chapter 4 port functions user ? s manual u15862ej3v0ud 200 (c) port 8 mode control register (pmc8) this is an 8-bit register that specifies the port mode/control mode. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kj1 0 0 0 0 0 0 pmc81 pmc80 after reset: 00h r/w address: fffff450h pmc8 i/o port txd2/scl1 note i/o pmc81 0 1 specification of p81 pin operation mode i/o port rxd2/sda1 note i/o pmc80 0 1 specification of p80 pin operation mode note only for the pd703216y, 703217y, and 70f3217y. (d) port 8 function register (pf8) this is an 8-bit register that specifies normal output/n-ch open-drain output. this register can be read/written in 8-bit or 1-bit units. (i) 850es/kj1 0 normal output n-ch open-drain output pf8n 0 1 control of normal output/n-ch open-drain output (n = 0, 1) pf8 0 0 0 0 0 pf81 pf80 after reset: 00h r/w address: fffffc70h caution when using p80 and p81 as n-ch open-drain-output alternate-function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p8n bit = 1 pfc8n bit = 0/1 pf8n bit = 1 pmc8n bit = 1 chapter 4 port functions user ? s manual u15862ej3v0ud 201 (e) port 8 function control register (pfc8) this is an 8-bit register that specifies control mode 1/control mode 2. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kj1 pfc8 txd2 output scl1 note i/o pfc81 0 1 specification of p81 pin operation mode in control mode rxd2 input sda1 note i/o pfc80 0 1 specification of p80 pin operation mode in control mode after reset: 00h r/w address: fffff470h 0 0 0 0 0 0 pfc81 pfc80 note only for the pd703216y, 703217y, and 70f3217y. set to 0 for all other products. (f) pull-up resistor option register 8 (pu8) this is an 8-bit register that specifies the connection of an on-chip pull-up resistor. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kj1 0 not connected connected pu8n 0 1 control of on-chip pull-up resistor connection (n = 0, 1) 0 0 0 0 0 pu81 pu80 after reset: 00h r/w address: fffffc50h pu8 chapter 4 port functions user ? s manual u15862ej3v0ud 202 (3) block diagram (port 8) figure 4-23. block diagram of p80 internal bus wr pmc rd address sda1 output rxd2 input sda1 input wr port p80/rxd2/sda1 pmc80 pmc8 wr pfc pfc80 pfc8 selector selector selector selector wr pu pu80 pu8 wr pm pm80 pm8 wr pf pf80 pf8 ev dd p-ch ev dd ev ss p-ch n-ch output latch (p80) remark pu8: pull-up resistor option register 8 pf8: port 8 function register pfc8: port 8 function control register pm8: port 8 mode register pmc8: port 8 mode control register rd: port 8 read signal wr: port 8 write signal chapter 4 port functions user ? s manual u15862ej3v0ud 203 figure 4-24. block diagram of p81 internal bus wr pmc rd address txd2 output scl1 output scl1 input wr port p81/txd2/scl1 pmc81 pmc8 wr pfc pfc81 pfc8 selector selector selector selector wr pu pu81 pu8 wr pm pm81 pm8 wr pf pf81 pf8 ev dd p-ch ev dd ev ss p-ch n-ch output latch (p81) remark pu8: pull-up resistor option register 8 pf8: port 8 function register pfc8: port 8 function control register pm8: port 8 mode register pmc8: port 8 mode control register rd: port 8 read signal wr: port 8 write signal chapter 4 port functions user?s manual u15862ej3v0ud 204 4.3.9 port 9 port 9 controls input/output in 1-bit units. the number of i/o port pins for port 9 differs according to the product. product i/o port pin count v850es/kf1 9-bit i/o port v850es/kg1 16-bit i/o port v850es/kj1 16-bit i/o port (1) port 9 functions { port input/output data can be specified in 1-bit units. specification is made by the port 9 register (p9). { port input/output can be specified in 1-bit units. specification is made by the port 9 mode register (pm9). { port mode/control mode (alternate functions) can be specified in 1-bit units. specification is made by the port 9 mode control register (pmc9). { n-ch open-drain can be specified in 1-bit units. specification is made by the port 9 function register (pf9h). { control mode 1/control mode 2 can be specified in 1-bit units. specification is made by the port 9 function control register (pfc9). { on-chip pull-up resistor connection can be specified in 1-bit units. specification is made by pull-up resistor option register 9 (pu9). { the valid edge of external interrupts (alternate function) can be specified in 1-bit units. the falling edge and the rising edge of the external interrupt are specified by falling edge specification register 9h (intf9h) and rising edge specification register 9h (intr9h), respectively. chapter 4 port functions user?s manual u15862ej3v0ud 205 port 9 includes the following alternate functions. table 4-15. alternate-function pins of port 9 (v850es/kf1) pin name alternate function i/o pull note remark p90 txd1/kr6 p91 rxd1/kr7 p96 ti51/to51 p97 si01 ? p98 so01 p99 sck01 n-ch open-drain output can be specified. p913 intp4 p914 intp5 port 9 p915 intp6 i/o no analog noise elimination note software pull-up function caution when port 9 is used as alternate-function, be sure to set the pfc9 register in addition to the pmc9 register. when the control mode is set by the pmc9n bit of the pmc9 register with the pfc9n bit of the pfc9 register maintaining the initial value (0), output becomes undefined. therefore, to set control mode 2 of port 9, follow the sequence below (n = 0, 1, 6 to 9, 13 to 15). <1> set the pfc9 register first (ofc9n bit = 1) <2> then set the pmc register (pmc9n bit = 1) table 4-16. alternate-function pins of port 9 (v850es/kg1, v850es/kj1) pin name alternate function i/o pull note remark p90 a0/txd1/kr6 p91 a1/rxd1/kr7 p92 a2/ti020/to02 p93 a3/ti021 p94 a4/ti030/to03 p95 a5/ti031 p96 a6/ti51/to51 p97 a7/si01 ? p98 a8/so01 p99 a9/sck01 n-ch open-drain output can be specified. p910 a10/sia1 ? p911 a11/soa1 p912 a12/scka1 n-ch open-drain output can be specified. p913 a13/intp4 p914 a14/intp5 port 9 p915 a15/intp6 i/o no analog noise elimination note software pull-up function chapter 4 port functions user?s manual u15862ej3v0ud 206 (2) registers (a) port 9 register (p9) the port 9 register (p9) is a 16-bit register that controls pin level read and output level write. this register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the p9 register are used as the p9h register and as the p9l register, respectively, these registers can be read/written in 8-bit or 1-bit units. (i) v850es/kf1 output 0 output 1 p9n 0 1 control of output data (in output mode) (n = 0, 1, 6 to 9, 13 to 15) after reset: undefined r/w address: fffff412h (p9, p9l), fffff413h (p9h) p915 p9 (p9h note ) p914 p913 0 0 0 p99 p98 p97 p96 0 0 0 0 p91 p90 8 9 10 11 12 13 14 15 (p9l) (ii) v850es/kg1, v850es/kj1 output 0 output 1 p9n 0 1 control of output data (in output mode) (n = 0 to 15) after reset: undefined r/w address: fffff412h (p9, p9l), fffff413h (p9h) p915 p9 (p9h note ) p914 p913 p912 p911 p910 p99 p98 p97 p96 p95 p94 p93 p92 p91 p90 8 9 10 11 12 13 14 15 (p9l) note when reading from or writing to bits 8 to 15 of the p9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the p9h register. remark in input mode: when read, port 9 (p9) returns the current pin level. when written to, the data written to p9 is written. this has no influence on the input pins. in output mode: when read, port 9 (p9) returns the p9 value. when written to, the value is written to p9 and the written value is immediately output. chapter 4 port functions user ? s manual u15862ej3v0ud 207 (b) port 9 mode register (pm9) this is a 16-bit register that specifies the input mode/output mode. this register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the pm9 register are used as the pm9h register and as the pm9l register, respectively, this register can be read/written in 8-bit or 1-bit units. (i) v850es/kf1 pm97 output mode input mode pm9n 0 1 control of i/o mode (n = 0, 1, 6 to 9, 13 to 15) pm96 1 1 1 1 pm91 pm90 after reset: ffffh r/w address: fffff432h (pm9, pm9l), fffff433h (pm9h) pm915 (pm9l) pm914 pm913 1 1 1 pm99 pm98 8 9 10 11 12 13 14 15 pm9 (pm9h note ) (ii) v850es/kg1, v850es/kj1 pm97 output mode input mode pm9n 0 1 control of i/o mode (n = 0 to 5) pm96 pm95 pm94 pm93 pm92 pm91 pm90 after reset: ffffh r/w address: fffff432h (pm9, pm9l), fffff433h (pm9h) pm915 pm9 (pm9h note ) pm914 pm913 pm912 pm911 pm910 pm99 pm98 8 9 10 11 12 13 14 15 (pm9l) note when reading from or writing to bits 8 to 15 of the pm9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pm9h register. (c) port 9 mode control register (pmc9) this is a 16-bit register that specifies the port mode/control mode. this register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the pmc9 register are used as the pmc9h register and as the pmc9l register, respectively, these registers can be read/written in 8-bit or 1-bit units. caution when used as the a0 to a15 pins, perform 16-bit setting of pmc9 register = ffffh at one time (only for v850es/kg1, v850es/kj1). chapter 4 port functions user ? s manual u15862ej3v0ud 208 (i) v850es/kj1 i/o port intp6 input pmc915 0 1 specification of p915 pin operation mode pmc97 pmc96 0 0 0 0 pmc91 pmc90 after reset: 0000h r/w address: fffff452h (pmc9, pmc9l), fffff453h (pml9h) pmc915 pmc9 (pmc9h note ) pmc914 pmc913 0 0 0 pmc99 pmc98 8 9 10 11 12 13 14 15 i/o port intp5 input pmc914 0 1 specification of p914 pin operation mode i/o port sck01 i/o pmc99 0 1 specification of p99 pin operation mode i/o port intp4 input pmc913 0 1 specification of p612 pin operation mode i/o port so01 output pmc98 0 1 specification of p98 pin operation mode i/o port si01 input pmc97 0 1 specification of p97 pin operation mode i/o port/ti51 input to51 output pmc96 0 1 specification of p96 pin operation mode i/o port/kr7 input rxd1 input pmc91 0 1 specification of p91 pin operation mode i/o port/kr6 input txd1 output pmc90 0 1 specification of p90 pin operation mode (pmc9l) note when reading from or writing to bits 8 to 15 of the pmc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc9h register. chapter 4 port functions user ? s manual u15862ej3v0ud 209 (1/2) (ii) v850es/kg1, v850es/kj1 i/o port a15/intp6 i/o pmc915 0 1 specification of p915 pin operation mode pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 after reset: 0000h r/w address: ffffff452h (pmc9, pmc9l), fffff453h (pmc9h) pmc915 pmc9 (pmc9h note ) pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 8 9 10 11 12 13 14 15 i/o port a14/intp5 i/o pmc914 0 1 specification of p914 pin operation mode i/o port a11/soa1 output pmc911 0 1 specification of p911 pin operation mode i/o port a10/sia1 i/o pmc910 0 1 specification of p910 pin operation mode i/o port a9/sck01 i/o pmc99 0 1 specification of p99 pin operation mode i/o port a13/intp4 i/o pmc913 0 1 specification of p913 pin operation mode i/o port a12/scka1 i/o pmc912 0 1 specification of p912 pin operation mode i/o port a8/so01 output pmc98 0 1 specification of p98 pin operation mode (pmc9l) note when reading from or writing to bits 8 to 15 of the pmc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmc9h register. chapter 4 port functions user ? s manual u15862ej3v0ud 210 (2/2) i/o port a7/si01 i/o pmc97 0 1 specification of p97 pin operation mode i/o port/ti51 a6/to51 output pmc96 0 1 specification of p96 pin operation mode i/o port a5/ti031 i/o pmc95 0 1 specification of p95 pin operation mode i/o port/ti030 input a4/to03 output pmc94 0 1 specification of p94 pin operation mode i/o port a3/ti021 i/o pmc93 0 1 specification of p93 pin operation mode i/o port/ti020 input a2/to02 output pmc92 0 1 specification of p92 pin operation mode i/o port/kr7 input a1/rxd1 i/o pmc91 0 1 specification of p91 pin operation mode i/o port/kr6 input a0/txd1 output pmc90 0 1 specification of p90 pin operation mode chapter 4 port functions user ? s manual u15862ej3v0ud 211 (d) port 9 function register h (pf9h) this is an 8-bit register that specifies normal output/n-ch open-drain output. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kf1 0 normal output n-ch open-drain output pf9n 0 1 control of normal output/n-ch open-drain output (n = 0, 1) pf9h 0 0 0 0 0 pf99 pf98 after reset: 00h r/w address: fffffc73h (ii) v850es/kg1, v850es/kj1 0 normal output n-ch open-drain output pf9n 0 1 control of normal output/n-ch open-drain output (n = 0, 1, 4, 5) pf9h 0 0 pf912 pf911 0 pf99 pf98 after reset: 00h r/w address: fffffc73h caution when using p98, p99, p911, and p912 as n-ch open-drain-output alternate- function pins, set in the following sequence. be sure to set the port latch to 1 before setting the pin to n-ch open-drain output. p9n bit = 1 pfc9n bit = 0/1 pf9n bit = 1 pmc9n bit = 1 (e) port 9 function control register (pfc9) this is a 16-bit register that specifies control mode 1/control mode 2. this register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the pfc9 register are used as the pfc9h register and as the pfc9l register, respectively, these registers can be read/written in 8-bit or 1-bit units. cautions 1. when used as the a0 to a15 pins, perform 16-bit setting of pfc9 register = 0000h at one time (only for v850es/kg1, v850es/kj1). 2. when the control mode is set by the pmc9n bit of the pmc9 register with the pfc9n bit of the pfc9 register maintaining the initial value (0), output becomes undefined. therefore, to set control mode 2 of port 9, set the pfc9n bit to 1 first and then set the pmc9n bit to 1 (n = 0, 1, 6 to 9, 13 to 15) (v850es/kf1 only). chapter 4 port functions user ? s manual u15862ej3v0ud 212 (i) v850es/kf1 pfc9 (pfc9h note ) intp6 input pfc915 1 specification of p915 pin operation mode in control mode intp5 input pfc914 1 specification of p914 pin operation mode in control mode intp4 input pfc913 1 specification of p913 pin operation mode in control mode after reset: 0000h r/w address: fffff472h (pfc9, pfc9l), fffff473h (pfc9h) pfc97 pfc96 0 0 0 0 pfc91 pfc90 pfc910 pfc910 pfc910 0 0 0 pfc99 pfc98 8 9 10 11 12 13 14 15 sck01 i/o pfc99 1 specification of p99 pin operation mode in control mode so01 output pfc98 1 specification of p98 pin operation mode in control mode si01 input pfc97 1 specification of p97 pin operation mode in control mode to51 output pfc96 1 specification of p96 pin operation mode in control mode rxd1 input pfc91 1 specification of p91 pin operation mode in control mode txd1 output pfc90 1 specification of p90 pin operation mode in control mode (pfc9l) note when reading from or writing to bits 8 to 15 of the pfc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pfc9h register. chapter 4 port functions user ? s manual u15862ej3v0ud 213 (1/2) (ii) v850es/kg1, v850es/kj1 pfc9 (pfc9h note ) a15 output intp6 input pfc915 0 1 specification of p915 pin operation mode in control mode a14 output intp5 input pfc914 0 1 specification of p914 pin operation mode in control mode a13 output intp4 input pfc913 0 1 specification of p913 pin operation mode in control mode a12 output scka1 i/o pfc912 0 1 specification of p912 pin operation mode in control mode after reset: 0000h r/w address: fffff472h (pfc9, pfc9l), fffff473h (pfc9h) pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 8 9 10 11 12 13 14 15 a11 output soa1 output pfc911 0 1 specification of p911 pin operation mode in control mode a10 output sia1 input pfc910 0 1 specification of p910 pin operation mode in control mode a9 output sck01 i/o pfc99 0 1 specification of p99 pin operation mode in control mode a8 output so01 output pfc98 0 1 specification of p98 pin operation mode in control mode (pfc9l) note when reading from or writing to bits 8 to 15 of the pfc9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pfc9h register. chapter 4 port functions user ? s manual u15862ej3v0ud 214 (2/2) a7 output si01 input pfc97 0 1 specification of p97 pin operation mode in control mode a6 output to51 output pfc96 0 1 specification of p96 pin operation mode in control mode a5 output ti031 input pfc95 0 1 specification of p95 pin operation mode in control mode a4 output to03 output pfc94 0 1 specification of p94 pin operation mode in control mode a3 output ti021 input pfc93 0 1 specification of p93 pin operation mode in control mode a2 output to02 output pfc92 0 1 specification of p92 pin operation mode in control mode a1 output rxd1 input pfc91 0 1 specification of p91 pin operation mode in control mode a0 output txd1 output pfc90 0 1 specification of p90 pin operation mode in control mode chapter 4 port functions user ? s manual u15862ej3v0ud 215 (f) pull-up resistor option register 9 (pu9) this is a 16-bit register that specifies the connection of an on-chip pull-up resistor. this register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the pu9 register are used as the pu9h register and as the pu9l register, respectively, these registers can be read/written in 8-bit or 1-bit units. (i) v850es/kf1, v850es/kg1 not connected connected pu9n 0 1 control of on-chip pull-up resistor connection (n = 0, 1, 6 to 9, 13 to 15) pu9 (pu9h note ) after reset: 0000h r/w address: fffffc52h (pu9, pu9l), fffffc53h (pu9h) pu97 pu96 0 0 0 0 pu91 pu90 pu915 pu914 pu913 0 0 0 pu99 pu98 8 9 10 11 12 13 14 15 (pu9l) (ii) v850es/kj1 not connected connected pu9n 0 1 control of on-chip pull-up resistor connection (n = 0 to 15) pu9 (pu9h note ) after reset: 0000h r/w address: fffffc52h (pu9, pu9l), fffffc53h (pu9h) pu97 pu96 pu95 pu94 pu93 pu92 pu91 pu90 pu915 pu914 pu913 pu912 pu911 pu910 pu99 pu98 8 9 10 11 12 13 14 15 (pu9l) note when reading from or writing to bits 8 to 15 of the pu9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pu9h register. chapter 4 port functions user ? s manual u15862ej3v0ud 216 (g) external interrupt falling edge specification register 9h (intf9h) this is an 8-bit register that specifies the falling edge as the detection edge for the external interrupt pin. this register can be read/written in 8-bit or 1-bit units. caution when switching from the external interrupt function (alternate function) to the port function, edge detection may be performed. therefore, set the port mode after setting intf9n bit = intr9n bit = 0. (i) v850es/kf1, v850es/kg1, v850es/kj1 intf915 intf9h intf914 intf913 0 0 0 0 0 after reset: 00h r/w address: fffffc13h remark for specification of the valid edge, refer to table 4-17 . (h) external interrupt rising edge specification register 9h (intr9h) this is an 8-bit register that specifies the rising edge as the detection edge for the external interrupt pin. this register can be read/written in 8-bit or 1-bit units. caution when switching from the external interrupt function (alternate function) to the port function, edge detection may be performed. therefore, set the port mode after setting intf9n bit = intr9n bit = 0. (i) v850es/kf1, v850es/kg1, v850es/kj1 intr915 intr9h intr914 intr913 0 0 0 0 0 after reset: 00h r/w address: fffffc33h remark for specification of the valid edge, refer to table 4-17 . table 4-17. valid edge specification intf9n intr9n specification of valid edge (n = 13 to 15) 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 13 to 15: control of intp4 to intp6 pins chapter 4 port functions user ? s manual u15862ej3v0ud 217 (3) block diagram (port 9) figure 4-25. block diagram of p90, p92, p94, and p96 internal bus wr pmc rd address kr6, ti020, ti030, ti51 input an output txd1, to02,to03, to51 input output buffer off signal wr port p90/a0/txd1/kr6, p92/a2/ti020/to02, p94/a4/ti030/to03, p96/a6/ti51/to51 pmc9n pmc9 selector selector selector selector selector wr pu pu9n pu9 wr pm pm9n pm9 wr pfc pfc9n pfc9 ev dd p-ch output latch (p9n) remarks 1. pu9: pull-up resistor option register 9 pfc9: port 9 function control register pm9: port 9 mode register pmc9: port 9 mode control register rd: port 9 read signal wr: port 9 write signal 2. n = 0, 2, 4, 6 chapter 4 port functions user ? s manual u15862ej3v0ud 218 figure 4-26. block diagram of p91 internal bus wr pmc rd address kr7 input a1 output rxd1 input output buffer off signal wr port p91/a1/rxd1/kr7 pmc91 pmc9 selector selector selector selector wr pu pu91 pu9 wr pm pm91 pm9 wr pfc pfc91 pfc9 ev dd p-ch output latch (p91) remark pu9: pull-up resistor option register 9 pfc9: port 9 function control register pm9: port 9 mode register pmc9: port 9 mode control register rd: port 9 read signal wr: port 9 write signal chapter 4 port functions user ? s manual u15862ej3v0ud 219 figure 4-27. block diagram of p93, p95, p97, and p910 internal bus wr pmc rd address output buffer off signal wr port pmc9n pmc9 selector selector selector selector wr pu pu9n pu9 wr pm pm9n pm9 wr pfc pfc9n pfc9 ev dd p-ch an output p93/a3/ti021, p95/a5/ti031, p97/a7/si01, p910/a10/sia1 ti021, ti031, si01, sia1 input output latch (p9n) remarks 1. pu9: pull-up resistor option register 9 pfc9: port 9 function control register pm9: port 9 mode register pmc9: port 9 mode control register rd: port 9 read signal wr: port 9 write signal 2. n = 3, 5, 7, 10 chapter 4 port functions user ? s manual u15862ej3v0ud 220 figure 4-28. block diagram of p98 and p911 internal bus wr pmc rd address an output so01, soa1 output wr port p98/a8/so01, p911/a11/soa1 pmc9n pmc9 wr pfc pfc9n pfc9 output buffer off signal selector selector selector selector selector wr pu pu9n pu9 wr pm pm9n pm9 wr pf pf9n pf9h ev dd p-ch ev dd ev ss p-ch n-ch output latch (p9n) remarks 1. pu9: pull-up resistor option register 9 pf9h: port 9 function register h pfc9: port 9 function control register pm9: port 9 mode register pmc9: port 9 mode control register rd: port 9 read signal wr: port 9 write signal 2. n = 8, 11 chapter 4 port functions user ? s manual u15862ej3v0ud 221 figure 4-29. block diagram of p99 and p912 internal bus wr pmc rd address an output sck01, scka1 output sck01, scka1 input wr port p99/a9/sck01, p912/a12/scka1 pmc9n pmc9 wr pfc pfc9n pfc9 a9 output csi01, csia1 output enable signal selector selector selector selector selector selector wr pu pu9n pu9 wr pm pm9n pm9 wr pf pf9n pf9h ev dd p-ch ev dd ev ss p-ch n-ch output latch (p9n) remarks 1. pu9: pull-up resistor option register 9 pf9h: port 9 function register h pfc9: port 9 function control register pm9: port 9 mode register pmc9: port 9 mode control register rd: port 9 read signal wr: port 9 write signal 2. n = 9, 12 chapter 4 port functions user ? s manual u15862ej3v0ud 222 figure 4-30. block diagram of p913 to p915 internal bus wr pmc rd address an output wr port p913/a13/intp4, p914/a14/intp5, p915/a15/intp6 pmc9n pmc9 wr pfc pfc9n pfc9 output buffer off signal selector selector selector selector wr pu pu9n pu9 wr pm pm9n pm9 wr intf intf9n intf9h wr intr intr9n intr9h ev dd p-ch intp4 to intp6 input noise eliminator noise detector output latch (p9n) remarks 1. pu9: pull-up resistor option register 9 pfc9: port 9 function control register intf9h: external interrupt falling edge specification register 9h intr9h: external interrupt rising edge specification register 9h pm9: port 9 mode register pmc9: port 9 mode control register rd: port 9 read signal wr: port 9 write signal 2. n = 13 to 15 chapter 4 port functions user ? s manual u15862ej3v0ud 223 4.3.10 port cd port cd can control input/output in 1-bit units. the number of i/o port pins for port cd differs according to the product. product i/o port pin count v850es/kf1 ? v850es/kg1 ? v850es/kj1 4-bit i/o port (1) port cd functions (v850es/kj1) { port input/output data can be specified in 1-bit units. specification is made by the port cd register (pcd). { port input/output can be specified in 1-bit units. specification is made by the port cd mode register (pmcd). port cd does not have alternate-function pins. table 4-18. alternate-function pins of port cd (v850es/kj1) pin name alternate function i/o pull note remark pcd0 ? pcd1 ? pcd2 ? port cd pcd3 ? i/o no ? note software pull-up function chapter 4 port functions user ? s manual u15862ej3v0ud 224 (2) registers (a) port cd register (pcd) the port cd register (pcd) is an 8-bit register that controls pin level read and output level write. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kj1 0 output 0 output 1 pcdn 0 1 control of output data (in output mode) (n = 0 to 3) pcd 0 0 0 pcd3 pcd2 pcd1 pcd0 after reset: undefined r/w address: fffff00eh remark in input mode: when read, port cd (pcd) returns the current pin level. when written to, the data written to pcd is written. this has no influence on the input pins. in output mode: when read, port cd (pcd) returns the pcd value. when written to, the value is written to pcd and the written value is immediately output. chapter 4 port functions user ? s manual u15862ej3v0ud 225 (b) port cd mode register (pmcd) this is an 8-bit register that specifies the input mode/output mode. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kj1 1 output mode input mode pmcdn 0 1 control of i/o mode (n = 0 to 3) pmcd 1 1 1 pmcd3 pmcd2 pmcd1 pmcd0 after reset: ffh r/w address: fffff02eh chapter 4 port functions user ? s manual u15862ej3v0ud 226 (3) block diagram (port cd) figure 4-31. block diagram of pcd0 to pcd3 internal bus wr pm rd address wr port pcd0, pcd1, pcd2, pcd3 pmcdn pmcd selector selector output latch (pcdn) remarks 1. pmcd: port cd mode register rd: port cd read signal wr: port cd write signal 2. n = 0 to 3 chapter 4 port functions user ? s manual u15862ej3v0ud 227 4.3.11 port cm port cm can control input/output in 1-bit units. the number of i/o port pins for port cm differs according to the product. product i/o port pin count v850es/kf1 4-bit i/o port v850es/kg1 4-bit i/o port v850es/kj1 6-bit i/o port (1) port cm functions { port input/output data can be specified in 1-bit units. specification is made by the port cm register (pcm). { port input/output can be specified in 1-bit units. specification is made by the port cm mode register (pmcm). { port mode/control mode (alternate functions) can be specified 1-bit units. specification is made by the port cm mode control register (pmccm). port cm includes the following alternate functions. table 4-19. alternate-function pins of port cm (v850es/kf1, v850es/kg1) pin name alternate function i/o pull note remark pcm0 wait pcm1 clkout pcm2 hldak port cm pcm3 hldqr i/o no ? note software pull-up function table 4-20. alternate-function pins of port cm (v850es/kj1) pin name alternate function i/o pull note remark pcm0 wait pcm1 clkout pcm2 hldak pcm3 hldqr pcm4 ? port cm pcm5 ? i/o no ? note software pull-up function chapter 4 port functions user ? s manual u15862ej3v0ud 228 (2) registers (a) port cm register (pcm) the port cm register (pcm) is an 8-bit register that controls pin level read and output level write. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kf1, v850es/kg1 output 0 output 1 pcmn 0 1 control of output data (in output mode) (n = 0 to 3) after reset: undefined r/w address: fffff00ch 0 pcm 0 0 0 pcm3 pcm2 pcm1 pcm0 (ii) v850es/kj1 output 0 output 1 pcmn 0 1 control of output data (in output mode) (n = 0 to 5) after reset: undefined r/w address: fffff00ch 0 pcm 0 pcm5 pcm4 pcm3 pcm2 pcm1 pcm0 remark in input mode: when read, port cm (pcm) returns the current pin level. when written to, the data written to pcm is written. this has no influence on the input pins. in output mode: when read, port cm (pcm) returns the pcm value. when written to, the value is written to pcm and the written value is immediately output. chapter 4 port functions user ? s manual u15862ej3v0ud 229 (b) port cm mode register (pmcm) this is an 8-bit register that specifies the input mode/output mode. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kf1, v850es/kg1 output mode input mode pmcmn 0 1 control of i/o mode (n = 0 to 3) after reset: ffh r/w address: fffff02ch 1 pmcm 1 1 1 pmcm3 pmcm2 pmcm1 pmcm0 (ii) v850es/kj1 output mode input mode pmcmn 0 1 control of i/o mode (n = 0 to 5) after reset: ffh r/w address: fffff02ch 1 pmcm 1 pmcm5 pmcm4 pmcm3 pmcm2 pmcm1 pmcm0 chapter 4 port functions user ? s manual u15862ej3v0ud 230 (c) port cm mode control register (pmccm) this is an 8-bit register that specifies the port mode/control mode. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kf1, v850es/kg1, v850es/kj1 0 pmccm 0 0 0 pmccm3 pmccm2 pmccm1 pmccm0 i/o port hldqr input pmccm3 0 1 specification of pcm3 pin operation mode i/o port hldak output pmccm2 0 1 specification of pcm2 pin operation mode i/o port clkout output pmccm1 0 1 specification of pcm1 pin operation mode i/o port wait input pmccm0 0 1 specification of pcm0 pin operation mode after reset: 00h r/w address: fffff04ch chapter 4 port functions user ? s manual u15862ej3v0ud 231 (3) block diagram (port cm) figure 4-32. block diagram of pcm0 and pcm3 internal bus wr pmc rd address wait, hldrq input wr port pcm0/wait, pcm3/hldrq pmccmn pmccm selector selector wr pm pmcmn pmcm output latch (pcmn) remarks 1. pmcm: port cm mode register pmccm: port cm mode control register rd: port cm read signal wr: port cm write signal 2. n = 0, 3 chapter 4 port functions user ? s manual u15862ej3v0ud 232 figure 4-33. block diagram of pcm1 and pcm2 internal bus wr pmc rd address clkout, hldak output signal wr port pcm1/clkout, pcm2/hldak pmccmn pmccm selector selector selector wr pm pmcmn pmcm output latch (pcmn) remarks 1. pmcm: port cm mode register pmccm: port cm mode control register rd: port cm read signal wr: port cm write signal 2. n = 1, 2 chapter 4 port functions user ? s manual u15862ej3v0ud 233 figure 4-34. block diagram of pcm4 and pcm5 internal bus wr pm rd address wr port pcm4, pcm5 pmcmn pmcm selector selector output latch (pcmn) remarks 1. pmcm: port cm mode register rd: port cm read signal wr: port cm write signal 2. n = 4, 5 chapter 4 port functions user ? s manual u15862ej3v0ud 234 4.3.12 port cs port cs can control input/output in 1-bit units. the number of i/o port pins for port cs differs according to the product. product i/o port pin count v850es/kf1 2-bit i/o port v850es/kg1 2-bit i/o port v850es/kj1 8-bit i/o port (1) port cs functions { port input/output data can be specified in 1-bit units. specification is made by the port cs register (pcs). { port input/output can be specified in 1-bit units. specification is made by the port cs mode register (pmcs). { port mode/control mode (alternate functions) can be specified 1-bit units. specification is made by the port cs mode control register (pmccs). port cs includes the following alternate functions. table 4-21. alternate-function pins of port cs (v850es/kf1, v850es/kg1) pin name alternate function i/o pull note remark pcs0 cs0 port cs pcs1 cs1 i/o no ? note software pull-up function table 4-22. alternate-function pins of port cs (v850es/kj1) pin name alternate function i/o pull note remark pcs0 cs0 pcs1 cs1 pcs2 cs2 pcs3 cs3 pcs4 ? pcs5 ? pcs6 ? port cs pcs7 ? i/o no ? note software pull-up function chapter 4 port functions user ? s manual u15862ej3v0ud 235 (2) registers (a) port cs register (pcs) the port cs register (pcs) is an 8-bit register that controls pin level read and output level write. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kf1, v850es/kg1 output 0 output 1 pcsn 0 1 control of output data (in output mode) (n = 0, 1) after reset: undefined r/w address: fffff008h 0 pcs 0 0 0 0 0 pcs1 pcs0 (ii) v850es/kj1 output 0 output 1 pcsn 0 1 control of output data (in output mode) (n = 0 to 7) after reset: undefined r/w address: fffff008h pcs7 pcs pcs6 pcs5 pcs4 pcs3 pcs2 pcs1 pcs0 remark in input mode: when read, port cs (pcs) returns the current pin level. when written to, the data written to pcs is written. this has no influence on the input pins. in output mode: when read, port cs (pcs) returns the pcs value. when written to, the value is written to pcs and the written value is immediately output. chapter 4 port functions user ? s manual u15862ej3v0ud 236 (b) port cs mode register (pmcs) this is an 8-bit register that specifies the input mode/output mode. this register can be written in 8-bit or 1-bit units. (i) v850es/kf1, v850es/kg1 1 output mode input mode pmcsn 0 1 control of i/o mode (n = 0, 1) pmcs 1 1 1 1 1 pmcs1 pmcs0 after reset: ffh r/w address: fffff028h (ii) v850es/kj1 pmcs7 output mode input mode pmcsn 0 1 control of i/o mode (n = 0 to 7) pmcs pmcs6 pmcs5 pmcs4 pmcs3 pmcs2 pmcs1 pmcs0 after reset: ffh r/w address: fffff028h chapter 4 port functions user ? s manual u15862ej3v0ud 237 (c) port cs mode control register (pmccs) this is an 8-bit register that specifies the port mode/control mode. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kf1, v850es/kg1 0 i/o port csn output pmccsn 0 1 specification of pcsn pin operation mode (n = 0, 1) pmccs 0 0 0 0 0 pmccs1 pmccs0 after reset: 00h r/w address: fffff048h (ii) v850es/kj1 0 i/o port csn output pmccsn 0 1 specification of pcsn pin operation mode (n = 0 to 3) pmccs 0 0 0 pmccs3 pmccs2 pmccs1 pmccs0 after reset: 00h r/w address: fffff048h chapter 4 port functions user ? s manual u15862ej3v0ud 238 (3) block diagram (port cs) figure 4-35. block diagram of pcs0 to pcs3 wr pmc rd address csn output output buffer off signal wr port pcs0/cs0, pcs1/cs1, pcs2/cs2, pcs3/cs3 pmccsn pmccs wr pm pmcsn pmcs output latch (pcsn) internal bus selector selector selector selector remarks 1. pmcs: port cs mode register pmccs: port cs mode control register rd: port cs read signal wr: port cs write signal 2. n = 0 to 3 chapter 4 port functions user ? s manual u15862ej3v0ud 239 figure 4-36. block diagram of pcs4 to pcs7 wr pm rd address wr port pcs4, pcs5, pcs6, pcs7 pmcsn pmcs output latch (pcsn) internal bus selector selector remarks 1. pmcs: port cs mode register 2. n = 4 to 7 chapter 4 port functions user ? s manual u15862ej3v0ud 240 4.3.13 port ct port ct can control input/output in 1-bit units. the number of i/o port pins for port ct differs according to the product. product i/o port pin count v850es/kf1 4-bit i/o port v850es/kg1 4-bit i/o port v850es/kj1 8-bit i/o port (1) port ct functions { port input/output data can be specified in 1-bit units. specification is made by the port ct register (pct). { port input/output can be specified in 1-bit units. specification is made by the port ct mode register (pmct). { port mode/control mode (alternate functions) can be specified 1-bit units. specification is made by the port ct mode control register (pmcct). port ct includes the following alternate functions. table 4-23. alternate-function pins of port ct (v850es/kf1, v850es/kg1) pin name alternate function i/o pull note remark pct0 wr0 pct1 wr1 pct4 rd port ct pct6 astb i/o no ? note software pull-up function table 4-24. alternate-function pins of port ct (v850es/kj1) pin name alternate function i/o pull note remark pct0 wr0 pct1 wr1 pct2 ? pct3 ? pct4 rd pct5 ? pct6 astb port ct pct7 ? i/o no ? note software pull-up function chapter 4 port functions user ? s manual u15862ej3v0ud 241 (2) registers (a) port ct register (pct) the port ct register (pct) is an 8-bit register that controls pin level read and output level write. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kf1, v850es/kg1 0 output 0 output 1 pctn 0 1 control of output data (in output mode) (n = 0, 1, 4, 6) pct pct6 0 pct4 0 0 pct1 pct0 after reset: undefined r/w address: fffff00ah (ii) v850es/kj1 pct7 output 0 output 1 pctn 0 1 control of output data (in output mode) (n = 0 to 7) pct pct6 pct5 pct4 pct3 pct2 pct1 pct0 after reset: undefined r/w address: fffff00ah remark in input mode: when read, port ct (pct) returns the current pin level. when written to, the data written to pct is written. this has no influence on the input pins. in output mode: when read, port ct (pct) returns the pct value. when written to, the value is written to pct and the written value is immediately output. chapter 4 port functions user ? s manual u15862ej3v0ud 242 (b) port ct mode register (pmct) this is an 8-bit register that specifies the input mode/output mode. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kf1, v850es/kg1 1 output mode input mode pmctn 0 1 control of i/o mode (n = 0, 1, 4, 6) pmct pmct6 1 pmct4 1 1 pmct1 pmct0 after reset: ffh r/w address: fffff02ah (ii) v850es/kj1 pmct7 output mode input mode pmctn 0 1 control of i/o mode (n = 0 to 7) pmct pmct6 pmct5 pmct4 pmct3 pmct2 pmct1 pmct0 after reset: ffh r/w address: fffff02ah chapter 4 port functions user ? s manual u15862ej3v0ud 243 (c) port ct mode control register (pmcct) this is an 8-bit register that specifies the port mode/control mode. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kf1, v850es/kg1, v850es/kj1 0 pmcct pmcct6 0 pmcct4 0 0 pmcct1 pmcct0 i/o port astb output pmcct6 0 1 specification of pct6 pin operation mode i/o port rd output pmcct4 0 1 specification of pct4 pin operation mode i/o port wr1 output pmcct1 0 1 specification of pct1 pin operation mode i/o port wr0 output pmcct0 0 1 specification of pct0 pin operation mode after reset: 00h r/w address: fffff04ah chapter 4 port functions user ? s manual u15862ej3v0ud 244 (3) block diagram (port ct) figure 4-37. block diagram of pct0, pct1, pct4, and pct6 wr pmc rd wr0, wr1, rd, astb output wr port pct0/wr0, pct1/wr1, pct4/rd, pct6/astb pmcctn pmcct wr pm pmctn pmct address output buffer off signal output latch (pctn) internal bus selector selector selector selector remarks 1. pmct: port ct mode register pmcct: port ct mode control register rd: port ct read signal wr: port ct write signal 2. n = 0, 1, 4, 6 chapter 4 port functions user ? s manual u15862ej3v0ud 245 figure 4-38. block diagram of pct2, pct3, pct5, and pct7 wr pm rd wr port pct2, pct3, pct5, pct7 pmctn pmct address output latch (pctn) internal bus selector selector remarks 1. pmct: port ct mode register rd: port cm read signal wr: port cm write signal 2. n = 2, 3, 5, 7 chapter 4 port functions user ? s manual u15862ej3v0ud 246 4.3.14 port dh port dh can control input/output in 1-bit units. the number of i/o port pins for port dh differs according to the product. product i/o port pin count v850es/kf1 ? v850es/kg1 6-bit i/o port v850es/kj1 8-bit i/o port (1) port dh functions (v850es/kg1, v850es/kj1) { port input/output data can be specified in 1-bit units. specification is made by the port dh register (pdh). { port input/output can be specified in 1-bit units. specification is made by the port dh mode register (pmdh). { port mode/control mode (alternate functions) can be specified 1-bit units. specification is made by the port dh mode control register (pmcdh). port dh includes the following alternate functions. table 4-25. alternate-function pins of port dh (v850es/kg1) pin name alternate function i/o pull note remark pdh0 a16 pdh1 a17 pdh2 a18 pdh3 a19 pdh4 a20 port dh pdh5 a21 i/o no ? note software pull-up function table 4-26. alternate-function pins of port dh (v850es/kj1) pin name alternate function i/o pull note remark pdh0 a16 pdh1 a17 pdh2 a18 pdh3 a19 pdh4 a20 pdh5 a21 pdh6 a22 port dh pdh7 a23 i/o no ? note software pull-up function chapter 4 port functions user ? s manual u15862ej3v0ud 247 (2) registers (a) port dh register (pdh) the port dh register (pdh) is an 8-bit register that controls pin level read and output level write. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kg1 output 0 output 1 pdhn 0 1 control of output data (in output mode) (n = 0 to 5) pdh after reset: undefined r/w address: fffff006h 0 0 pdh5 pdh4 pdh3 pdh2 pdh1 pdh0 (ii) v850es/kj1 output 0 output 1 pdhn 0 1 control of output data (in output mode) (n = 0 to 7) pdh after reset: undefined r/w address: fffff006h pdh7 pdh6 pdh5 pdh4 pdh3 pdh2 pdh1 pdh0 remark in input mode: when read, port dh (pdh) returns the current pin level. when written to, the data written to pdh is written. this has no influence on the input pins. in output mode: when read, port dh (pdh) returns the pdh value. when written to, the value is written to pdh and the written value is immediately output. chapter 4 port functions user ? s manual u15862ej3v0ud 248 (b) port dh mode register (pmdh) this is an 8-bit register that specifies the input mode/output mode. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kg1 1 output mode input mode pmdhn 0 1 control of i/o mode (n = 0 to 5) 1 pmdh5 pmdh4 pmdh3 pmdh2 pmdh1 pmdh0 after reset: ffh r/w address: fffff026h pmdh (ii) v850es/kj1 pmdh7 output mode input mode pmdhn 0 1 control of i/o mode (n = 0 to 7) pmdh6 pmdh5 pmdh4 pmdh3 pmdh2 pmdh1 pmdh0 after reset: ffh r/w address: fffff026h pmdh chapter 4 port functions user ? s manual u15862ej3v0ud 249 (c) port dh mode control register (pmcdh) this is an 8-bit register that specifies the port mode/control mode. this register can be read/written in 8-bit or 1-bit units. (i) v850es/kg1 i/o port am output (address bus output) (m = 16 to 21) pmcdhn 0 1 specification of pdhn pin operation mode (n = 0 to 5) 0 0 pmcdh5 pmcdh4 pmcdh3 pmcdh2 pmcdh1 pmcdh0 after reset: 00h r/w address: fffff046h pmcdh caution when specifying the port mode/control mode (alternate function) for each bit, pay careful attention to the operation of the alternate functions. (ii) v850es/kj1 i/o port am output (address bus output) (m = 16 to 23) pmcdhn 0 1 specification of pdhn pin operation mode (n = 0 to 7) pmcdh7 pmcdh6 pmcdh5 pmcdh4 pmcdh3 pmcdh2 pmcdh1 pmcdh0 after reset: 00h r/w address: fffff046h pmcdh caution when specifying the port mode/control mode (alternate function) for each bit, pay careful attention to the operation of the alternate functions. chapter 4 port functions user ? s manual u15862ej3v0ud 250 (3) block diagram (port dh) figure 4-39. block diagram of pdh0 to pdh7 wr pmc rd am output wr port pdh0/a16, pdh1/a17, pdh2/a18, pdh3/a19, pdh4/a20, pdh5/a21, pdh6/a22, pdh7/a23 pmcdhn pmcdh wr pm pmdhn pmdh address output buffer off signal output latch (pchn) internal bus selector selector selector selector remarks 1. pmdh: port dh mode register pmcdh: port dh mode control register rd: port dh read signal wr: port dh write signal 2. n = 0 to 7 m = 16 to 23 chapter 4 port functions user ? s manual u15862ej3v0ud 251 4.3.15 port dl port dl can control input/output in 1-bit units. the number of i/o port pins for port 1 differs according to the product. product i/o port pin count v850es/kf1 16-bit i/o port v850es/kg1 16-bit i/o port v850es/kj1 16-bit i/o port (1) port dl functions { port input/output data can be specified in 1-bit units. specification is made by the port dl register (pdl). { port input/output can be specified in 1-bit units. specification is made by the port dl mode register (pmdl). { port mode/control mode (alternate function) can be specified in 1-bit units. specification is made by the port dl mode control register (pmcdl). port dl includes the following alternate functions. table 4-27. alternate-function pins of port dl pin name alternate function i/o pull note remark pdl0 ad0 pdl1 ad1 pdl2 ad2 pdl3 ad3 pdl4 ad4 pdl5 ad5 pdl6 ad6 pdl7 ad7 pdl8 ad8 pdldl ad9 pdl10 ad10 pdl11 ad11 pdl12 ad12 pdl13 ad13 pdl14 ad14 port dl pdl15 ad15 i/o no ? note software pull-up function chapter 4 port functions user ? s manual u15862ej3v0ud 252 (2) registers (a) port dl register (pdl) the port dl register (pdl) is an 16-bit register that controls pin level read and output level write. this register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the pdl register are used as the pdlh register and as the pdll register, respectively, these registers can be read/written in 8-bit or 1-bit units. pdl15 outputs 0 outputs 1 pdln 0 1 control of output data (in output mode) (n = 0 to 15) pdl (pdlh note ) pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 after reset: undefined r/w address: fffff004h (pdl, pdll), fffff005h (pdlh) pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 8 9 10 11 12 13 14 15 (pdll) note when reading from or writing to bits 8 to 15 of the pdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pdlh register. remark in input mode: when read, port dl (pdl) returns the current pin level. when written to, the data written to pdl is written. this has no influence on the input pins. in output mode: when read, port dl (pdl) returns the pdl value. when written to, the value is written to pdl and the written value is immediately output. chapter 4 port functions user ? s manual u15862ej3v0ud 253 (b) port dl mode register (pmdl) this is a 16-bit register that specifies the input mode/output mode. this register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the pmdl register are used as the pmdlh register and as the pmdll register, respectively, these registers can be read/written in 8-bit or 1-bit units. pmdl7 output mode input mode pmdln 0 1 control of i/o mode (n = 0 to 15) pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 after reset: ffffh r/w address: fffff024h (pmdl, pmdll), fffff025h (pmdlh) pmdl15 pmdl (pmdlh note ) pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 8 9 10 11 12 13 14 15 (pmdll) note when reading from or writing to bits 8 to 15 of the pmdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmdlh register. (c) port dl mode control register (pmcdl) this is a 16-bit register that specifies the port mode/control mode. this register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the pmcdl register are used as the pmcdlh register and as the pmcdll register, respectively, these registers can be read/written in 8-bit or 1-bit units. i/o port adn i/o (address/data bus i/o) pmcdln 0 1 specification of pdln pin operation mode (n = 0 to 15) pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 after reset: 0000h r/w address: fffff044h (pmcdl, pmcdll), fffff045h (pmcdlh) pmcdl15 pmcdl (pmcdlh note ) pmcdl14 pmcdl13 pmcdl12 pmcdl11pmcdl10 pmcdl9 pmcdl8 8 9 10 11 12 13 14 15 (pmcdll) note when reading from or writing to bits 8 to 15 of the pmcdl register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the pmcdlh register. caution when specifying the port mode/control mode (alternate function) for each bit, pay careful attention to the operation of the alternate functions. chapter 4 port functions user ? s manual u15862ej3v0ud 254 (3) block diagram (port dl) figure 4-40. block diagram of pdl0 to pdl15 wr pmc rd adn output input enable signal for address/data bus adn input output enable signal for address/data bus wr port pdl0/ad0, pdl1/ad1, pdl2/ad2, pdl3/ad3, pdl4/ad4, pdl5/ad5, pdl6/ad6, pdl7/ad7, pdl8/ad8, pdl9/ad9, pdl10/ad10, pdl11/ad11, pdl12/ad12, pdl13/ad13, pdl14/ad14, pdl15/ad15 pmcdln pmcdl wr pm pmdln pmdl address output buffer off signal output latch (pdln) internal bus selector selector selector selector remarks 1. pmdl: port dl mode register pmcdl: port dl mode control register rd: port dl read signal wr: port dl write signal 2. n = 0 to 15 chapter 4 port functions user ? s manual u15862ej3v0ud 255 other bits (registers) ? ? intr02 (intr0), intf02 (intf0) intr03 (intr0), intf03 (intf0) intr04 (intr0), intf04 (intf0) intr05 (intr0) ,intf05 (intf0) intr06 (intr0), intf06 (intf0) ? ? ? ? ? ? ? ? ? ? pf38 (pf3) = 1 pf39 (pf3) = 1 ? pf41 (pf4) = don ? t care pf42 (pf4) = don ? t care pfcnx bit of pfcn register ? ? ? ? ? ? ? ? ? ? ? ? pfc33 = 0 pfc33 = 1 ? pfc35 = 0 pfc35 = 1 ? ? ? ? ? pmcnx bit of pmcn register pmc00 = 1 pmc01 = 1 pmc02 = 1 pmc03 = 1 pmc04 = 1 pmc05 = 1 pmc06 = 1 ? ? pmc30 = 1 pmc31 = 1 pmc32 = 1 pmc33 = 1 pmc33 = 1 pmc34 = 1 pmc35 = 1 pmc35 = 1 pmc38 = 1 pmc39 = 1 pmc40 = 1 pmc41 = 1 pmc42 = 1 pmnx bit of pmn register pm00 = setting not required pm01 = setting not required pm02 = setting not required pm03 = setting not required pm04 = setting not required pm05 = setting not required pm06 = setting not required pm10 = 1 note 1 pm11 = 1 note 1 pm30 = setting not required pm31 = setting not required pm32 = setting not required pm33 = setting not required pm33 = setting not required pm34 = setting not required pm35 = setting not required pm35 = setting not required pm38 = setting not required pm39 = setting not required pm40 = setting not required pm41 = setting not required pm42 = setting not required pnx bit of pn register p00 = setting not required p01 = setting not required p02 = setting not required p03 = setting not required p04 = setting not required p05 = setting not required p06 = setting not required p10 = setting not required p11 = setting not required p30 = setting not required p31 = setting not required p32 = setting not required p33 = setting not required p33 = setting not required p34 = setting not required p35 = setting not required p35 = setting not required p38 = setting not required p39 = setting not required p40 = setting not required p41 = setting not required p42 = setting not required i/o output output input input input input input output output output input input input output input input output i/o i/o input output i/o alternate function function name toh0 toh1 nmi intp0 intp1 intp2 intp3 ano0 ano1 txd0 rxd0 asck0 ti000 to00 ti001 ti010 to01 sda0 note 2 scl0 note 2 si00 so00 sck00 table 4-28. settings when port pins are used for alternate functions (1/7) pin name p00 p01 p02 p03 p04 p05 p06 p10 p11 p30 p31 p32 p33 p34 p35 p38 p39 p40 p41 p42 notes 1. when setting the ano0 and ano1 pins, set pm1 register = ffh at one time. 2. only for products with an i 2 c bus chapter 4 port functions user ? s manual u15862ej3v0ud 256 other bits (registers) ? ? krm0 (krm) = 1 ? ? krm1 (krm) = 1 ? ? krm2 (krm) = 1 ? ? krm3 (krm) = 1 pf54 (pf5) = don ? t care pf54 (pf5) = 0 pf54 (pf5) = 0, krm4 (krm) = 1 pf55 (pf5) = don ? t care pf55 (pf5) = 0 pf55 (pf5) = 0, krm5 (krm) = 1 pfcnx bit of pfcn register pfc50 = 0 pfc50 = 1 pfc50 = 0 pfc51 = 0 pfc51 = 1 pfc51 = 0 pfc52 = 0 pfc52 = 1 pfc52 = 0 pfc53 = 0 pfc53 = 1 pfc53 = 0 pfc54 = 0 pfc54 = 1 pfc54 = 0 pfc55 = 0 pfc55 = 1 pfc55 = 0 pmcnx bit of pmcn register pmc50 = 1 pmc50 = 1 pmc50 = 0 pmc51 = 1 pmc51 = 1 pmc51 = 0 pmc52 = 1 pmc52 = 1 pmc52 = 0 pmc53 = 1 pmc53 = 1 pmc53 = 0 pmc54 = 1 pmc54 = 1 pmc54 = 0 pmc55 = 1 pmc55 = 1 pmc55 = 0 pmnx bit of pmn register pm50 = setting not required pm50 = setting not required pm50 = 1 pm51 = setting not required pm51 = setting not required pm51 = 1 pm52 = setting not required pm52 = setting not required pm52 = 1 pm53 = setting not required pm53 = setting not required pm53 = 1 pm54 = setting not required pm54 = setting not required pm54 = 1 pm55 = setting not required pm55 = setting not required pm55 = 1 pnx bit of pn register p50 = setting not required p50 = setting not required p50 = setting not required p51 = setting not required p51 = setting not required p51 = setting not required p52 = setting not required p52 = setting not required p52 = setting not required p53 = setting not required p53 = setting not required p53 = setting not required p54 = setting not required p54 = setting not required p54 = setting not required p55 = setting not required p55 = setting not required p55 = setting not required i/o input output input input output input output output input input output input output output input i/o output input alternate function function name ti011 rtp00 kr0 ti50 rtp01 kr1 to50 rtp02 kr2 sia0 rtp03 kr3 soa0 rtp04 kr4 scka0 rtp05 kr5 table 4-28. settings when port pins are used for alternate functions (2/7) pin name p50 p51 p52 p53 p54 p55 chapter 4 port functions user ? s manual u15862ej3v0ud 257 other bits (registers) ? ? ? ? ? ? ? pf67 (pf6) = don ? t care pf68 (pf6) = don ? t care ? ? ? ? ? ? pfcnx bit of pfcn register ? ? ? ? ? ? ? ? ? ? ? ? ? pfc613 = 0 pfc613 = 1 pmcnx bit of pmcn register pmc60 = 1 pmc61 = 1 pmc62 = 1 pmc63 = 1 pmc64 = 1 pmc65 = 1 pmc66 = 1 pmc67 = 1 pmc68 = 1 pmc69 = 1 pmc610 = 1 pmc611 = 1 pmc612 = 1 pmc613 = 1 pmc613 = 1 pmnx bit of pmn register pm60 = setting not required pm61 = setting not required pm62 = setting not required pm63 = setting not required pm64 = setting not required pm65 = setting not required pm66 = setting not required pm67 = setting not required pm68 = setting not required pm69 = setting not required pm610 = setting not required pm611 = setting not required pm612 = setting not required pm613 = setting not required pm613 = setting not required pnx bit of pn register p60 = setting not required p61 = setting not required p62 = setting not required p63 = setting not required p64 = setting not required p65 = setting not required p66 = setting not required p67 = setting not required p68 = setting not required p69 = setting not required p610 = setting not required p611 = setting not required p612 = setting not required p613 = setting not required p613 = setting not required i/o output output output output output output input output i/o input input output input input output alternate function function name rtp10 rtp11 rtp12 rtp13 rtp14 rtp15 si02 so02 sck02 ti040 ti041 to04 ti050 ti051 to05 table 4-28. settings when port pins are used for alternate functions (3/7) pin name p60 p61 p62 p63 p64 p65 p66 p67 p68 p69 p610 p611 p612 p613 chapter 4 port functions user ? s manual u15862ej3v0ud 258 other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pf80 (pf8) = 0 pf80 (pf8) = 1 pf80 (pf8) = 0 pf81 (pf8) = 1 pfcnx bit of pfcn register ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pfc80 = 0 pfc80 = 1 pfc81 = 0 pfc81 = 1 pmcnx bit of pmcn register ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pmc80 = 1 pmc80 = 1 pmc81 = 1 pmc81 = 1 pmnx bit of pmn register ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pm80 = setting not required pm80 = setting not required pm81 = setting not required pm81 = setting not required pnx bit of pn register p70 = setting not required p71 = setting not required p72 = setting not required p73 = setting not required p74 = setting not required p75 = setting not required p76 = setting not required p77 = setting not required p78 = setting not required p79 = setting not required p710 = setting not required p711 = setting not required p712 = setting not required p713 = setting not required p714 = setting not required p715 = setting not required p80 = setting not required p80 = setting not required p81 = setting not required p81 = setting not required i/o input input input input input input input input input input input input input input input input input i/o output i/o alternate function function name ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 ani12 ani13 ani14 ani15 rxd2 sda1 note 1 txd2 scl1 note 1 table 4-28. settings when port pins are used for alternate functions (4/7) pin name p70 p71 p72 p73 p74 p75 p76 p77 p78 p79 p710 p711 p712 p713 p714 p715 p80 p81 note only for the pd703216y, 703217y, and 70f3217y chapter 4 port functions user ? s manual u15862ej3v0ud 259 other bits (registers) note ? krm6 (krm) = 1 note ? krm7 (krm) = 1 note ? ? note ? note ? ? note ? note ? ? note note , pf98 (pf9) = 0 pf98 (pf9) = don ? t care note , pf98 (pf9) = 0 pf98 (pf9) = don ? t care pfcnx bit of pfcn register pfc90 = 0 pfc90 = 1 pfc90 = 0 pfc91 = 0 pfc91 = 1 pfc91 = 0 pfc92 = 0 pfc92 = 0 pfc92 = 1 pfc93 = 0 pfc93 = 1 pfc94 = 0 pfc94 = 0 pfc94 = 1 pfc95 = 0 pfc95 = 1 pfc96 = 0 pfc96 = 0 pfc96 = 1 pfc97 = 0 pfc97 = 1 pfc98 = 0 pfc98 = 1 pfc99 = 0 pfc99 = 1 pmcnx bit of pmcn register pmc90 = 1 pmc90 = 1 pmc90 = 0 pmc91 = 1 pmc91 = 1 pmc91 = 0 pmc92 = 1 pmc92 = 0 pmc92 = 1 pmc93 = 1 pmc93 = 1 pmc94 = 1 pmc94 = 0 pmc94 = 1 pmc95 = 1 pmc95 = 1 pmc96 = 1 pmc96 = 0 pmc96 = 1 pmc97 = 1 pmc97 = 1 pmc98 = 1 pmc98 = 1 pmc99 = 1 pmc99 = 1 pmnx bit of pmn register pm90 = setting not required pm90 = setting not required pm90 = 1 pm91 = setting not required pm91 = setting not required pm91 = 1 pm92 = setting not required pm92 = setting not required pm92 = setting not required pm93 = setting not required pm93 = setting not required pm94 = setting not required pm94 = 1 pm94 = setting not required pm95 = setting not required pm95 = setting not required pm96 = setting not required pm96 = 1 pm96 = setting not required pm97 = setting not required pm97 = setting not required pm98 = setting not required pm98 = setting not required pm99 = setting not required pm99 = setting not required pnx bit of pn register p90 = setting not required p90 = setting not required p90 = setting not required p91 = setting not required p91 = setting not required p91 = setting not required p92 = setting not required p92 = setting not required p92 = setting not required p93 = setting not required p93 = setting not required p94 = setting not required p94 = setting not required p94 = setting not required p95 = setting not required p95 = setting not required p96 = setting not required p96 = setting not required p96 = setting not required p97 = setting not required p97 = setting not required p98 = setting not required p98 = setting not required p99 = setting not required p99 = setting not required i/o output output input output input input output input output output input output input output output input output input output output input output output output i/o alternate function function name a0 txd1 kr6 a1 rxd1 kr7 a2 ti020 to02 a3 ti021 a4 ti030 to03 a5 ti031 a6 ti51 to51 a7 si01 a8 so01 a9 sck01 table 4-28. settings when port pins are used for alternate functions (5/7) pin name p90 p91 p92 p93 p94 p95 p96 p97 p98 p99 note when setting the a0 to a15 pins, perform 16-bit setting of pfc9 register = 0000h and pmc9 register = ffffh at one time. chapter 4 port functions user ? s manual u15862ej3v0ud 260 other bits (registers) note ? note , pf911 (pf9) = 0 pf911 (pf9) = don ? t care note , pf912 (pf9) = 0 pf912 (pf9) = don ? t care note intr913 (intr9), intf913 (intf9) note intr914 (intr9), intf914 (intf9) note intr915 (intr9), intf915 (intf9) ? ? ? ? ? ? ? ? ? ? ? ? pfcnx bit of pfcn register pfc910 = 0 pfc910 = 1 pfc911 = 0 pfc911 = 1 pfc912 = 0 pfc912 = 1 pfc913 = 0 pfc913 = 1 pfc914 = 0 pfc914 = 1 pfc915 = 0 pfc915 = 1 ? ? ? ? ? ? ? ? ? ? ? ? pmcnx bit of pmcn register pmc910 = 1 pmc910 = 1 pmc911 = 1 pmc911 = 1 pmc912 = 1 pmc912 = 1 pmc913 = 1 pmc913 = 1 pmc914 = 1 pmc914 = 1 pmc915 = 1 pmc915 = 1 pmccm0 = 1 pmccm1 = 1 pmccm2 = 1 pmccm3 = 1 pmccs0 = 1 pmccs1 = 1 pmccs2 = 1 pmccs3 = 1 pmcct0 = 1 pmcct1 = 1 pmcct4 = 1 pmcct6 = 1 pmnx bit of pmn register pm910 = setting not required pm910 = setting not required pm911 = setting not required pm911 = setting not required pm912 = setting not required pm912 = setting not required pm913 = setting not required pm913 = setting not required pm914 = setting not required pm914 = setting not required pm915 = setting not required pm915 = setting not required pmcm0 = setting not required pmcm1 = setting not required pmcm2 = setting not required pmcm3 = setting not required pmcs0 = setting not required pmcs1 = setting not required pmcs2 = setting not required pmcs3 = setting not required pmct0 = setting not required pmct1 = setting not required pmct4 = setting not required pmct6 = setting not required pnx bit of pn register p910 = setting not required p910 = setting not required p911 = setting not required p911 = setting not required p912 = setting not required p912 = setting not required p913 = setting not required p913 = setting not required p914 = setting not required p914 = setting not required p915 = setting not required p915 = setting not required pcm0 = setting not required pcm1 = setting not required pcm2 = setting not required pcm3 = setting not required pcs0 = setting not required pcs1 = setting not required pcs2 = setting not required pcs3 = setting not required pct0 = setting not required pct1 = setting not required pct4 = setting not required pct6 = setting not required i/o output input output output output i/o output input output input output input input output output input output output output output output output output output alternate function function name a10 sia1 a11 soa1 a12 scka1 a13 intp4 a14 intp5 a15 intp6 wait clkout hldak hldqr cs0 cs1 cs2 cs3 wr0 wr1 rd astb table 4-28. settings when port pins are used for alternate functions (6/7) pin name p910 p911 p912 p913 p914 p915 pcm0 pcm1 pcm2 pcm3 pcs0 pcs1 pcs2 pcs3 pct0 pct1 pct4 pct6 note when setting the a0 to a15 pins, perform 16-bit setting of pfc9 register = 0000h and pmc9 register = ffffh at one time. chapter 4 port functions user ? s manual u15862ej3v0ud 261 other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pfcnx bit of pfcn register ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pmcnx bit of pmcn register pmcdh0 = 1 pmcdh1 = 1 pmcdh2 = 1 pmcdh3 = 1 pmcdh4 = 1 pmcdh5 = 1 pmcdh6 = 1 pmcdh7 = 1 pmcdl0 = 1 pmcdl1 = 1 pmcdl2 = 1 pmcdl3 = 1 pmcdl4 = 1 pmcdl5 = 1 pmcdl6 = 1 pmcdl7 = 1 pmcdl8 = 1 pmcdl9 = 1 pmcdl10 = 1 pmcdl11 = 1 pmcdl12 = 1 pmcdl13 = 1 pmcdl14 = 1 pmcdl15 = 1 pmnx bit of pmn register pmdh0 = setting not required pmdh1 = setting not required pmdh2 = setting not required pmdh3 = setting not required pmdh4 = setting not required pmdh5 = setting not required pmdh6 = setting not required pmdh7 = setting not required pmdl0 = setting not required pmdl1 = setting not required pmdl2 = setting not required pmdl3 = setting not required pmdl4 = setting not required pmdl5 = setting not required pmdl6 = setting not required pmdl7 = setting not required pmdl8 = setting not required pmdl9 = setting not required pmdl10 = setting not required pmdl11 = setting not required pmdl12 = setting not required pmdl13 = setting not required pmdl14 = setting not required pmdl15 = setting not required pnx bit of pn register pdh0 = setting not required pdh1 = setting not required pdh2 = setting not required pdh3 = setting not required pdh4 = setting not required pdh5 = setting not required pdh6 = setting not required pdh7 = setting not required pdl0 = setting not required pdl1 = setting not required pdl2 = setting not required pdl3 = setting not required pdl4 = setting not required pdl5 = setting not required pdl6 = setting not required pdl7 = setting not required pdl8 = setting not required pdl9 = setting not required pdl10 = setting not required pdl11 = setting not required pdl12 = setting not required pdl13 = setting not required pdl14 = setting not required pdl15 = setting not required i/o output output output output output output output output i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o alternate function function name a16 a17 a18 a19 a20 a21 a22 a23 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 table 4-28. settings when port pins are used for alternate functions (7/7) pin name pdh0 pdh1 pdh2 pdh3 pdh4 pdh5 pdh6 pdh7 pdl0 pdl1 pdl2 pdl3 pdl4 pdl5 pdl6 pdl7 pdl8 pdl9 pdl10 pdl11 pdl12 pdl13 pdl14 pdl15 chapter 4 port functions user ? s manual u15862ej3v0ud 262 4.4 port function operation port operation differs according to the input/output mode setting, as follows. 4.4.1 write operation to i/o port (1) in output mode a value is written to the output latch using the transfer instruction, and the contents of the output latch are output from the pin. data that has been written once to the output latch is held until the next data is written to the output latch. (2) in input mode a value is written to the output latch using the transfer instruction. however, since the output buffer is off, the pin status does not change. data that has been written once to the output latch is held until the next data is written to the output latch. caution in the case of 1-bit memory manipulation instructions, the manipulation target is just one bit, but the port is accessed in 8-bit units. therefore, in the case of ports for which a mixture of input/output is used, the output latch contents of pins specified as input other than the target bit also become undefined. 4.4.2 read operation from i/o port (1) in output mode the output latch contents are read using the transfer instruction. the output latch contents remain unchanged. (2) in input mode the pin status is read using the transfer instruction. the output latch contents remain unchanged. 4.4.3 arithmetic operation with i/o ports (1) in output mode an arithmetic operation on the output latch contents is performed, the result is written to the output latch, and the output latch contents are output from the pin. data that has been written once to the output latch is held until the next data is written to the output latch. (2) in input mode the output latch contents become undefined. however, since the output buffer is off, the pin status does not change. caution in the case of 1-bit memory manipulation instructions, the manipulation target is just one bit, but the port is accessed in 8-bit units. therefore, in the case of ports for which input/output is used in mix, the output latch contents of pins specified for input other than the target bit also become undefined. user?s manual u15862ej3v0ud 263 chapter 5 bus control function the v850es/kf1, v850es/kg1, and v850es/kj1 are provided with an external bus interface function by which external memories such as rom and ram, and i/o can be connected. 5.1 features { output is selectable from a multiplex bus with a minimum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles (separate bus output is only available in the v850es/kg1 and v850es/kj1) { chip select function for up to 4 spaces (v850es/kf1, v850es/kg1: 2 spaces, v850es/kj1: 4 spaces) { 8-bit/16-bit data bus selectable (for each area selected by chip select function) { wait function ? programmable wait function of up to 7 states (selectable for each area selected by chip select function) ? external wait function using wait pin { idle state function { bus hold function { the bus can be controlled using a different voltage from the operating voltage by setting bv dd v dd = ev dd (however, only in multiplex bus mode). 5.2 bus control pins the pins used to connect an external device are listed in the table below. (1) multiplex bus mode table 5-1. v850es/kf1 bus control pins bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o address/data bus wait pcm0 input external wait control clkout pcm1 output internal system clock output cs0, cs1 pcs0, pcs1 output chip select wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal astb pct6 output address strobe signal hldrq pcm3 input hldak pcm2 output bus hold control chapter 5 bus control function user?s manual u15862ej3v0ud 264 table 5-2. v850es/kg1 bus control pins bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o address/data bus a16 to a21 pdh0 to pdh5 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock output cs0, cs1 pcs0 to pcs1 output chip select wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal astb pct6 output address strobe signal hldrq pcm3 input hldak pcm2 output bus hold control table 5-3. v850es/kj1 bus control pins bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o address/data bus a16 to a23 pdh0 to pdh7 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock output cs0 to cs3 pcs0 to pcs3 output chip select wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal astb pct6 output address strobe signal hldrq pcm3 input hldak pcm2 output bus hold control (2) separate bus mode note that the separate bus mode is not available in the v850es/kf1. table 5-4. v850es/kg1 bus control pins bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o data bus a0 to a15 p90 to p915 output address bus a16 to a21 pdh0 to pdh5 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock output cs0, cs1 pcs0, pcs1 output chip select wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal hldrq pcm3 input hldak pcm2 output bus hold control chapter 5 bus control function user?s manual u15862ej3v0ud 265 table 5-5. v850es/kj1 bus control pins bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o data bus a0 to a15 p90 to p915 output address bus a16 to a23 pdh0 to pdh7 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock output cs0 to cs3 pcs0 to pcs3 output chip select wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal hldrq pcm3 input hldak pcm2 output bus hold control 5.2.1 pin status when internal rom, internal ram, or on-chip peripheral i/o is accessed table 5-6. pin status when internal rom, internal ram, or on-chip peripheral i/o is accessed access destination address bus data bus control signal internal rom undefined hi-z inactive internal ram undefined hi-z inactive on-chip peripheral i/o note hi-z inactive note when an on-chip peripheral i/o is accessed, the address bus outputs the address of the on-chip peripheral i/o that is accessed. 5.2.2 pin status in each operation mode for the pin status of the v850es/kf1, v850es/kg1, and v850es/kj1 in each operation mode, refer to 2.2 pin status . chapter 5 bus control function user?s manual u15862ej3v0ud 266 5.3 memory block function (1) v850es/kf1 the 64 mb memory space is divided into memory blocks of (lower) 2 mb and 64 kb. the programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units. figure 5-1. data memory map (v850es/kf1) 3ffffffh 3fec000h 3febfffh 0210000h 020ffffh 0200000h 01fffffh 0000000h 01fffffh 0100000h 00fffffh 0110000h 010ffffh 3ffd800h 3ffd7ffh 3fff000h 3ffefffh 3ffffffh 0000000h 3fec000h (80 kb) access-prohibited area internal rom area note 2 (1 mb) external memory area (64 kb) internal ram area note 1 (6 kb) on-chip peripheral i/o area (4 kb) access-prohibited area access-prohibited area external memory area (64 kb) (2 mb) cs0 cs1 notes 1. this area is the 4 kb space of 3ffe000h to 3ffefffh in the pd703208, 703208y, 703209, and 703209y. 2. this area is an external memory area in the case of a data write access. caution a write access to addresses 0000000h to 000ffffh is the same operations as a write access to addresses 0100000h to 010ffffh. chapter 5 bus control function user ? s manual u15862ej3v0ud 267 (2) v850es/kg1 the 64 mb memory space is divided into memory blocks of (lower) 2 mb and 2 mb. the programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units. figure 5-2. data memory map (v850es/kg1) 3ffffffh 3fec000h 3febfffh 0400000h 03fffffh 0200000h 01fffffh 0000000h 01fffffh 0100000h 00fffffh 3ffd800h 3ffd7ffh 3fff000h 3ffefffh 3ffffffh 0000000h 3fec000h (80 kb) access-prohibited area internal rom area note 2 (1 mb) external memory area (1 mb) internal ram area note 1 (6 kb) on-chip peripheral i/o area (4 kb) access-prohibited area external memory area (2 mb) (2 mb) cs0 cs1 notes 1. this area is the 4 kb space of 3ffe000h to 3ffefffh in the pd703212, 703212y, 703213, and 703213y. 2. this area is an external memory area in the case of a data write access. chapter 5 bus control function user ? s manual u15862ej3v0ud 268 (3) v850es/kj1 the 64 mb memory space is divided into memory blocks of (lower) 2 mb, 2 mb, 4 mb, and 8 mb. the programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units. figure 5-3. data memory map (v850es/kj1) 3ffffffh 3fec000h 3febfffh 1000000h 0ffffffh 0800000h 07fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h 01fffffh 0100000h 00fffffh 3ffd800h 3ffd7ffh 3fff000h 3ffefffh 3ffffffh 0000000h 3fec000h (80 kb) access-prohibited area external memory area (8 mb) internal rom area note (1 mb) external memory area (1 mb) internal ram area (6 kb) on-chip peripheral i/o area (4 kb) access-prohibited area external memory area (4 mb) external memory area (2 mb) (2 mb) cs0 cs1 cs2 cs3 note this area is an external memory area in the case of a data write access. chapter 5 bus control function user ? s manual u15862ej3v0ud 269 5.3.1 chip select control function of the 64 mb (linear) address space, the lower 16 mb (0000000h to 0ffffffh) include four chip select control functions, cs0 to cs3. the areas that can be selected by cs0 to cs3 are fixed. by using these chip select control functions, the memory block can be divided to enable effective use of the memory space. the allocation of the memory blocks is shown in the table below. v850es/kf1 v850es/kg1 v850es/kj1 cs0 0000000h to 010ffffh (1088 kb) 0000000h to 01fffffh (2 mb) 0000000h to 01fffffh (2 mb) cs1 0200000h to 020ffffh (64 kb) 0200000h to 03fffffh (2 mb) 0200000h to 03fffffh (2 mb) cs2 ?? 0400000h to 07fffffh (4 mb) cs3 ?? 0800000h to 0ffffffh (8 mb) 5.4 external bus interface mode control function the v850es/kg1 and v850es/kj1 include the following two external bus interface modes. ? multiplex bus mode ? separate bus mode these two modes can be selected by using the external bus interface mode control register (eximc). remark only the multiplex bus mode is available in the v850es/kf1. (1) external bus interface mode control register (eximc) this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution the eximc register is only available in the v850es/kg1 and v850es/kj1. 0 multiplex bus mode separate bus mode smsel 0 1 mode selection eximc 0 0 0 0 0 0 smsel after reset: 00h r/w address: ffffffbeh chapter 5 bus control function user ? s manual u15862ej3v0ud 270 5.5 bus access 5.5.1 number of clocks for access the following table shows the number of basic clocks required for accessing each resource. area (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) external memory (16 bits) instruction fetch (normal access) 1 1 or 2 3 + n note instruction fetch (branch) 2 1 or 2 3+ n note operand data access 3 1 3 +n note note 2 + n clocks (n: number of wait states) when the separate bus mode is selected (v850es/kg1 and v850es/kj1). remark unit: clocks/access 5.5.2 bus size setting function the bus size of each external memory area selected by csn can be set (to 8 bits or 16 bits) by using the bsc register. the external memory area of the v850es/kj1 (0100000h to 0ffffffh) is selected by cs0 to cs3. the external memory area of the v850es/kg1 (0100000h to 03fffffh) is selected by cs0 and cs1. the external memory area of the v850es/kf1 (0100000h to 010ffffh and 0200000h to 020ffffh) is selected by cs0 and cs1. (1) bus size configuration register (bsc) this register can be read or written in 16-bit units. caution write to the bsc register after reset, and then do not change the set values. also, do not access an external memory area other than the one for this initialization routine until the initial settings of the bsc register are complete. however, external memory areas whose initial settings are complete may be accessed. after reset: 5555h r/w address: fffff066h 0 0 bsn0 0 1 8 bits 16 bits bsc 1 bs30 note 0 0 1 bs20 note 0 0 1 bs10 0 0 1 bs00 8 9 10 11 12 13 data bus width of csn space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 cs0 cs3 csn signal cs2 cs1 note the bs30 and bs20 bits are only valid in the v850es/kj1. changing these bits has no effect on the operation in the v850es/kf1 and v850es/kg1. caution be sure to set bits 14, 12, 10, and 8 to 1, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0. chapter 5 bus control function user ? s manual u15862ej3v0ud 271 5.5.3 access by bus size the v850es/kf1, v850es/kg1, and v850es/kj1 access the on-chip peripheral i/o and external memory in 8-bit, 16-bit, or 32-bit units. the bus size is as follows. ? the bus size of the on-chip peripheral i/o is fixed to 16 bits. ? the bus size of the external memory is selectable from 8 bits or 16 bits (by using the bsc register). the operation when each of the above is accessed is described below. all data is accessed starting from the lower side. the v850es/kf1, v850es/kg1, and v850es/kj1 support only the little endian format. figure 5-4. little endian address in word 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 (1) byte access (8 bits) (a) 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 15 8 2n + 1 address byte data external data bus (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 2n address byte data external data bus 7 0 7 0 2n + 1 address byte data external data bus chapter 5 bus control function user ? s manual u15862ej3v0ud 272 (2) halfword access (16 bits) (a) with 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access 7 0 7 0 15 8 2n address 15 8 2n + 1 halfword data external data bus 7 0 7 0 15 8 15 8 7 0 7 0 15 8 15 8 2n + 2 2n address address 2n + 1 halfword data external data bus halfword data external data bus (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access first access second access 7 0 7 0 15 8 address 7 0 7 0 15 8 2n + 1 address 2n halfword data external data bus halfword data external data bus 7 0 7 0 15 8 7 0 7 0 15 8 2n + 2 2n + 1 address address halfword data external data bus halfword data external data bus chapter 5 bus control function user ? s manual u15862ej3v0ud 273 (3) word access (32 bits) (a) 16-bit data bus width (1/2) <1> access to address (4n) first access second access 7 0 7 0 15 8 4n 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access 7 0 7 0 15 8 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 23 16 31 24 address address address word data external data bus word data external data bus word data external data bus chapter 5 bus control function user ? s manual u15862ej3v0ud 274 (a) 16-bit data bus width (2/2) <3> access to address (4n + 2) first access second access 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 address address word data external data bus word data external data bus <4> access to address (4n + 3) first access second access third access 7 0 7 0 15 8 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 7 0 7 0 15 8 4n + 6 15 8 23 16 31 24 address address address word data external data bus word data external data bus word data external data bus chapter 5 bus control function user ? s manual u15862ej3v0ud 275 (b) 8-bit data bus width (1/2) <1> access to address (4n) first access second access third access fourth access 7 0 7 0 15 8 4n 23 16 31 24 7 0 7 0 4n + 1 15 8 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 word data external data bus address address address address word data external data bus word data external data bus word data external data bus <2> access to address (4n + 1) first access second access third access fourth access 7 0 7 0 15 8 4n + 1 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 address address address address word data external data bus word data external data bus word data external data bus word data external data bus chapter 5 bus control function user ? s manual u15862ej3v0ud 276 (b) 8-bit data bus width (2/2) <3> access to address (4n + 2) first access second access third access fourth access address address address address 7 0 7 0 15 8 4n + 2 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 word data external data bus word data external data bus word data external data bus word data external data bus <4> access to address (4n + 3) first access second access third access fourth access 7 0 7 0 15 8 4n + 3 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 7 0 7 0 4n + 6 15 8 23 16 31 24 address address address address word data external data bus word data external data bus word data external data bus word data external data bus chapter 5 bus control function user ? s manual u15862ej3v0ud 277 5.6 wait function 5.6.1 programmable wait function (1) data wait control register 0 (dwc0) to realize interfacing with a low-speed memory or i/o, up to seven data wait states can be inserted in the bus cycle that is executed for each cs space. the number of wait states can be programmed by using data wait control register 0 (dwc0). immediately after system reset, 7 data wait states are inserted for all the blocks. the dwc0 register can be read or written in 16-bit units. cautions 1. the internal rom and internal ram areas are not subject to programmable wait, and are always accessed without a wait state. the on-chip peripheral i/o area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. write to the dwc0 register after reset, and then do not change the set values. also, do not access an external memory area other than the one for this initialization routine until the initial settings of the dwc0 register are complete. however, external memory areas whose initial settings are complete may be accessed. after reset: 7777h r/w address: fffff484h 0 0 dwn2 0 0 0 0 1 1 1 1 dwn1 0 0 1 1 0 0 1 1 dwn0 0 1 0 1 0 1 0 1 none 1 2 3 4 5 6 7 dwc0 dw32 note dw12 dw31 note dw11 dw30 note dw10 0 0 dw22 note dw02 dw21 note dw01 dw20 note dw00 8 9 10 11 12 13 number of wait states inserted in csn space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 cs0 cs3 csn signal csn signal cs2 cs1 note the dw32 to dw30 and dw22 to dw20 bits are only valid in the v850es/kj1. changing these bits has no effect on the operation in the v850es/kf1 and v850es/kg1. caution be sure to clear bits 15, 11, 7, and 3 to 0. chapter 5 bus control function user ? s manual u15862ej3v0ud 278 5.6.2 external wait function to synchronize an extremely slow external device, i/o, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (wait). access to each area of the internal rom, internal ram, and on-chip peripheral i/o is not subject to control by the external wait function, in the same manner as the programmable wait function. the wait signal can be input asynchronously to clkout, and is sampled at the falling edge of the clock in the t2 and tw states of the bus cycle in the multiplex bus mode. in the separate bus mode, it is sampled at the rising edge of the clock immediately after the t1 and tw states of the bus cycle. if the setup/hold time of the sampling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all. chapter 5 bus control function user ? s manual u15862ej3v0ud 279 5.6.3 relationship between programmable wait and external wait wait cycles are inserted as the result of an or operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the wait pin. the number of wait cycles is determined by the side with the greatest number of cycles. wait control programmable wait wait via wait pin for example, if the timing of the programmable wait and the wait pin signal is as illustrated below, three wait states will be inserted in the bus cycle. figure 5-5. example of inserting wait states (a) in separate bus mode t1 tw tw tw t2 clkout wait pin wait via wait pin programmable wait wait control remark the circles indicate the sampling timing. (b) in multiplex bus mode clkout t1 t2 tw tw tw t3 wait pin wait by wait pin programmable wait wait control remark { : valid sampling timing chapter 5 bus control function user ? s manual u15862ej3v0ud 280 5.6.4 programmable address wait function address-setup or address-hold waits to be inserted in each bus cycle can be set by using the address wait control register (awc). address wait insertion is set for each chip select area (cs0 to cs3). if an address setup wait is inserted, it seems that the high-clock period of t1 state is extended by 1 clock. if an address hold wait is inserted, it seems that the low-clock period of t1 state is extended by 1 clock. (1) address wait control register (awc) this register can be read or written in 16-bit units. after reset: ffffh r/w address: fffff488h 1 ahw3 note ahwn 0 1 not inserted inserted awc 1 asw3 note 1 ahw2 note 1 asw2 note 1 ahw1 1 asw1 1 ahw0 1 asw0 8 9 10 11 12 13 specifies insertion of address hold wait (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 aswn 0 1 not inserted inserted specifies insertion of address setup wait (n = 0 to 3) cs0 cs3 csn signal cs2 cs1 note the ahw3, ahw2, asw3, and asw2 bits are only valid in the v850es/kj1. changing these bits has no effect on the operation in the v850es/kf1 and v850es/kg1. caution be sure to set bits 15 to 8 to 1. chapter 5 bus control function user ? s manual u15862ej3v0ud 281 5.7 idle state insertion function to facilitate interfacing with low-speed memories, one idle state (ti) can be inserted after the t3 state in the bus cycle that is executed for each space selected by the chip select function in the multiplex address/data bus mode. in the separate bus mode, one idle state (ti) can be inserted after the t2 state. by inserting idle states, the data output float delay time of the memory can be secured during read access (an idle state cannot be inserted during write access). whether the idle state is to be inserted can be programmed by using the bus cycle control register (bcc). an idle state is inserted for all the areas immediately after system reset. (1) bus cycle control register (bcc) this register can be read or written in 16-bit units. cautions 1. the internal rom, internal ram, and on-chip peripheral i/o areas are not subject to idle state insertion. 2. write to the bcc register after reset, and then do not change the set values. also, do not access an external memory area other than the one for this initialization routine until the initial settings of the bcc register are complete. however, external memory areas whose initial settings are complete may be accessed. after reset: aaaah r/w address: fffff48ah 1 bc31 note bcn1 0 1 not inserted inserted bcc 0 0 1 bc21 note 0 0 1 bc11 0 0 1 bc01 0 0 8 9 10 11 12 13 specifies insertion of idle state (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 cs0 cs3 csn signal cs2 cs1 note the bc31 and bc21 bits are only valid in the v850es/kj1. changing these bits has no effect on the operation in the v850es/kf1 and v850es/kg1. caution be sure to set bits 15, 13, 11, and 9 to 1, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to 0. chapter 5 bus control function user ? s manual u15862ej3v0ud 282 5.8 bus hold function 5.8.1 functional outline the hldak and hldrq functions are valid if the pcm2 and pcm3 pins are set in the control mode. when the hldrq pin is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status). if the request for the bus mastership is cleared and the hldrq pin is deasserted (high level), driving these pins is started again. during the bus hold period, execution of the program in the internal rom and internal ram is continued until a peripheral i/o register or the external memory is accessed. the bus hold status is indicated by assertion (low level) of the hldak pin. the bus hold function enables the configuration of multi-processor type systems in which two or more bus masters exist. note that the bus hold request is not acknowledged during a multiple-access cycle initiated by the bus sizing function or a bit manipulation instruction. status data bus width access type timing in which bus hold request not acknowledged word access to even address between first and second access between first and second access word access to odd address between second and third access 16 bits halfword access to odd address between first and second access between first and second access between second and third access word access between third and fourth access cpu bus lock 8 bits halfword access between first and second access read-modify-write access of bit manipulation instruction ?? between read access and write access chapter 5 bus control function user ? s manual u15862ej3v0ud 283 5.8.2 bus hold procedure the bus hold status transition procedure is shown below. <1> hldrq = 0 acknowledged <2> all bus cycle start requests inhibited <3> end of current bus cycle <4> shift to bus idle status. <5> hldak = 0 <6> hldrq = 1 acknowledged <7> hldak = 1 <8> bus cycle start request inhibition released <9> bus cycle starts normal status bus hold status normal status hldak (output) hldrq (input) <1> <2> <3><4> <5> <6> <7><8><9> 5.8.3 operation in power save mode because the internal system clock is stopped in the stop and idle modes, the bus hold status is not entered even if the hldrq pin is asserted. in the halt mode, the hldak pin is asserted as soon as the hldrq pin has been asserted, and the bus hold status is entered. when the hldrq pin is later deasserted, the hldak pin is also deasserted, and the bus hold status is cleared. chapter 5 bus control function user ? s manual u15862ej3v0ud 284 5.9 bus priority bus hold, instruction fetch (branch), instruction fetch (successive), and operand data accesses are executed in the external bus cycle. bus hold has the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (successive). an instruction fetch may be inserted between the read access and write access in a read-modify-write access. if an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between accesses due to bus size limitations. table 5-7. bus priority priority external bus cycle bus master high bus hold external device operand data access cpu instruction fetch (branch) cpu low instruction fetch (successive) cpu 5.10 boundary operation conditions 5.10.1 program space (1) if a branch instruction exists at the upper limit of the internal ram area, a prefetch operation straddling over the on-chip peripheral i/o area (invalid fetch) does not occur. (2) instruction execution to the external memory area cannot be continued without a branch from the internal rom area to the external memory area. 5.10.2 data space the v850es/kf1, v850es/kg1, and v850es/kj1 have an address misalign function. with this function, data can be placed at all addresses, regardless of the format of the data (word data or halfword data). however, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least twice, causing the bus efficiency to drop. (1) halfword-length data access a byte-length bus cycle is generated twice if the least significant bit of the address is 1. (2) word-length data access (a) a byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if the least significant bit of the address is 1. (b) a halfword-length bus cycle is generated twice if the lower 2 bits of the address are 10. chapter 5 bus control function user ? s manual u15862ej3v0ud 285 5.11 bus timing figure 5-6. multiplex bus read timing (bus size: 16 bits, 16-bit access) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout a23 to a16 astb cs3 to cs0 wait ad15 to ad0 rd 8-bit access ad15 to ad8 ad7 to ad0 odd address active ? even address ? active remark the broken lines indicate high impedance. figure 5-7. multiplex bus read timing (bus size: 8 bits) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout a23 to a16, ad15 to ad8 astb cs3 to cs0 wait ad7 to ad0 rd remark the broken lines indicate high impedance. chapter 5 bus control function user ? s manual u15862ej3v0ud 286 figure 5-8. multiplex bus write timing (bus size: 16 bits, 16-bit access) a1 11 00 11 11 00 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout a23 to a16 astb cs3 to cs0 wait ad15 to ad0 wr1, wr0 wr1, wr0 01 10 8-bit access ad15 to ad8 ad7 to ad0 odd address active undefined even address undefined active figure 5-9. multiplex bus write timing (bus size: 8 bits) a1 11 10 11 11 10 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout a23 to a16, ad15 to ad8 astb cs3 to cs0 wait ad7 to ad0 wr1, wr0 chapter 5 bus control function user ? s manual u15862ej3v0ud 287 figure 5-10. multiplex bus hold timing (bus size: 16 bits, 16-bit access) t1 a1 undefined a1 a2 t2 t3 ti note th th th th ti note t1 t2 t3 d1 clkout hldrq hldak a23 to a16 astb cs3 to cs0 ad15 to ad0 rd undefined undefined undefined a2 d2 1111 1111 note this idle state (ti) does not depend on the bcc register settings. remarks 1. refer to tables 2-2 to 2-4 for the pin statuses in the bus hold mode. 2. the broken lines indicate high impedance. chapter 5 bus control function user ? s manual u15862ej3v0ud 288 figure 5-11. separate bus read timing (bus size: 16 bits, 16-bit access) t1 a1 a2 a3 t2 t1 tw tw t2 t2 ti t1 d3 d2 programmable wait external wait idle state d1 clkout a23 to a0 cs3 to cs0 wait ad15 to ad0 rd 8-bit access ad15 to ad8 ad7 to ad0 odd address active ? even address ? active remark the broken lines indicate high impedance. figure 5-12. separate bus read timing (bus size: 8 bits) t1 a1 a2 a3 t2 t1 tw tw t2 t2 ti t1 d3 d2 programmable wait external wait idle state d1 clkout a23 to a0 cs3 to cs0 wait ad7 to ad0 rd remark the broken lines indicate high impedance. chapter 5 bus control function user ? s manual u15862ej3v0ud 289 figure 5-13. separate bus write timing (bus size: 16 bits, 16-bit access) t1 a1 11 00 00 00 11 11 11 11 a2 a3 t2 t1 tw tw t2 t1 t2 d3 d2 programmable wait external wait d1 clkout a23 to a0 cs3 to cs0 wait ad15 to ad0 wr1, wr0 wr1, wr0 01 10 8-bit access ad15 to ad8 ad7 to ad0 odd address active undefined even address undefined active remark the broken lines indicate high impedance. figure 5-14. separate bus write timing (bus size: 8 bits) t1 a1 a2 a3 t2 t1 tw tw t2 t1 t2 d3 d2 programmable wait external wait d1 clkout a23 to a0 cs3 to cs0 wait ad7 to ad0 wr1, wr0 11 10 10 10 11 11 11 11 remark the broken lines indicate high impedance. chapter 5 bus control function user ? s manual u15862ej3v0ud 290 figure 5-15. separate bus hold timing (bus size: 8 bits, write) clkout t1 t2 a1 d1 d2 undefined a2 undefined 11 11 10 d3 a3 t1 t2 th ti ? ti ? th th th t1 t2 hldrq hldak a23 to a0 ad7 to ad0 wr1, wr0 cs3 to cs0 11 10 11 10 1111 1111 11 note this idle state (ti) does not depend on the bcc register settings. remark the broken lines indicate high impedance. figure 5-16. address wait timing (separate bus read, bus size: 16 bits, 16-bit access) tasw t1 tahw t2 clkout astb a23 to a0 cs3 to cs0 wait ad15 to ad0 rd d1 a1 t1 t2 clkout astb a23 to a0 cs3 to cs0 wait ad15 to ad0 rd d1 a1 remarks 1. tasw (address setup wait): image of high-level width of t1 state expanded. 2. tahw (address hold wait): image of low-level width of t1 state expanded. 3. the broken lines indicate high impedance. chapter 5 bus control function user ? s manual u15862ej3v0ud 291 5.12 cautions with the external bus function, signals may not be output at the correct timing under the following conditions. user?s manual u15862ej3v0ud 292 chapter 6 clock generation function 6.1 overview the following clock generation functions are available. { main clock oscillator ? f x = 2 to 2.5 mhz (regc = v dd = 2.7 to 5.5 v, in pll mode) ? f x = 2 to 5 mhz (regc = v dd = 4.5 to 5.5 v, in pll mode) ? f x = 2 to 4 mhz (regc = capacitor, v dd = 4.0 to 5.5 v, in pll mode) ? f x = 2 to 10 mhz (regc = v dd = 2.7 to 5.5 v, in clock-through mode) { subclock oscillator ? 32.768 khz { multiply ( 4) function by pll (phase locked loop) ? clock-through mode/pll mode selectable ? usable voltage: v dd = 2.7 to 5.5 v { internal system clock generation ? 7 steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) { peripheral clock generation { clock output function chapter 6 clock generation function user?s manual u15862ej3v0ud 293 6.2 configuration figure 6-1. clock generator frc bit mfrc bit ck2 to ck0 bits selpll bit pllon bit cls bit, ck3 bit stop mode subclock oscillator port cm prescaler 1 prescaler 2 idle control halt control halt mode cpu clock watch timer clock watch timer clock, watchdog timer clock peripheral clock, watchdog timer 2 clock watchdog timer 1 clock internal system clock prescaler 3 main clock oscillator main clock oscillator stop control xt1 xt2 clkout x1 x2 idle mode idle control idle mode selector pll f xx /32 f xx /16 f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xx to f xx /1024 f brg = f x /2 to f x /2 12 f xt f xt f xx f x f xw idle control idle mode selector selector (1) main clock oscillator the main resonator oscillates the following frequencies (f x ): ? f x = 2 to 2.5 mhz (regc = v dd = 2.7 to 5.5 v, in pll mode) ? f x = 2 to 5 mhz (regc = v dd = 4.5 v to 5.5 v, in pll mode) ? f x = 2 to 4 mhz (regc = capacitor, v dd = 4.0 to 5.5 v, in pll mode) ? f x = 2 to 10 mhz (regc = v dd = 2.7 to 5.5 v, in clock-through mode) (2) subclock oscillator the sub-resonator oscillates a frequency of 32.768 khz (f xt ). (3) main clock oscillator stop control this circuit generates a control signal that stops oscillation of the main clock oscillator. oscillation of the main clock oscillator is stopped in the stop mode or when the mck bit of the pcc register = 1 (valid only when the cls bit of the pcc register = 1). chapter 6 clock generation function user ? s manual u15862ej3v0ud 294 (4) prescaler 1 this prescaler generates the clock (f xx to f xx /1024) to be supplied to the following on-chip peripheral functions: tm00 to tm05, tm50, tm51, tmh0, tmh1, csi00 to csi02, csia0, csia1, uart0 to uart2, i 2 c0, i 2 c1, adc, dac, and wdt2 (5) prescaler 2 this circuit divides the cpu clock (f cpu ) and main clock (f xx ). the clock generated by prescaler 2 (f xx to f xx /32) is supplied to the selector that generates the internal system clock (f clk ). f clk is the clock supplied to the intc, rom correction, rom, and ram blocks, and can be output from the clkout pin. (6) prescaler 3 this circuit divides the clock (f x ) generated by the main clock oscillator to a specific frequency (32.768 khz) and supplies that clock to the watch timer block. for details, refer to chapter 11 watch timer functions . (7) pll this circuit multiplies the clock (f x ) generated by the main clock oscillator. it operates in two modes: clock-through mode in which f x is output as is, and pll mode in which a multiplied clock is output. these modes can be selected by using the selpll bit of the pll control register (pllctl). operation of the pll can be started or stopped by the pllon bit of the pllctl register. chapter 6 clock generation function user ? s manual u15862ej3v0ud 295 6.3 control registers (1) processor clock control register (pcc) the processor clock control register (pcc) is a special register. data can be written to this register only in combination of specific sequences (refer to 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. (1/2) frc used not used frc 0 1 use of subclock on-chip feedback resistor pcc mck mfrc cls note ck3 ck2 ck1 ck0 operating stopped mck 0 1 operation of main clock used not used mfrc 0 1 use of main clock on-chip feedback resistor after reset: 03h r/w after reset: fffff828h main clock operation subclock operation cls 0 1 status of cpu clock (f cpu ) even if the mck bit is set to 1 while the system is operating with the main clock as the cpu clock, the operation of the main clock does not stop. it stops after the cpu clock has been changed to the subclock. when the main clock is stopped and the device is operating on the subclock, clear the mck bit to 0 and wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. note the cls bit is a read-only bit. chapter 6 clock generation function user ? s manual u15862ej3v0ud 296 (2/2) f xx f xx /2 f xx /4 f xx /8 (default value) f xx /16 f xx /32 setting prohibited f xt ck2 0 0 0 0 1 1 1 clock selection (f clk /f cpu ) ck1 0 0 1 1 0 0 1 ck0 0 1 0 1 0 1 ck3 0 0 0 0 0 0 0 1 cautions 1. do not change the cpu clock (by using the ck3 to ck0 bits of the pcc register) while clkout is being output. 2. use a bit manipulation instruction to manipulate the ck3 bit. when using an 8-bit manipulation instruction, do not change the set values of the ck2 to ck0 bits. 3. when the cpu operates on the subclock and no clock is input to the x1 pin, do not access a register in which a wait occurs using an access method that causes a wait (refer to 3.4.8 (2) access to special on-chip peripheral i/o register for details of the access methods). if a wait occurs, it can only be released by a reset. remark : don ? t care (a) example of setting main clock operation subclock operation <1> internal system clock check: check that the following condition is satisfied. ? internal system clock (f xx ) > subclock (32.768 khz) 4 when the above condition is not satisfied, change the ck2 to ck0 bits to satisfy the condition. at this time, do not change the ck3 bit. <2> ck3 1: use of a bit manipulation instruction is recommended. do not change ck2 to ck0 bits. <3> subclock operation: it takes up to the following number of instructions after the ck3 bit is set until the subclock operation is started. max.: (f cpu of main clock/f xt ) therefore, read the cls bit to check if the subclock operation has started. <4> mck 1: set the mck bit to 1 only when stopping the main clock. chapter 6 clock generation function user ? s manual u15862ej3v0ud 297 (b) example of setting subclock operation main clock operation <1> mck 0: main clock oscillation starts. <2> insert wait cycles by program and wait until the oscillation of the main clock has been stabilized. <3> ck3 0: use of a bit manipulation instruction is recommended. do not change ck2, ck1, and ck0 bits. <4> main clock operation: it takes up to the following number of instructions after the ck3 bit is set until the main clock operation specified by ck2 to ck0 is started. max.: (1/subclock frequency) therefore, read the cls bit to check if the subclock operation has started. (2) power save control register (psc) the power save control register (psc) is a special register. data can be written to this register only in a combination of specific sequences (refer to 3.4.7 special registers ). this register can be read or written in 8-bit or 1-bit units. nmi2m psc 0 nmi0m intm 0 0 stp 0 intwdt2 request enabled intwdt2 request disabled nmi2m 0 1 controls non-maskable interrupt request (intwdt2) from watchdog timer 2 note 1 nmi request enabled nmi request disabled nmi0m 0 1 controls non-maskable interrupt request (nmi) from nmi pin note 1 intxx request enabled intxx request disabled intm 0 1 controls all maskable interrupt requests (intxx) note 1 normal mode standby mode note 2 stp 0 1 sets operation mode after reset: 00h r/w after reset: fffff1feh < > < > < > < > notes 1. setting these bits is valid only in the stop mode. 2. set stop or idle mode using the psm bit of the psmr register. remark for details of intxx, refer to tables 19-1 to 19-3 interrupt source lists . chapter 6 clock generation function user ? s manual u15862ej3v0ud 298 (3) power save mode register (psmr) this is an 8-bit register that controls the operation status in the power save mode and the clock operation. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 idle mode stop mode psm 0 1 specifies operation in software standby mode psmr 0 0 0 0 0 0 psm after reset: 00h r/w after reset: fffff820h < > cautions 1. be sure to clear bits 1 to 7 of the psmr register to 0. 2. the psm bit is valid only when the stp bit of the psc register is 1. (4) oscillation stabilization time selection register (osts) this register selects the oscillation stabilization time following reset or cancellation of the stop mode. refer to 12.1.3 (1) oscillation stabilization time selection register (osts) . chapter 6 clock generation function user ? s manual u15862ej3v0ud 299 6.4 operation 6.4.1 operation of each clock the following table shows the operation status of each clock. table 6-1. operation status of each clock clk bit = 0, mck bit = 0 cls bit = 1, mck bit = 0 cls bit = 1, mck bit = 1 <1> <2> <3> <4> <5> <6> <7> <6> <7> main clock oscillator (f x ) { { { { { subclock oscillator (f xt ) { { { { { { { { { cpu clock (f cpu ) { { internal system clock (f clk ) { { { peripheral clock (f xx to f xx /1024) { { wt clock (main) { { { { { wt clock (sub) { { { { { { { { { wdt1 clock (f xw ) { { { { { wdt2 clock (main) { { wdt2 clock (sub) { { { { { { { { { remark cls bit: bit 4 of the processor clock control register (pcc) mck bit: bit 6 of the pcc register o: operable : stopped <1>: reset pin input <2>: during oscillation stabilization time count <3>: halt mode <4>: idle mode <5>: stop mode <6>: subclock operation mode <7>: sub-idle mode 6.4.2 clock output function the clock output function is used to output the internal system clock (f clk ) from the clkout pin. the internal system clock (f clk ) is selected by using the ck3 to ck0 bits of the processor clock control register (pcc). the clkout pin functions alternately as the pcm1 pin and functions as a clock output pin if so specified by the control register of port cm. the status of the clkout pin is the same as the internal system clock in table 6-1 and the pin can output the clock when it is in the operable status. it outputs a low level in the stopped status. however, the alternate-function pin function (pcm1: input mode) is selected in <1> and <2> after the reset signal has been input. consequently, the clkout pin goes into a high-impedance state. 6.4.3 external clock input function an external clock can be directly input to the oscillator. input the clock to the x1 pin and its inverse signal to the x2 pin. set the mfrc bit of the pcc register to 1 (to cut off the feedback resistor). note, however, that oscillation stabilization time is inserted even in the external clock mode. chapter 6 clock generation function user ? s manual u15862ej3v0ud 300 6.5 pll function 6.5.1 overview the pll function is used to output the operating clock of the cpu and peripheral macro at a frequency 4 times higher than the oscillation frequency, and select the clock-through mode. when pll function is used: input clock = 2 to 5 mhz (f xx : 8 to 20 mhz) (usable voltage: v dd = 2.7 to 5.5 v) clock-through mode: input clock = 2 to 10 mhz (f xx : 2 to 10 mhz) 6.5.2 control register (1) pll control register (pllctl) this 8-bit register controls the pll function. this register can be read or written in 8-bit or 1-bit units. reset input sets pllctl to 01h. note for the rtost1 and rtost2 bits, refer to chapter 10 real-time output function (rto) . caution be sure to set bits 4 to 7 to 0. 0 pllctl 0 0 0 rtost1 note rtost0 note selpll pllon pll stopped pll operating pllon 0 1 pll operation stop register clock-through operation pll operation selpll 0 1 pll clock selection register after reset: 01h r/w after reset: fffff806h < > < > < > < > chapter 6 clock generation function user ? s manual u15862ej3v0ud 301 6.5.3 usage (1) to use pll ? after the reset has been released, the pll operates (pllon = 1), but because the default mode is the clock-through mode (selpll = 0), select the pll mode (selpll = 1). ? to set the idle or stop mode, first select the clock-through mode and then stop the pll. to return from the idle or stop mode, first enable pll operation (pllon = 1), and then select the pll mode (selpll = 1). ? to enable the pll operation, first set pllon to 1, wait for 200 s, and then set pllsel to 1. to stop the pll, first select the clock-through mode (selpll = 0), wait for 8 clocks or more, and then stop the pll (pllon = 0). (2) when pll is not used ? the clock-through mode (selpll = 0) is selected after the reset has been released, but the pll is operating (pllon = 1) and must therefore be stopped (pllon = 0). user?s manual u15862ej3v0ud 302 chapter 7 16-bit timer/event counters 00 to 05 the number of 16-bit timer/event counter 00 to 05 channels incorporated differs as follows depending on the product. product name v850es/kf1 v850es/kg1 v850es/kj1 number of channels 2 channels (tm00, tm01) 4 channels (tm00 to tm03) 6 channels (tm00 to tm05) 7.1 functions 16-bit timer/event counters 00 to 05 have the following functions. (1) interval timer generates an interrupt at predetermined time intervals. (2) ppg output can output a rectangular wave with any frequency and any output pulse width. (3) pulse width measurement can measure the pulse width of a signal input from an external source. (4) external event counter can measure the pulse width of a signal input from an external source. (5) square-wave output can output a square wave of any frequency. (6) one-shot pulse output (16-bit timer/event counters 00, 01, 04 and 05 only) can output a one-shot pulse with any output pulse width. chapter 7 16-bit timer/event counters 00 to 05 user?s manual u15862ej3v0ud 303 7.2 configuration 16-bit timer/event counters 00 to 05 consist of the following hardware. table 7-1. configuration of 16-bit timer/event counters 00 to 05 item configuration timer/counters 16 bits 1 6 channels (tm0n) registers 16-bit timer capture/compare register: 16 bits 2 6 channels (cr0n0, cr0n1) timer outputs 1 6 channels (to0n) control registers note 16-bit timer mode control register n (tmc0n) capture/compare control register n (crc0n) 16-bit timer output control register (toc0n) prescaler mode register 0n (prm0n) note to use the ti0n0, ti0n1, and to0n pin functions, refer to table 4-28 settings when port pins are used for alternate functions . remark n = 0 to 5 figure 7-1 shows the block diagram. chapter 7 16-bit timer/event counters 00 to 05 user?s manual u15862ej3v0ud 304 figure 7-1. block diagram of 16-bit timer/event counter 0n match clear noise eliminator noise eliminator 16-bit timer capture/compare register 0n0 (cr0n0) 16-bit timer capture/compare register 0n1 (cr0n1) 16-bit timer counter 0n (tm0n) match inttm0n0 to0n inttm0n1 internal bus tl0n1 f xx /4 tl0n0 2 crc0n2 prm0n1 crc0n2 crc0n1 crc0n0 prm0n0 tmc0n3 tmc0n2 tmc0n1 ovf0n ospt0m ospe0m toc0n4 lvs0n lvr0n toc0n1 toe0n count clock note capture/compare control register 0n (crc0n) output controller selector timer output control register 0n (toc0n) noise eliminator prescaler mode register 0n (prm0n) 16-bit timer mode control register 0n (tmc0n) selector selector internal bus selector note set by the prm0n register. remarks 1. ? ? are signals that can be directly connected to ports. 2. n = 0 to 5 m = 0, 1, 4, 5 3. f xx : internal system clock frequency (1) 16-bit timer counter 0n (tm0n) the tm0n register is a 16-bit read-only register that counts count pulses. the counter is incremented in synchronization with the rising edge of the input clock. the count value is reset to 0000h in the following cases. <1> at reset input <2> if the tmc0n3 and tmc0n2 bits are cleared. <3> if the valid edge of ti0n0 is input in the mode in which clear & start occurs when inputting the valid edge of ti0n0 <4> if the tm0n register and the cr0n0 register match each other in the mode in which clear & start occurs on cr0n0 register match <5> if the ospt0m bit is set or if the valid edge of ti0k0 is input in the one-shot pulse output mode remark n = 0 to 5 m = 0, 1, 4, 5 k = 4, 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 305 (2) 16-bit timer capture/compare register 0n0 (cr0n0) the cr0n0 register is a 16-bit register that combines capture register and compare register functions. bit 0 (crc0n0) of the capture/compare control register (crc0n) is used to set whether to use the cr0n0 register as a capture register or as a compare register. (a) when using the cr0n0 register as a compare register the value set to the cr0n0 register and the count value set to the tm0n register are always compared and when these values match, an interrupt request signal (inttm0n0) is generated. when the tm0n register is set to operate as an interval timer, cr0n0 can be used as a register for holding the interval time. (b) when using the cr0n0 register as a capture register the tm0n register count value is captured to the cr0n0 register by inputting a capture trigger. the valid edge of the ti0n0 pin or ti0n1 pin can be selected as the capture trigger. the valid edge of the ti0n0 pin or ti0n1 pin is set with prescaler mode register 0n (prm0n). table 7-2 shows the settings when the valid edge of the ti0n0 pin is specified as the capture trigger, and table 7-3 shows the settings when the valid edge of the ti0n1 is specified as the capture trigger. table 7-2. valid edge of ti0n0 pin and capture trigger of cr0n0 register esn01 esn00 valid edge of ti0n0 pin capture trigger of cr0n0 register 0 0 falling edge rising edge 0 1 rising edge falling edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges no capture operation remark n = 0 to 5 table 7-3. valid edge of ti0n1 pin and capture trigger of cr0n0 register esn11 esn10 valid edge of ti0n1 pin capture trigger of cr0n0 register 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges remark n = 0 to 5 the cr0n0 register is set by a 16-bit memory manipulation instruction. reset input sets this register to 0000h. chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 306 cautions 1. set a value other than 0000h to the cr0n0 register in the mode in which clear & start occurs upon a match of the values of the tm0n register and cr0n0 register. however, if 0000h is set to the cr0n0 register in the free-running mode or the ti0n0 valid edge clear mode, an interrupt request (inttm0n0) is generated after an overflow (ffffh). 2. when the p33, p35, p613, p92, and p94 pins are used as the valid edges of ti000, ti010, ti020, ti030, and ti051, they cannot be used as timer outputs (to00 to to03, to05). moreover, when used as to00 to to03 and to05, these pins cannot be used as the valid edge of ti000, ti010, ti020, ti030, and ti051. 3. if, when the cr0n0 register is used as a capture register, the register read interval and capture trigger input conflict, the read data becomes undefined (but the capture data itself is normal). moreover, when the count stop input and capture trigger input conflict, the capture data becomes undefined. 4. the cr0n0 register cannot be rewritten during tm0n register operation. chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 307 (3) 16-bit timer capture/compare register 0n1 (cr0n1) the cr0n1 register is a 16-bit register that combines capture register and compare register functions. bit 2 (crc0n2) of the crc0n register is used to set whether to use the cr0n1 register as a capture register or as a compare register. (a) when using the cr0n1 register as a compare register the value set to the cr0n1 register and the count value of the tm0n register are always compared and when these values match, an interrupt request signal (inttm0n1) is generated. (b) when using the cr0n1 register as a capture register the tm0n register count value is captured to the cr0n1 register by inputting a capture trigger. the valid edge of the ti0n0 pin can be selected as the capture trigger. the valid edge of the ti0n0 pin is set with the prm0n register. table 7-4 shows the settings when the valid edge of the ti0n0 pin is specified as the capture trigger. table 7-4. valid edge of ti0n0 pin and capture trigger of cr0n1 register esn01 esn00 valid edge of ti0n0 pin capture trigger of cr0n1 register 0 0 falling edge falling edge 0 1 rising edge rising edge 1 0 setting prohibited setting prohibited 1 1 both rising and falling edges both rising and falling edges remark n = 0 to 5 the cr0n1 register is set by a 16-bit memory manipulation instruction. reset input sets this register to 0000h. cautions 1. set a value other than 0000h to the cr0n1 register in the mode in which clear & start occurs upon a match of the values of the tm0n register and cr0n0 register. however, if 0000h is set to the cr0n1 register in the free-running mode or the ti0n1 valid edge clear mode, an interrupt request (inttm0n1) is generated after an overflow (ffffh). 2. when the p33, p35, p613, p92, and p94 pins are used as the valid edges of ti000, ti010, ti020, ti030, and ti051, they cannot be used as timer outputs (to00 to to03, to05). moreover, when used as to00 to to03 and to05, these pins cannot be used as the valid edges of ti000, ti010, ti020, ti030, and ti051. 3. if, when the cr0n1 register is used as a capture register, the register read interval and capture trigger input conflict, the read data becomes undefined (but the capture data itself is normal). moreover, when the count stop input and capture trigger input conflict, the capture data becomes undefined. 4. the cr0n1 register can be rewritten during tm0n register operation only in the ppg output mode. refer to 7.4.2 ppg output operation. chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 308 7.3 control registers the registers that control 16-bit timer/event counters 00 to 05 are as follows. ? 16-bit timer mode control register 0n (tmc0n) ? capture/compare control register 0n (crc0n) ? 16-bit timer output control register 0n (toc0n) ? prescaler mode register 0n (prm0n) remark to use the ti0n0, ti0n1, and to0n pin functions, refer to table 4-28 settings when port pins are used for alternate functions . (1) 16-bit timer mode control register 0n (tmc0n) tmc0n is used to set the 16-bit timer operation mode, the 16-bit timer counter 0n (tm0n) clear mode, and the output timing, and to detect overflow. the tmc0n register is set by an 8-bit or 1-bit memory manipulation instruction. reset input sets this register to 00h. caution the tm0n register starts operating when a value other than 00 (operation stop mode) is set to the tmc0n3 and tmc0n2 bits of the tmc0n register. to stop the operation, set 00 to the tmc0n3 and tmc0n2 bits. remark n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 309 7 0 operation stop (tm0n cleared to 0) free-running mode clear & start with valid edge of ti0n0 clear & start upon match of tm0n and cr0n0 unchanged match of tm0n and cr0n0 or match of tm0n and cr0n1 match of tm0m and cr0m0, match of tm0m and cr0m1, or valid edge of ti0m0 note match of tm0m and cr0m0 or match of tm0m and cr0m1 note match of tm0m and cr0m0, match of tm0m and cr0m1, or valid edge of ti0m0 note match of tm0n and cr0n0 or match of tm0n and cr0n1 match of tm0m and cr0m0, match of tm0m and cr0m1, or valid edge of ti0m0 note not generated generated upon match of tm0n and cr0n0 and match of tm0n and cr0n1 tmc0n3 0 0 0 0 1 1 1 1 selection of operation mode and clear mode selection of to0n output timing (n = 0 to 5 m = 4, 5) 6 0 5 0 4 0 3 tmc0n3 2 tmc0n2 1 tmc0n1 <0> ovf0n tmc0n2 0 0 1 1 0 0 1 1 tmc0n1 0 1 0 1 0 1 0 1 after reset: 00h r/w address: fffff606h, fffff616h, fffff626h fffff636h, fffff646h, fffff656h no overflow overflow ovf0n 0 1 detection of overflow of 16-bit timer register 0n tmc0n generation of interrupt note setting of tm00 to tm03 is prohibited. cautions 1. write to bits other than the ovf0n flag after stopping the timer operation. 2. the valid edge of the ti0n0 pin is set by prescaler mode register 0n (prm0n). 3. when the mode in which the timer is cleared and started upon match of tm0n and cr0n0 is selected, the setting value of cr0n0 is ffffh, and when the value of tm0n changes from ffffh to 0000h, the ovf0n flag is set to 1. remark to0n: output pin of 16-bit timer/event counter 0n ti0n0: input pin of 16-bit timer/event counter 0n tm0n: 16-bit timer counter 0n cr0n0: 16-bit timer capture/compare register 0n0 cr0n1: 16-bit timer capture/compare register 0n1 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 310 (2) capture/compare control register 0n (crc0n) crc0n controls the operation of 16-bit timer capture/compare registers 0n0 and 0n1 (cr0n0 and crc0n1). the crc0n register is set by an 8-bit or 1-bit memory manipulation instruction. reset input clears crc0n to 00h. 7 0 operation as compare register operation as capture register crc0n2 0 1 selection of operation mode of cr0n1 register crc0n 6 0 5 0 4 0 3 0 2 crc0n2 1 crc0n1 0 crc0n0 after reset: 00h r/w address: fffff608h, fffff618h, fffff628h fffff638h, fffff648h, fffff658h capture at valid edge of ti0n1 capture at inverse phase of valid edge of ti0n0 crc0n1 0 1 selection of capture trigger of cr0n0 register operation as compare register operation as capture register crc0n0 0 1 selection of operation mode of cr0n0 register (n = 0 to 5) cautions 1. before setting the crc0n register, be sure to stop the timer operation. 2. when the mode in which the timer is cleared and started upon match of the tm0n register and cr0n0 register is selected by 16-bit timer mode control register 0n (tmc0n), do not specify the cr0n0 register as the capture register. 3. when both the rising and falling edges are specified for the ti0n0 valid edge, capture operation is not performed. 4. to ensure reliable capture operation, a pulse longer than two of the count clocks selected by prescaler mode register 0n (prm0n) is required. remark ti0n0, ti0n1: input pins of 16-bit timer/event counter 0n. (3) 16-bit timer output control register 0n (toc0n) toc0n controls the operation of the 16-bit timer/event counter 0n output controller by setting or resetting the r-s flip-flop (lv0n), enabling or disabling inverse output, enabling or disabling the timer of 16-bit timer/event counter 0n, enabling or disabling the one-shot pulse output operation, and selecting an output trigger for a one-shot pulse by software (16-bit timer/event counters 02 and 03 do not have a one-shot pulse output function). the toc0n register is set by an 8-bit memory manipulation instruction. reset input clears toc0n to 00h. chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 311 0 output disabled output enabled ospt0m note 1 0 1 control of output trigger for one-shot pulse by software toc0n ospt0m note 1 ospe0m note 1 toc0n4 lvs0n lvr0n toc0n1 toe0n successive pulse output one-shot pulse output note 2 ospe0m note 1 0 1 control of one-shot pulse output operation inversion operation disabled inversion operation enabled toc0n4 0 1 control of timer output f/f upon match of cr0n1 register and tm0n register inversion operation disabled inversion operation enabled toc0n1 0 1 control of timer output f/f upon match of cr0n0 register and tm0n register output disabled (output is fixed to 0 level) output enabled toe0n 0 1 control of output of 16-bit timer/event counter 0n unchanged reset timer output f/f (0) set timer output f/f (1) setting prohibited lvs0n 0 0 1 1 setting of status of timer output f/f of 16-bit timer/event counter 0n lvr0n 0 1 0 1 after reset: 00h r/w address: fffff609h, fffff619h, fffff629h fffff639h, fffff649h, fffff659h (n = 0 to 5 m = 0, 1, 4, 5 k = 4, 5) 76 54 32 1 0 notes 1. when using tm02 and tm03, be sure to set bits 5 and 6 to 0. when using tm00 and tm01, since the valid edges of the ti000 and ti010 pins cannot be used, set the tmc0n bit of the tmc00 and tmc01 registers to 0. 2. the one-shot pulse output operates normally in the free-running mode and the mode in which clear & start occurs on the valid edge of ti0k0. in the mode in which clear & start occurs on match between the tm0m register and the cr0m0 register, one-shot pulse output is not performed because no overflow occurs. cautions 1. be sure to stop the timer operation before setting other than the toc0n4 bit. 2. the lvs0n and lvr0n bits are 0 when read after data has been set to them. 3. the ospt0m bit is 0 when read because it is automatically cleared after data has been set. 4. do not set (to 1) the ospt0m bit other than for one-shot pulse output. 5. when performing successive writes to the ospt0m bit, place an interval between writes of two or more operating clocks. chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 312 (4) prescaler mode register 0n (prm0n) this register sets the count clock of 16-bit timer counter 0n (tm0n) and the valid edge of the ti0n0 and ti0n1 pin inputs. the prm0n register is set by an 8-bit memory manipulation instruction. reset input clears prm0n to 00h. cautions 1. when setting the count clock to the ti0n0 valid edge, do not set the mode in which clear & start occurs on ti0n0 valid edge and do not set the ti0n0 valid edge as the capture trigger. 2. before setting the prm0n register, be sure to stop the timer operation. 3. if 16-bit timer counter 0n (tm0n) operation is enabled by specifying the rising edge of both edges for the valid edge of the ti0n0 pin or ti0n1 pin while the ti0n0 pin or ti0n1 pin is high level immediately after system reset, the rising edge is detected immediately after the rising edge or both edges is specified. be careful when pulling up the ti0n0 pin or ti0n1 pin. however, the rising edge is not detected when operation is enabled after it has been stopped. 4. when the p33, p35, p613, p92, and p94 pins are used as the valid edges of ti000, ti010, ti020, ti030, and ti051, they cannot be used as timer outputs (to00 to to03, to05). moreover, when used as to00 to to03 and to05, these pins cannot be used as the valid edges of ti000, ti010, ti020, ti030, and ti051. chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 313 (a) prescaler mode register 00 (prm00) es011 falling edge rising edge setting prohibited both rising and falling edges es011 0 0 1 1 selection of valid edge of ti001 prm00 es010 es001 es000 0 0 prm001 prm000 es010 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges es001 0 0 1 1 selection of valid edge of ti000 es000 0 1 0 1 f xx /2 f xx /4 f xx /8 valid edge of ti000 note 2 selection of count clock note 1 prm001 0 0 1 1 prm000 0 1 0 1 20 mhz 100 ns 200 ns 400 ns ? 16 mhz 125 ns 250 ns 500 ns ? count clock f xx after reset: 00h r/w address: fffff607h 76 54 32 1 0 notes 1. when the internal clock is selected, set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 to 4.0 v: count clock 5 mhz 2. the external clock requires a pulse longer than two internal clocks (f xx /4). remark f xx : internal system clock frequency chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 314 (b) prescaler mode register 01 (prm01) es111 falling edge rising edge setting prohibited both rising and falling edges es111 0 0 1 1 selection of valid edge of ti0n1 prm01 es110 es101 es100 0 0 prm011 prm010 es110 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges es101 0 0 1 1 selection of valid edge of ti0n0 es100 0 1 0 1 f xx f xx /4 intwt valid edge of ti010 note 2 selection of count clock note 1 prm011 0 0 1 1 prm010 0 1 0 1 20 mhz setting prohibited 200 ns ? ? 16 mhz setting prohibited 250 ns ? ? count clock f xx after reset: 00h r/w address: fffff617h 76 54 32 1 0 notes 1. when the internal clock is selected, set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 to 4.0 v: count clock 5 mhz 2. the external clock requires a pulse longer than two internal clocks (f xx /4). remark f xx : internal system clock frequency chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 315 (c) prescaler mode register 02 (prm02) es211 falling edge rising edge setting prohibited both rising and falling edges es211 0 0 1 1 selection of valid edge of ti021 prm02 es210 es201 es200 0 0 prm021 prm020 es210 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges es201 0 0 1 1 selection of valid edge of ti020 es200 0 1 0 1 f xx /2 f xx /4 f xx /8 valid edge of ti020 note 2 selection of count clock note 1 prm021 0 0 1 1 prm020 0 1 0 1 20 mhz 100 ns 200 ns 400 ns ? 16 mhz 125 ns 250 ns 500 ns ? count clock f xx after reset: 00h r/w address: fffff627h 76 54 32 1 0 notes 1. when the internal clock is selected, set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 to 4.0 v: count clock 5 mhz 2. the external clock requires a pulse longer than two internal clocks (f xx /4). remark f xx : internal system clock frequency chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 316 (d) prescaler mode register 03 (prm03) es311 falling edge rising edge setting prohibited both rising and falling edges es311 0 0 1 1 selection of valid edge of ti031 prm03 es310 es301 es300 0 0 prm031 prm030 es310 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges es301 0 0 1 1 selection of valid edge of ti030 es300 0 1 0 1 f xx /4 f xx /16 f xx /512 valid edge of ti030 note 2 selection of count clock note 1 prm031 0 0 1 1 prm030 0 1 0 1 20 mhz 200 ns 800 ns 25.6 s ? 16 mhz 250 ns 1 s 32 s ? count clock f xx after reset: 00h r/w address: fffff637h 76 54 32 1 0 notes 1. when the internal clock is selected, set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 to 4.0 v: count clock 5 mhz 2. the external clock requires a pulse longer than two internal clocks (f xx /4). remark f xx : internal system clock frequency chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 317 (e) prescaler mode register 04 (prm04) es411 falling edge rising edge setting prohibited both rising and falling edges es411 0 0 1 1 selection of valid edge of ti041 prm04 es410 es401 es400 0 0 prm041 prm040 es410 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges es401 0 0 1 1 selection of valid edge of ti040 es400 0 1 0 1 f xx /2 f xx /4 f xx /8 valid edge of ti040 note 2 selection of count clock note 1 prm041 0 0 1 1 prm040 0 1 0 1 20 mhz 100 ns 200 ns 400 ns ? 16 mhz 125 ns 250 ns 500 ns ? count clock f xx after reset: 00h r/w address: fffff647h 76 54 32 1 0 notes 1. when the internal clock is selected, set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 to 4.0 v: count clock 5 mhz 2. the external clock requires a pulse longer than two internal clocks (f xx /4). remark f xx : internal system clock frequency chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 318 (f) prescaler mode register 05 (prm05) es511 falling edge rising edge setting prohibited both rising and falling edges es511 0 0 1 1 selection of valid edge of ti051 prm05 es510 es501 es500 0 0 prm051 prm050 es510 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges es501 0 0 1 1 selection of valid edge of ti050 es500 0 1 0 1 f xx f xx /4 f xx /256 valid edge of ti050 note 2 selection of count clock note 1 prm051 0 0 1 1 prm050 0 1 0 1 20 mhz setting prohibited 200 ns 128 s ? 16 mhz setting prohibited 250 ns 16 s ? count clock f xx after reset: 00h r/w address: fffff657h 76 54 32 1 0 notes 1. when the internal clock is selected, set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 to 4.0 v: count clock 5 mhz 2. the external clock requires a pulse longer than two internal clocks (f xx /4). remark f xx : internal system clock frequency chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 319 7.4 operation 7.4.1 operation as interval timer (16 bits) 16-bit timer/event counter 0n can be made to operate as an interval timer by setting 16-bit timer mode control register 0n (tmc0n) and capture/compare control register 0n (crc0n) as shown in figure 7-2 (n = 0 to 5). setting procedure the basic operation setting procedure is as follows. <1> set the crc0n register (see figure 7-2 for the setting value). <2> set any value to the crc0n0 register. <3> set the count clock using the prm0n register. <4> enable the inttm0n0 interrupt (see chapter 19 interrupt/exception processing function for details). <5> set the tmc0n register: start operation (see figure 7-2 for the setting value). the interval timer repeatedly generates interrupts at the interval of the preset count value in 16-bit timer capture/compare register 0n0 (cr0n0). if the count value in 16-bit timer counter 0n (tm0n) matches the value set in the cr0n0 register, an interrupt request signal (inttm0n0) is generated at the same time that the value of the tm0n register is cleared to 0 and counting is continued. the count clock of 16-bit timer/event counter 0n can be selected with bits 0 and 1 of prescaler mode register 0n (prm0n). the value of the cr0n0 and cr0n1 registers cannot be changed during timer count operation. however, the cr0n1 register value can be changed in the ppg output mode. for details, refer to 7.4.2 ppg output operation . remark n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 320 figure 7-2. control register setting contents during interval timer operation (a) 16-bit timer mode control register 0n (tmc0n) 0 tmc0n 000110/10 tmc0n3 tmc0n2 tmc0n1 ovf0n clears & starts upon match between tm0n and cr0n0 (b) capture/compare control register 0n (crc0n) 0 crc0n 00000/10/10 crc0n2 crc0n1 crc0n0 cr0n0 used as compare register remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the interval timer function. for details, refer to 7.3 (1) 16-bit timer mode control register 0n (tmc0n) and 7.3 (2) capture/compare control register 0n (crc0n) . 2. n = 0 to 5 figure 7-3. configuration of interval timer 16-bit timer capture/compare register 0n0 (cr0n0) 16-bit timer counter 0n (tm0n) selector ovf0n inttm0n0 count clock note ti0n0 clear circuit noise eliminator f xx /4 note set with prm0n register. remarks 1. ? ? indicates a signal that can be directly connected to a port. 2. f xx : internal system clock frequency 3. n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 321 figure 7-4. timing of interval timer operation t interval time interval time interval time 0000h n 0001h 0001h 0000h nn n n n n 0001h 0000h clear interrupt acknowledgment interrupt acknowledgment clear count clock tm0n count value cr0n0 inttm0n0 count start remarks 1. interval time = (n + 1) t: n = 0001h to ffffh 2. n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 322 7.4.2 ppg output operation 16-bit timer/event counter 0n can be used for ppg (programmable pulse generator) output by setting 16-bit timer mode control register 0n (tmc0n) and capture/compare control register 0n (crc0n) as shown in figure 7-5 . setting procedure the basic operation setting procedure is as follows. <1> set the pins to the to0n pin mode (see chapter 4 port functions ). <2> set the crc0n register (see figure 7-5 for the setting value). <3> set any value to the crc0n0 register. <4> set any value as a duty to the cr0n1 register. <5> set the toc0n register (see figure 7-5 for the setting value). <6> set the count clock using the prm0n register. <7> enable the inttm0n0 interrupt (see chapter 19 interrupt/exception processing function for details). <8> set the tmc0n register: start operation (see figure 7-5 for the setting value). note to change the duty value (cr0n1 register) during operation, refer to caution 2 in figure 7-5 control register settings in ppg output operation . the ppg output function outputs a rectangular wave from the to0n pin with the cycle specified by the count value set in advance to 16-bit timer capture/compare register 0n0 (cr0n0) and the pulse width specified by the count value set in advance to 16-bit timer capture/compare register 0n1 (cr0n1). chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 323 figure 7-5. control register settings in ppg output operation (a) 16-bit timer mode control register 0n (tmc0n) 00001 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n clears and starts upon match between tm0n and cr0n0 100 (b) capture/compare control register 0n (crc0n) 00000 crc0n crc0n2 crc0n1 crc0n0 cr0n0 used as compare register cr0n1 used as compare register 0 : don't care 0 (c) 16-bit timer output control register 0n (toc0n) 0 0 0 1 0/1 toc0n enables to0n output inverts output upon match between tm0n and cr0n0 specifies initial value of to0n output f/f inverts output upon match between tm0n and cr0n1 disables one-shot pulse output (other than tm02, tm03) 0/1 1 1 lvr0n toc0n1 toe0n ospe0n ospt0n toc0n4 lvs0n cautions 1. make sure that 0000h < cr0n1 < cr0n0 ffffh is set to the cr0n0 register and cr0n1 register. 2. the cycle of the pulse generated by ppg output is (cr0n0 setting value + 1). the duty factor is (cr0n1 setting value + 1) / (cr0n0 setting value + 1) remark n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 324 figure 7-6. configuration of ppg output f xx /4 ti0k0 to0n 16-bit capture/compare register 0n1 (cr0n1) 16-bit capture/compare register 0n0 (cr0n0) count clock note selector noise eliminator 16-bit timer counter 0n (tm0n) clear circuit output controller note the count clock is set by the prm0n register. remarks 1. ? ? indicates a signal that can be directly connected to a port. 2. k = 4, 5 n =0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 325 figure 7-7. ppg output operation timing t 0000h 0000h 0001h 0001h m-1 to0n n m m n-1 n count clock tm0n count value value loaded to cr0n0 value loaded to cr0n1 clear count starts pulse width: (m + 1) t 1 cycle: (n + 1) t caution cr0n0 cannot be rewritten during tm0n operation. remarks 1. 0000h < m < n ffffh 2. change the pulse width during tm0n operation (rewrite cr0n1) as follows in a ppg output operation. <1> disable the timer output inversion operation based on a match of tm0n and cr0n1 (toc0n4 = 0). <2> disable the inttm0n1 interrupt (tm0mkn1 =1). <3> rewrite cr0n1. <4> wait for a cycle of the tm0n count clock. <5> enable the timer output inversion operation based on a match of tm0n and cr0n1 (toc0n4 = 1). <6> clear the interrupt request flag of inttm0n1 (tm0ifn1 = 0). <7> enable the inttm0n1 interrupt (tm0mkn1 = 0). 3. n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 326 7.4.3 pulse width measurement the 16-bit timer counter (tm0n) can be used to measure the pulse widths of the signals input to the ti0n0 and ti0n1 pins. measurement can be carried out with the tm0n register used as a free-running counter or by restarting the timer in synchronization with the edge of the signal input to the ti0n0 pin. setting procedure the basic operation setting procedure is as follows. <1> set the pins to the ti0n0 (or ti0n1) pin mode (see chapter 4 port functions ). <2> set the crc0n register (see figures 7-8 , 7-11 , 7-14 , and 7-16 for the setting value). <3> set the count clock using the prm0n register. <4> enable the inttm0n0 (or inttm0n1) interrupt (see chapter 19 interrupt/exception processing function for details). <5> set the tmc0n register: start operation (see figures 7-8 , 7-11 , 7-14 , and 7-16 for the setting value). note when using two capture registers, set the ti0n0 and ti0n1 pins. (1) pulse width measurement with free-running counter and one capture register if the edge specified by prescaler mode register 0n (prm0n) is input to the ti0n0 pin when 16-bit timer counter 0n (tm0n) is operated as a free-running counter (refer to figure 7-8 ), the value of the tm0n register is loaded to 16-bit timer capture/compare register 0n1 (cr0n1) and an external interrupt request signal (inttm0n1) is set. the edge is specified by using bits 4 and 5 (esn00, esn01) of the prm0n register. the rising edge, falling edge, or both the rising and falling edges can be selected. the valid edge is detected through sampling at a count clock cycle selected with the prm0n register, and the capture operation is not performed until the valid edge is detected twice. as a result, noise with a short pulse width can be eliminated. remark n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 327 figure 7-8. control register settings for pulse width measurement with free-running counter and one capture register (a) 16-bit timer mode control register 0n (tmc0n) 00000 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n free-running mode 1 0/1 0 (b) capture/compare control register 0n (crc0n) 00000 crc0n crc0n2 crc0n1 crc0n0 cr0n0 used as compare register cr0n1 used as capture register 1 0/1 0 remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the pulse width measurement function. for details, refer to 7.3 (1) 16-bit timer mode control register 0n (tmc0n) and 7.3 (2) capture/compare control register 0n (crc0n) . 2. n = 0 to 5 figure 7-9. configuration for pulse width measurement with free-running counter 16-bit timer counter 0n (tm0n) 16-bit timer capture/compare register 0n1 (cr0n1) selector ovf0n inttm0n1 internal bus ti0n0 count clock note note the count clock is set with the prm0n register. remarks 1. ? ? indicates a signal that can be directly connected to a port. 2. n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 328 figure 7-10. timing of pulse width measurement with free-running counter and one capture register (with both edges specified) t 0000h 0000h ffffh 0001h d0 d0 + 1 d1 d0 d1 d2 d3 d2 d3 d1 + 1 (d1 ? d0) t (d3 ? d2) t (10000h ? d1 + d2) t count clock tm0n count value ti0n0 pin input value loaded to cr0n1 inttm0n1 ovf0n cleared by instruction remark n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 329 (2) measurement of two pulse widths with free-running counter the pulse widths of two signals respectively input to the ti0n0 pin and the ti0n1 pin can be simultaneously measured when 16-bit timer counter 0n (tm0n) is used as a free-running counter (refer to figure 7-11 ). when the edge specified by bits 4 and 5 (esn00, esn01) of prescaler mode register 0n (prm0n) is input to the ti0n0 pin, the value of the tm0n register is loaded to 16-bit timer capture/compare register 0n1 (cr0n1) and an external interrupt request signal (inttm0n1) is set. when the edge specified by bits 6 and 7 (esn10 and esn11) of the prm0n register is input to the ti0n1 pin, the value of the tm0n register is loaded to 16-bit timer capture/compare register 0n0 and an external interrupt request signal (inttm0n0) is set. the edges of the ti0n0 and ti0n1 pins are specified by bits 4 and 5 (esn00 and esn01) and bits 6 and 7 (esn10, esn11) of the prm0n register, respectively. the rising, falling, or both rising and falling edges can be specified. the valid edge of the ti0n0 pin is detected through sampling at the count clock cycle selected with the prm0n register, and the capture operation is not performed until the valid level is detected twice. as a result, noise with a short pulse width can be eliminated. remark n = 0 to 5 figure 7-11. control register settings for measurement of two pulse widths with free-running counter (a) 16-bit timer mode control register 0n (tmc0n) 0 tmc0n 000010/10 tmc0n3 tmc0n2 tmc0n1 ovf0n free-running mode (b) capture/compare control register 0n (crc0n) 0 crc0n 0000101 crc0n2 crc0n1 crc0n0 cr0n0 used as capture register captures to cr0n0 at valid edge of ti0n1 pin cr0n1 used as capture register remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the pulse width measurement function. for details, refer to 7.3 (1) 16-bit timer mode control register 0n (tmc0n) . 2. n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 330 ? capture operation (free-running mode) the following figure illustrates the operation of the capture register when the capture trigger is input. figure 7-12. cr0n1 capture operation with rising edge specified n ? 3n ? 2n ? 1 n n + 1 n count clock tm0n cr0n1 inttm0n1 ti0n0 rising edge detection remark n = 0 to 5 figure 7-13. timing of pulse width measurement with free-running counter (with both edges specified) t 0000h 0001h ffffh 0000h d0 d0 + 1 d1 d0 d1 d1 d2 + 1 d2 d1 + 1 d2 d3 d2 + 1 d2 + 2 (d1 ? d0) t(d3 ? d2) t (10000h ? d1 + d2) t (10000h ? d1 + (d2 + 1)) t count clock tm0n count value ti0n0 pin input ti0n1 pin input value loaded to cr0n1 value loaded to cr0n0 inttm0n1 inttm0n0 ovf0n remark n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 331 (3) pulse width measurement with free-running counter and two capture registers when 16-bit timer counter 0n (tm0n) is used as a free-running counter (refer to figure 7-14 ), the pulse width of the signal input to the ti0n0 pin can be measured. when the edge specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register 0n (prm0n) is input to the ti0n0 pin, the value of the tm0n register is loaded to 16-bit timer capture/compare register 0n1 (cr0n1) and an external interrupt request signal (inttm0n1) is set. the value of the tm0n register is also loaded to 16-bit timer capture/compare register 0n0 (cr0n0) when an edge inverse to the one that triggers capturing to the cr0n1 register is input. the edge of the ti0n0 pin is specified by bits 4 and 5 (esn00 and esn01) of the prm0n register. the rising or falling edge can be specified. the valid edge of the ti0n0 pin is detected through sampling at a count clock cycle selected with the prm0n register, and the capture operation is not performed until the valid edge is detected twice. as a result, noise with a short pulse width can be eliminated. caution if the valid edge of the ti0n0 pin is specified to be both the rising and falling edges, the cr0n0 register cannot perform capture operation. figure 7-14. control register settings for pulse width measurement with free-running counter and two capture registers (a) 16-bit timer mode control register 0n (tmc0n) 0 tmc0n 000010/10 tmc0n3 tmc0n2 tmc0n1 ovf0n free-running mode (b) capture/compare control register 0n (crc0n) 0 crc0n 0000111 crc0n2 crc0n1 crc0n0 cr0n0 used as capture register captures to cr0n0 at edge inverse to valid edge of ti0n0 pin cr0n1 used as capture register remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the pulse width measurement function. for details, refer to 7.3 (1) 16-bit timer mode control register 0n (tmc0n) . 2. n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 332 figure 7-15. timing of pulse width measurement with free-running counter and two capture registers (with rising edge specified) t 0000h 0001h ffffh 0000h d0 d0 d1 d3 d2 d0 + 1 d1 d1 + 1 d2 d3 d2 + 1 (d1 ? d0) t(d3 ? d2) t (10000h ? d1 + d2) t count clock tm0n count value ti0n0 pin input value loaded to cr0n1 value loaded to cr0n0 inttm0n1 ovf0n cleared by instruction remark n = 0 to 5 (4) pulse width measurement by restarting when the valid edge of the ti0n0 pin is detected, the pulse width of the signal input to the ti0n0 pin can be measured by clearing the tm0n register and then resuming counting after loading the count value of 16-bit timer counter 0n (tm0n) to 16-bit timer capture/compare register 0n1 (cr0n1) (refer to figure 7-17 ). the edge is specified by bits 4 and 5 (esn00 and esn01) of prescaler mode register 0n (prm0n). the rising or falling edge can be specified. the valid edge is detected through sampling at a count clock cycle selected with the prm0n register and the capture operation is not performed until the valid level is detected twice. as a result, noise with a short pulse can be eliminated. caution if the valid edge of the ti0n0 pin is specified to be both the rising and falling edges, capture/compare register 0n0 (cr0n0) cannot perform a capture operation. chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 333 figure 7-16. control register settings for pulse width measurement by restarting (a) 16-bit timer mode control register 0n (tmc0n) 0 tmc0n 000100/10 tmc0n3 tmc0n2 tmc0n1 ovf0n clears and starts at valid edge of ti0n0 pin (b) capture/compare control register 0n (crc0n) 0 crc0n 0000111 crc0n2 crc0n1 crc0n0 cr0n0 used as capture register captures to cr0n0 at edge inverse to valid edge of ti0n0 pin cr0n1 used as capture register remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the pulse width measurement function. for details, refer to 7.3 (1) 16-bit timer mode control register 0n (tmc0n) . 2. n = 0 to 5 figure 7-17. timing of pulse width measurement by restarting (with rising edge specified) t (d1 + 1) t (d2 + 1) t d0 d0 d2 d1 d1 d2 0001h 0000h 0001h 0000h 0001h 0000h count clock tm0n count clock ti0n0 pin input inttm0n1 value loaded to cr0n1 value loaded to cr0n0 remark n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 334 7.4.4 operation as external event counter setting procedure the basic operation setting procedure is as follows. <1> set the pins to the ti0n0 pin mode (see chapter 4 port functions ). <2> set the crc0n register (see figure 7-18 for the setting value). <3> set the count clock using the prm0n register. <4> set any value (except for 0000h) to the crc0n0 register. <5> enable the inttm0n0 (or inttm0n1) interrupt (see chapter 19 interrupt/exception processing function for details). <6> set the tmc0n register: start operation (see figure 7-18 for the setting value). the external event counter counts the number of clock pulses input to the ti0n0 pin from an external source by using 16-bit timer counter 0n (tm0n). each time the valid edge specified by prescaler mode register 0n (prm0n) has been input, the tm0n register is incremented. when the count value of the tm0n register matches the value of 16-bit timer capture/compare register 0n0 (cr0n0), the tm0n register is cleared to 0 and an interrupt request signal (inttm0n0) is generated. set the cr0n0 register to a value other than 0000h (one-pulse count operation is not possible). the edge is specified by bits 4 and 5 (esn00 and esn01) of the prm0n register. the rising, falling, or both the rising and falling edges can be specified. the valid edge is detected through sampling at a count clock cycle of f xx /4, and the capture operation is not performed until the valid level is detected twice. as a result, noise with a short pulse width can be eliminated. cautions 1. when using the tm00 to tm03 registers as external event counters, the timer outputs (to00 to to03) cannot be used. 2. the value of the cr0n0 and cr0n1 registers cannot be changed during timer count operation. however, the cr0n1 register value can be changed in the ppg output mode. for details, refer to 7.4.2 ppg output operation. remark n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 335 figure 7-18. control register settings in external event counter mode (a) 16-bit timer mode control register 0n (tmc0n) 00001 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n clears and starts on match between tm0n and cr0n0 1 0/1 0 (b) capture/compare control register 0n (crc0n) 00000 crc0n crc0n2 crc0n1 crc0n0 cr0n0 used as compare register 0/1 0/1 0 remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the external event counter function. for details, refer to 7.3 (1) 16-bit timer mode control register 0n (tmc0n) and 7.3 (2) capture/compare control register 0n (crc0n) . 2. n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 336 figure 7-19. configuration of external event counter 16-bit timer capture/compare register 0n0 (cr0n0) 16-bit timer counter 0n (tm0n) 16-bit timer capture/compare register 0n1 (cr0n1) selector ovf0n inttm0n0 count clock note fxx/4 ti0n0 valid edge internal bus noise eliminator match clear note set with the prm0n register. remarks 1. ? ? indicates a signal that can be directly connected to a port. 2. n = 0 to 5 figure 7-20. timing of external event counter operation (with rising edge specified) 0000h 0001h 0002h 0003h 0000h 0001h 0002h 0003h 0004h 0005h n ? 1n n ti0n0 pin input tm0n count value cr0n0 inttm0n0 count start cautions 1. read the tm0n register when reading the count value of the external event counter. 2. counting is not possible at the first valid edge after the external event counter mode is entered. remark n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 337 7.4.5 square-wave output operation setting procedure the basic operation setting procedure is as follows. <1> set the count clock using the prm0n register. <2> set the crc0n register (see figure 7-21 for the setting value). <3> set the toc0n register (see figure 7-21 for the setting value). <4> set any value (except for 0000h) to the crc0n0 register. <5> set the pins to the to0n pin mode (see chapter 4 port functions ). <6> enable the inttm0n0 interrupt (see chapter 19 interrupt/exception processing function for details). <7> set the tmc0n register: start operation (see figure 7-21 for the setting value). 16-bit timer/event counter 0n can be used to output a square wave with any frequency at an interval specified by the count value set in advance to 16-bit timer capture/compare register 0n0 (cr0n0). by setting bits 0 (toe0n) and 1 (toc0n1) of 16-bit timer output control register 0n (toc0n) to 1, the output status of the to0n pin is inverted at an interval set in advance to the cr0n0 register. in this way, a square wave of any frequency can be output. caution the value of the cr0n0 and cr0n1 registers cannot be changed during timer count operation. however, the cr0n1 register value can be changed in the ppg output mode. for details, refer to 7.4.2 ppg output operation. chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 338 figure 7-21. control register settings in square-wave output mode (a) 16-bit timer mode control register 0n (tmc0n) 00001 tmc0n3 tmc0n tmc0n2 tmc0n1 ovf0n clears and starts upon match between tm0n and cr0n0 100 (b) capture/compare control register 0n (crc0n) 00000 crc0n crc0n2 crc0n1 crc0n0 cr0n0 used as compare register 0/1 0/1 0 (c) 16-bit timer output control register 0n (toc0n) 00000/1 toc0n lvr0n lvs0n toc0n4 ospe0n ospt0n toc0n1 toe0n enables to0n output inverts output upon match between tm0n and cr0n0 specifies initial value of to0n output f/f does not invert output upon match between tm0n and cr0n1 disables one-shot pulse output (other than tm02 and tm03) 0/1 1 1 remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the square-wave output function. for details, refer to 7.3 (2) capture/compare control register 0n (crc0n) and 7.3 (3) 16-bit timer output control register 0n (toc0n) . 2. n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 339 figure 7-22. timing of square-wave output operation 0000h 0001h 0002h 0000h 0001h 0002h n ? 1n n 0000h n ? 1n count clock tm0n count value cr0n0 inttm0n0 to0n pin output remark n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 340 7.4.6 one-shot pulse output operation the one-shot pulse output is valid only for 16-bit timer/event counters 00, 01, 04, and 05. 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (ti0k0 pin input). setting procedure the basic operation setting procedure is as follows. <1> set the count clock using the prm0m register. <2> set the crc0m register (see figures 7-23 and 7-25 for the setting value). <3> set the toc0m register (see figures 7-23 and 7-25 for the setting value). <4> set any value to the crc0m0 and crc0m1 registers. <5> set the pins to the to0m0 pin mode (see chapter 4 port functions ). <6> enable the inttm0m0 interrupt (see chapter 19 interrupt/exception processing function for details). <7> set the tmc0m register: start operation (see figures 7-23 and 7-25 for the setting value). (1) one-shot pulse output with software trigger (16-bit timer/event counters 00, 01, 04, and 05 only) a one-shot pulse can be output from the to0m pin by setting 16-bit timer mode control register 0m (tmc0m), capture/compare control register 0m (crc0m), and 16-bit timer output control register 0m (toc0m) as shown in figure 7-23, and by setting bit 6 (ospt0m) of the toc0m register to 1 by software. by setting the ospt0m bit to 1, 16-bit timer/event counter 0m is cleared and started, and its output becomes active at the count value (n) set in advance to 16-bit timer capture/compare register 0m1 (cr0m1). after that, the output becomes inactive at the count value (m) set in advance to 16-bit timer capture/compare register 0m0 (cr0m0) note . even after the one-shot pulse has been output, the tm0m register continues its operation. to stop the tm0m register, the tmc0m3 and tmc0m2 bits of the tmc0m register must be set to 00. note the case where n < m is described here. when n > m, the output becomes active with the cr0m0 register and inactive with the cr0m1 register. cautions 1. do not set the ospt0m bit while the one-shot pulse is being output. to output the one- shot pulse again, wait until the current one-shot pulse output is completed. 2. the value of the cr0m0 and cr0m1 registers cannot be changed during timer count operation. however, the cr0m1 register value can be changed in the ppg output mode. for details, refer to 7.4.2 ppg output operation. remark m = 0, 1, 4, 5 k = 4, 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 341 figure 7-23. control register settings for one-shot pulse output with software trigger (a) 16-bit timer mode control register 0m (tmc0m) 00000 tmc0m3 tmc0m tmc0m2 tmc0m1 ovf0m free-running mode 100 (b) capture/compare control register 0m (crc0m) 00000 crc0m crc0m2 crc0m1 crc0m0 cr0m0 used as compare register cr0m1 used as compare register 0 0/1 0 (c) 16-bit timer output control register 0m (toc0m) 0 0 1 1 0/1 toc0m lvr0m lvs0m toc0m4 ospe0m ospt0m toc0m1 toe0m enables to0m output inverts output upon match between tm0m and cr0m0 specifies initial value of to0m output f/f inverts output upon match between tm0m and cr0m1 sets one-shot pulse output mode set to 1 for output 0/1 1 1 caution do not set 0000h to the cr0m0 and cr0m1 registers. remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the one- shot pulse output function. for details, refer to 7.3 (2) capture/compare control register 0n (crc0n) and 7.3 (3) 16-bit timer output control register 0n (toc0n) . 2. m = 0, 1, 4, 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 342 figure 7-24. timing of one-shot pulse output operation with software trigger 0000h n nn n n mm m m nm n + 1 n ? 1m ? 1 0001h m + 1 m + 2 0000h count clock tm0m count cr0m1 set value cr0m0 set value ospt0m inttm0m1 inttm0m0 to0m pin output set tmc0m to 0ch (tm0m count starts) caution 16-bit timer counter 0m starts operating as soon as a value other than 00 (operation stop mode) is set to the tmc0m3 and tmc0m2 bits. remark m = 0, 1, 4, 5 n < m (2) one-shot pulse output with external trigger (16-bit timer/event counters 04 and 05 only) a one-shot pulse can be output from the to0k pin by setting 16-bit timer mode control register 0k (tmc0k), capture/compare control register 0k (crc0k), and 16-bit timer output control register 0k (toc0k) as shown in figure 7-25, and by using the valid edge of the ti0k0 pin as an external trigger. the valid edge of the ti0k0 pin is specified by bits 4 and 5 (esk00, esk01) of prescaler mode register 0k (prm0k). the rising, falling, or both the rising and falling edges can be specified. when the valid edge of the ti0k0 pin is detected, the 16-bit timer/event counter is cleared and started, and the output becomes active at the count value set in advance to 16-bit timer capture/compare register 0k1 (cr0k1). after that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register 0k0 (cr0k0) note . note the case where n < m is described here. when n > m, the output becomes active with the cr0k0 register and inactive with the cr0k1 register. cautions 1. even if the external trigger is generated again while the one-shot pulse is output, it is ignored. 2. the value of the cr0k0 and cr0k1 registers cannot be changed during timer count operation. however, the cr0k1 register value can be changed in the ppg output mode. for details, refer to 7.4.2 ppg output operation. remark k = 4, 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 343 figure 7-25. control register settings for one-shot pulse output with external trigger (a) 16-bit timer mode control register 0k (tmc0k) 00001 tmc0k3 tmc0k tmc0k2 tmc0k1 ovf0k clears and starts at valid edge of ti0k0 pin 000 (b) capture/compare control register 0k (crc0k) 00000 crc0k crc0k2 crc0k1 crc0k0 cr0k0 used as compare register cr0k1 used as compare register 0 0/1 0 (c) 16-bit timer output control register 0k (toc0k) 00 1 1 0/1 toc0k lvr0k toc0k1 toe0k ospe0k ospt0k toc0k4 lvs0k enables to0k output inverts output upon match between tm0k and cr0k0 specifies initial value of to0k output f/f inverts output upon match between tm0k and cr0k1 sets one-shot pulse output mode 0/1 1 1 caution do not set the cr0k0 and cr0k1 registers to 0000h. remarks 1. 0/1: when these bits are reset to 0 or set to 1, other functions can be used together with the one- shot pulse output function. for details, refer to 7.3 (2) capture/compare control register 0n (crc0n) and 7.3 (3) 16-bit timer output control register 0n (toc0n) . 2. k = 4, 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 344 figure 7-26. timing of one-shot pulse output operation with external trigger (with rising edge specified) 0000h n nn n n mm m m m n + 1 n + 2 m + 1 m + 2 m ? 2m ? 1 0001h 0000h count clock tm0k count value cr0k1 set value cr0k0 set value ti0k0 pin input inttm0k1 inttm0k0 to0k pin output set tmc0k to 08h (tm0k count starts) caution 16-bit timer/event counter 0k starts operating as soon as a value other than 00 (operation stop mode) is set to the tmc0k2 and tmc0k3 bits. remark k = 4, 5 n < m chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 345 7.4.7 cautions (1) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because 16-bit timer counter 0n (tm0n) is started asynchronously to the count pulse. figure 7-27. start timing of 16-bit timer counter 0n 0000h timer start 0001h 0002h 0003h 0004h count pulse tm0n count value remark n = 0 to 5 (2) setting 16-bit timer capture/compare register (in the mode in which clear & start occurs upon match between tm0n register and cr0n0 register) set 16-bit timer capture/compare registers 0n0 and 0n1 (cr0n0 and cr0n1) to a value other than 0000h (when using these registers as event counters, one-pulse count operation is not possible). (3) data hold timing of capture register if the valid edge of the ti0n0 pin is input while 16-bit timer capture/compare register 0n1 (cr0n1) is read, the cr0n1 register performs capture operation, but the capture value at this time is not guaranteed. however, the interrupt request signal (inttm0n1) is generated as a result of detection of the valid edge. figure 7-28. data hold timing of capture register n n + 1 n + 2 x n+ 1 m m + 1 m + 2 count pulse tm0n count value edge input inttm0n1 cr0n1 interrupt value capture read signal capture operation is performed but not guaranteed capture operation remark n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 346 (4) setting valid edge before setting the valid edge of the ti0n0 pin, stop the timer operation by setting bits 2 and 3 (tmc0n2 and tmc0n3) of 16-bit timer mode control register 0n to 0, 0. set the valid edge by using bits 4 and 5 (esn00 and esn01) of prescaler mode register 0n (prm0n). (5) re-triggering one-shot pulse (tm00, tm01, tm04, tm05) (a) one-shot pulse output by software when a one-shot pulse is output, do not set the ospt0m bit to 1. do not output the one-shot pulse again until inttm0m0, which occurs upon match with the cr0m0 register, or inttm0m1, which occurs upon match with the cr0m1 register, occurs. remark m = 4, 5 (b) one-shot pulse output with external trigger if the external trigger occurs again while a one-shot pulse is output, it is ignored. (c) one-shot pulse output function when using the one-shot pulse output of timer 0 with a software trigger, do not change the level of the ti0m0 pin or its alternate function port pin. because the external trigger is effective even in this case, the timer is cleared and started even with the ti0m0 pin or its alternate function port pin level, resulting in the output of a pulse at an undesired timing. remark m = 4, 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 347 (6) operation of ovf0n flag (a) setting of ovf0n flag the ovf0n flag is set to 1 in the following case in addition to when the tm0n register overflows. select the mode in which clear & start occurs upon match between the tm0n register and the cr0n0 register. set the cr0n0 register to ffffh when the tm0n register is cleared from ffffh to 0000h upon match with the cr0n register figure 7-29. operation timing of ovf0n flag fffeh ffffh ffffh 0000h 0001h count pulse tm0n inttm0n0 ovf0n cr0n0 remark n = 0 to 5 (b) clearing of ovf0n flag after the tm0n register overflows, clearing ovf0n flag is invalid and set again even if the ovf0n flag is cleared before the next count clock is counted (before tm0n register becomes 0001h). remark n = 0 to 5 (7) conflict between read period and capture trigger input if the read period conflicts with the capture trigger input when 16-bit timer capture/compare registers 0n0 and 0n1 (cr0n0 and cr0n1) are being used as capture registers, the capture trigger input has priority and the read data of the cr0n0 and cr0n1 registers becomes undefined. remark n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 348 (8) timer operation (a) cr0n1 register capture even if 16-bit timer counter 0n (tm0n) is read, the read data cannot be captured into 16-bit timer capture/compare register 0n1 (cr0n1). (b) ti0n0, ti0n1 pin acknowledgement regardless of the cpu ? s operation mode, if the timer is stopped, signals input to the ti0n0 and ti0n1 pins are not acknowledged. (c) one-shot pulse output (16-bit timer/event counters 00, 01, 04, and 05 only) one-shot pulse output operates normally in either the free-running mode or the mode in which clear & start occurs on the valid edge of the ti0k0 pin. because no overflow occurs in the mode in which clear & start occurs upon match between the tm0m register and the cr0m0 register, one-shot pulse output is not possible. remark n = 0 to 5 m = 0, 1, 4, 5 k = 4, 5 (9) capture operation (a) if valid edge of ti0n0 is specified for count clock if the valid edge of ti0n0 is specified for the count clock, the capture register that specified ti0n0 as the trigger does not operate normally. (b) if both rising and falling edges are selected for valid edge of ti0n0 if both the rising and falling edges are selected for the valid edge of ti0n0, capture operation is not performed. (c) to ensure that signals from ti0n1 and ti0n0 are correctly captured for the capture trigger to capture the signals from ti0n1 and ti0n0 correctly, a pulse longer than two of the count clocks selected by prescaler mode register 0n (prm0n) is required. (d) interrupt request input although a capture operation is performed at the falling edge of the count clock, an interrupt request signal (inttm0n0, inttm0n1) is generated at the rising edge of the next count clock. remark n = 0 to 5 chapter 7 16-bit timer/event counters 00 to 05 user ? s manual u15862ej3v0ud 349 (10) compare operation (a) when overwriting cr0n1 register during timer operation in ppg output mode when overwriting 16-bit timer capture/compare register 0n1 (cr0n1) while the timer is operating, if the new value is close to and larger than the timer value, match interrupt request generation may not be performed normally. (b) when setting cr0n0, cr0n1 to compare mode when set to the compare mode, the cr0n0 and cr0n1 registers do not perform capture operation even if a capture trigger is input. caution the value of the cr0n0 register cannot be changed during timer operation. the value of the cr0n1 register cannot be changed during timer operation other than in the ppg output mode. to change the cr0n1 register in the ppg output mode, refer to 7.4.2 ppg output operation. remark n = 0 to 5 (11) edge detection (a) when ti0n0 pin or ti0n1 pin is high level immediately following system reset when the ti0n0 or ti0n1 pin is high level immediately after a system reset, if either the rising edge or both edges of the ti0n0 pin or ti0n1 pin is specified as the valid edge and 16-bit timer counter 0n (tm0n) operation is enabled, the immediately following rising edge is detected. care is therefore required when pulling up the ti0n0 pin or the ti0n1 pin. however, once the timer is stopped and the operation enabled again, the rising edge is not detected. (b) sampling clock for noise elimination the sampling clock for noise elimination differs depending on whether the valid edge of ti0n0 is used for the count clock or as a capture trigger. in the former case, sampling is performed using f xx /4, and in the latter case, sampling is performed using the count clock selected by prescaler mode register 0n (prm0n). the first capture operation does not start until the valid edges are sampled and two valid levels are detected, thus eliminating noise with a short pulse width. remarks 1. f xx : internal system clock frequency 2. n = 0 to 5 user?s manual u15862ej3v0ud 350 chapter 8 8-bit timer/event counters 50 and 51 two 8-bit timer/event counter 50 and 51 channels are incorporated in each product. product name v850es/kf1 v850es/kg1 v850es/kj1 number of channels 2 channels (tm50, tm51) 8.1 functions 8-bit timer/event counter 5n has the following two modes (n = 0, 1). ? mode using 8-bit timer/event counter alone (individual mode) ? mode using cascade connection (16-bit resolution: cascade connection mode) these two modes are described below. (1) mode using 8-bit timer/event counter alone (individual mode) 8-bit timer/event counter 5n operates as an 8-bit timer/event counter. the following functions can be used. ? interval timer ? external event counter ? square-wave output ? pwm output (2) mode using cascade connection (16-bit resolution: cascade connection mode) 8-bit timer/event counters 50 and 51 operate as a 16-bit timer/event counter by connecting the tm50 and tm51 registers in cascade. the following functions can be used. ? interval timer with 16-bit resolution ? external event counter with 16-bit resolution ? square-wave output with 16-bit resolution the block diagram of 8-bit timer/event counters 50 and 51 is shown next. chapter 8 8-bit timer/event counters 50 and 51 user?s manual u15862ej3v0ud 351 figure 8-1. block diagram of 8-bit timer/event counters 50 and 51 ovf ti5n 3 tcl5n2 tcl5n1 tcl5n0 tce5n tmc5n6 tmc5n4 lvs5n lvr5n tmc5n1 toe5n to5n inttm5n s r q inv s r q match clear count clock note selector internal bus internal bus 8-bit timer mode control register 5n (tmc5n) 8-bit timer compare register 5n (cr5n) 8-bit timer counter 5n (tm5n) selector invert level mask circuit timer clock selection register 5n (tcl5n) selector selector note the count clock is set by the tcl5n register. remarks 1. ? ? are signals that can be directly connected to ports. 2. n = 0 to 5. 8.2 configuration 8-bit timer/event counters 50 and 51 consist of the following hardware. table 8-1. configuration of 8-bit timer/event counters 50 and 51 item configuration timer registers 8-bit timer counters 50 and 51 (tm50, tm51) 16-bit timer counter 5 (tm5): only when using cascade connection registers 8-bit timer compare registers 50, 51 (cr50, cr51) 16-bit timer compare register 5 (cr5): only when using cascade connection timer output to50, to51 control registers note timer clock selection registers 50, 51 (tcl50, tcl51) timer clock selection register 5 (tcl5): only when using cascade connection 8-bit timer mode control registers 50, 51 (tmc50, tmc51) 16-bit timer mode control register 5 (tmc5): only when using cascade connection note when using the functions of the ti5n and to5n pins, refer to table 4-28 settings when port pins are used for alternate functions . chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 352 (1) 8-bit timer counters 50 and 51 (tm50, tm51) the tm5n register is an 8-bit read-only register that counts the count pulses. the counter is incremented in synchronization with the rising edge of the count clock. through cascade connection, the tm5n registers can be used as a 16-bit timer. when using the tm50 register and the tm51 register in cascade as a 16-bit timer, these registers can be read by a 16-bit memory manipulation instruction. however, because these registers are connected by an internal 8-bit bus, the tm50 register and tm51 register must be read divided into two times. therefore, read these registers twice and compare the values, taking into consideration that the reading occurs during a count change. in the following cases, the count value becomes 00h. ? reset input ? when the tce5n bit of 8-bit timer mode control register 5n (tmc5n) is cleared ? the tm5n register and cr5n register match in the mode in which clear & start occurs on a match between the tm5n register and 8-bit timer compare register 5n (cr5n) caution when connected in cascade, these registers become 00h even when the tce50 bit in the lowest timer (tm50) is cleared. remark n = 0, 1 (2) 8-bit timer compare registers 50 and 51 (cr50, cr51) the cr5n register can be read and written by an 8-bit memory manipulation instruction. in a mode other than the pwm mode, the value set to the cr5n register is always compared to the count value of 8-bit counter 5n (tm5n), and if the two values match, an interrupt request signal (inttm5n) is generated. in the pwm mode, tm5n register overflow causes the to5n pin output to change to the active level, and when the values of the tm5n register and the cr5n register match, the to5n pin output changes to the inactive level. the value of the cr5n register can be set in the range of 00h to ffh. when using the tm50 register and tm51 register in cascade as a 16-bit timer, the cr50 register and cr51 register operate as 16-bit timer compare register 5 (cr5). the counter value and register value are compared in 16-bit lengths, and if they match, an interrupt request (inttm50) is generated. cautions 1. in the mode in which clear & start occurs upon a match of the tm5n register and cr5n register (tmc5n6 =0), do not write a different value to the cr5n register during the count operation. 2. in the pwm mode, set the cr5n register rewrite interval to three or more count clocks (clock selected with timer clock selection register 5n (tcl5n)). 3. before changing the value of the cr5n register when using a cascade connection, be sure to stop the timer operation. remark n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 353 8.3 control registers the following two registers are used to control 8-bit timer/event counter 5n. ? timer clock selection register 5n (tcl5n) ? 8-bit timer mode control register 5n (tmc5n) remark to use the functions of the ti5n and to5n pins, refer to table 4-28 settings when port pins are used for alternate functions . (1) timer clock selection registers 50 and 51 (tcl50, tcl51) these registers set the count clock of 8-bit timer/event counter 5n and the valid edge of the ti5n pin input. the tcl5n register is set by an 8-bit memory manipulation instruction. reset input clears this register to 00h. falling edge of ti5n rising edge of ti5n f xx f xx /2 f xx /4 f xx /64 f xx /256 inttm010 count clock selection note tcl5n2 0 0 0 0 1 1 1 1 tcl5n1 0 0 1 1 0 0 1 1 tcl5n0 0 1 0 1 0 1 0 1 16 mhz 8 mhz ? ? 62.5 ns 125 ns 250 ns 4 s 16 s ? ? ? 125 ns 250 ns 0.5 s 8 s 32 s ? clock f xx 0 tcl5n (n = 0, 1) 0 0 0 0 tcl5n2 tcl5n1 tcl5n0 after reset: 00h r/w address: tcl50 fffff5c4h, tcl51 fffff5c5h 76 54 32 1 0 note when the internal clock is selected, set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 to 4.0 v: count clock 5 mhz caution before overwriting the tcl5n register with different data, stop the timer operation. remark when tm50 and tm51 are connected in cascade, the tcl51 register settings are invalid. chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 354 (2) 8-bit timer mode control registers 50 and 51 (tmc50, tmc51) the tmc5n register performs the following six settings. ? controls counting by 8-bit timer counters 50 and 51 (tm50, tm51) ? selects the operation mode of the tm50 and tm51 registers ? selects the individual mode or cascade connection mode ? sets the status of the timer output flip-flop ? controls the timer output flip-flop or selects the active level in the pwm (free-running) mode ? controls timer output the tmc50 and tmc51 registers are set by an 8-bit or 1-bit memory manipulation instruction. reset input clears these registers to 00h. chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 355 tce5n counting is disabled after the counter is cleared to 0 (counter disabled) start count operation tce5n 0 1 control of count operation of 8-bit timer/event counter 5n tmc5n (n = 0, 1) tmc5n6 0 tmc514 note lvs5n lvr5n tmc5n1 toe5n mode in which clear & start occurs on match between tm5n register and cr5n register pwm (free-running) mode tmc5n6 0 1 selection of operation mode of 8-bit timer/event counter 5n individual mode cascade connection mode (connected with tm50) tmc514 0 1 selection of individual mode or cascade connection mode for 8-bit timer/event counter 51 unchanged reset timer output f/f to 0 set timer output f/f to 1 setting prohibited lvs5n 0 0 1 1 setting of status of timer output f/f lvr5n 0 1 0 1 after reset: 00h r/w address: tmc51 fffff5c7h tmc50 fffff5c6h disable inversion operation enable inversion operation high active low active tmc5n1 0 1 other than pwm (free-running) mode (tmc5n6 = 0) controls timer f/f pwm (free-running) mode (tmc5n6 = 1) selects active level disable output (to5n pin is low level) enable output toe5n 0 1 timer output control <7> 6 5 4 3 2 1 <0> note bit 4 of the tmc50 register is fixed to 0. cautions 1. because the to51 and ti51 pins are alternate functions of the same pin, only one can be used at one time. 2. the lvs5n and lvr5n bit settings are valid in modes other than the pwm mode. 3. do not rewrite the tmc5n1 bit and toe5n bit at the same time. 4. when switching to the pwm mode, do not rewrite the tmc5n6 bit and the lvs5n and lvr5n bits at the same time. 5. before rewriting the tmc5n6 bit or tmc514 bit, stop the timer operation. remarks 1. in the pwm mode, the pwm output is set to the inactive level by tce5n = 0. 2. when the lvs5n and lvr5n bits are read, 0 is read. 3. the values of the tmc5n6, lvs5n, lvr5n, tmc5n1, and toe5n bits are reflected to the to5n output regardless of the tce5n value. chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 356 8.4 operation 8.4.1 operation as interval timer (8 bits) 8-bit timer/event counter 5n operates as an interval timer that repeatedly generates interrupts at the interval of the count value preset in 8-bit timer compare register 5n (cr5n). if the count value in 8-bit timer counter 5n (tm5n) matches the value set in the cr5n register, the value of the tm5n register is cleared to 0 and counting is continued, and at the same time, an interrupt request signal (inttm5n) is generated. setting method <1> set each register. ? tcl5n register: selects the count clock (t). ? cr5n register: compare value (n) ? tmc5n register: stops count operation and selects the mode in which clear & start occurs on a match between the tm5n register and cr5n register (tmc5n register = 0000xx00b, : don ? t care). <2> when the tce5n bit of the tmc5n register is set to 1, the count operation starts. <3> when the values of the tm5n register and cr5n register match, inttm5n is generated (tm5n register is cleared to 00h). <4> then, inttm5n is repeatedly generated at the same interval. to stop counting, set tce5n = 0. interval time = (n + 1) t: n = 00h to ffh caution during interval timer operation, do not rewrite the value of the cr5n register. remark n = 0, 1 figure 8-2. timing of interval timer operation (1/2) basic operation t interval time interval time 00h n 01h 01h 00h n n n n n n 01h 00h clear interrupt acknowledgment interrupt acknowledgment clear count clock tm5n count value cr5n tce5n inttm5n count start remark n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 357 figure 8-2. timing of interval timer operation (2/2) when cr5n register = 00h t interval time 00h 00h 00h 00h 00h count clock tm5n count value cr5n tce5n inttm5n remark n = 0, 1 when cr5n register = ffh t 01h 00h feh ffh 00h feh ffh 00h ffh ffh ffh count clock tm5n count value cr5n tce5n inttm5n interval time interrupt acknowledgment interrupt acknowledgment remark n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 358 8.4.2 operation as external event counter (8 bits) the external event counter counts the number of clock pulses input to the ti5n pin from an external source by using 8-bit timer counter 5n (tm5n). each time the valid edge specified by timer clock selection register 5n (tcl5n) is input to the ti5n pin, the tm5n register is incremented. either the rising edge or the falling edge can be specified as the valid edge. when the count value of the tm5n register matches the value of 8-bit timer compare register 5n (cr5n), the tm5n register is cleared to 0 and an interrupt request signal (inttm5n) is generated. setting method <1> set each register. ? tcl5n register: selects the ti5n input edge. falling edge of ti5n pin tlc5n = 00h rising edge of ti5n pin tcl5n = 01h ? cr5n register: compare value (n) ? tmc5n register: stops count operation, selects the mode in which clear & start occurs on a match between the tm5n register and cr5n register, disables timer output f/f inversion operation, and disables timer output. (tmc5n register = 0000xx00b, : don ? t care) <2> when the tce5n bit of the tmc5n register is set to 1, the counter counts the number of pulses input from ti5n. <3> when the values of the tm5n register and cr5n register match, inttm5n is generated (tm5n register is cleared to 00h). <4> then, inttm5n is generated each time the values of the tm5n register and cr5n register match. inttm5n is generated when the valid edge of ti5n is input n + 1 times: n = 00h to ffh caution during external event counter operation, do not rewrite the value of the cr5n register. remark n = 0, 1 figure 8-3. timing of external event counter operation (with rising edge specified) 00h 01h 02h 03h 04h 05h n ? 1n n 00h 01h 02h 03h ti5n cr5n inttm5n tce5n tm5n count value count start remark n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 359 8.4.3 square-wave output operation (8-bit resolution) a square wave with any frequency can be output at an interval specified by the value preset in 8-bit timer compare register 5n (cr5n). by setting the toe5n bit of 8-bit timer mode control register 5n (tmc5n) to 1, the output status of the to5n pin is inverted at an interval specified by the count value preset in the cr5n register. in this way, a square wave of any frequency can be output (duty = 50%) (n = 0, 1). setting method <1> set each register. ? tcl5n register: selects the count clock (t). ? cr5n register: compare value (n) ? tmc5n register: stops count operation, selects the mode in which clear & start occurs on a match between the tm5n register and cr5n register. lvs5n lvr5n timer output f/f status setting 1 0 high-level output 0 1 low-level output enables timer output f/f inversion operation, and enables timer output. (tmc5n register = 00001011b or 00000111b) <2> when the tce5n bit of the tmc5n register is set to 1, counting starts. <3> when the values of the tm5n register and cr5n register match, the timer output f/f is inverted. moreover, inttm5n is generated and the tm5n register is cleared to 00h. <4> then, the timer f/f is inverted during the same interval and a square wave is output from the to5n pin. frequency = : n = 00h to ffh caution do not rewrite the value of the cr5n register during square-wave output. 1/2t(n + 1) t(n + 1) chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 360 figure 8-4. timing of square-wave output operation t interval time interval time 00h n 01h 01h 00h n n n n n n 01h 00h clear interrupt acknowledgement interrupt acknowledgement clear count clock tm5n count value cr5n to5n tce5n inttm5n count start note the initial value of the to5n output can be set using the lvs5n and lvr5n bits of the tmc5n register. remark n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 361 8.4.4 8-bit pwm output operation by setting the tmc5n6 bit of 8-bit timer mode control register 5n (tmc5n) to 1, 8-bit timer/event counter 5n performs pwm output. pulses with a duty factor determined by the value set in 8-bit timer compare register 5n (cr5n) are output from the to5n pin. set the width of the active level of the pwm pulse in the cr5n register. the active level can be selected using the tmc5n1 bit of the tmc5n register. the count clock can be selected using timer clock selection register 5n (tcl5n). pwm output can be enabled/disabled by the toe5n bit of the tmc5n register. caution the cr5n register rewrite interval must be three or more operation clocks (set by the tcl5n register). (1) basic operation of pwm output setting method <1> set each register. ? tcl5n register: selects the count clock (t). ? cr5n register: compare value (n) ? tmc5n register: stops count operation, selects pwm mode, and leave timer output f/f unchanged. tmc5n1 active level selection 0 active-high 1active-low timer output enabled (tmc5n register = 01000001b or 01000011b) <2> when the tce5n bit of the tmc5n register is set to 1, counting starts. pwm output operation <1> when counting starts, pwm output (output from the to5n pin) outputs the inactive level until an overflow occurs. <2> when an overflow occurs, the active level set by setting method <1> is output. the active level is output until the value of the cr5n register and the count value of 8-bit timer counter 5n (tm5n) match. <3> when the value of the cr5n register and the count value match, the inactive level is output and continues to be output until an overflow occurs again. <4> then, steps <2> and <3> are repeated until counting is stopped. <5> when counting is stopped by setting tce5n to 0, pwm output becomes inactive. cycle = 2 8 t, active level width = nt, duty = n/2 8 : n = 00h to ffh remark n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 362 (a) basic operation of pwm output figure 8-5. timing of pwm output operation basic operation (active level = h) 00h n + 1 n n 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h active level inactive level active level count clock tm5n count value cr5n tce5n inttm5n to5n t when cr5n register = 00h 00h n + 1 n + 2 n 00h 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h inactive level inactive level count clock tm5n count value cr5n tce5n inttm5n to5n t when cr5n register = ffh 00h n + 1 n + 2 n ffh 00h m 00h ffh 01h 02h 01h 00h ffh 02h 01h inactive level inactive level inactive level active level active level count clock tm5n count value cr5n tce5n inttm5n to5n t remark n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 363 (b) operation based on cr5n register transitions figure 8-6. timing of operation based on cr5n register transitions when the value of the cr5n register changes from n to m before the rising edge of the ffh clock the value of the cr5n register is reloaded at the overflow that occurs immediately after. n n ? 1n ? 2 m n <1> cr5n transition (n m) m m ? 1m ? 2 m m ? 1m ? 2 ffh 02h 00h 01h ffh 02h 00h 01h count clock tm5n count value cr5n tce5n h inttm5n to5n <2> t when the value of the cr5n register changes from n to m after the rising edge of the ffh clock the value of the cr5n register is reloaded at the second overflow. n n ? 1n ? 2 n nn <1> cr5n transition (n m) m n ? 1n ? 2 m m ? 1m ? 2 ffh 03h 02h 00h 01h ffh 02h 00h 01h count clock tm5n count value cr5n tce5n h inttm5n to5n <2> t caution in the case of reload from the cr5n register between <1> and <2>, the value that is actually used differs (read value: m; actual value of cr5n register: n). remark n = 0, 1 chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 364 8.4.5 operation as interval timer (16 bits) the v850es/kf1, v850es/kg1, and v850es/kj1 are provided with a 16-bit register that can be used only during cascade connection. the 16-bit resolution timer/event counter mode is selected by setting the tmc514 bit of 8-bit timer mode control register 51 (tmc51) to 1. 8-bit timer/event counter 5n operates as an interval timer by repeatedly generating interrupts using the count value preset in 16-bit timer compare register 5 (cr5) as the interval. setting method <1> set each register. ? tcl50 register: selects the count clock (t) (the tcl51 register does not need to be set in cascade connection) ? cr50 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr51 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc50, tmc51 register: selects the mode in which clear & start occurs on a match between tm5 register and cr5 register ( : don ? t care) tmc50 register = 0000xx00b tmc51 register = 0001xx00b <2> set the tce51 bit of the tmc51 register to 1. then set the tce50 bit of the tmc50 register to 1 to start the count operation. <3> when the values of the tm5 register and cr5 register connected in cascade match, inttm50 is generated (the tm5 register is cleared to 0000h). <4> inttm50 is then generated repeatedly at the same interval. interval time = (n + 1) t: n = 0000h to ffffh cautions 1. to write using 8-bit access during cascade connection, set the tce51 bit to 1 at operation start and then set the tce50 bit to 1. when operation is stopped, set the tce50 bit to 0 and then set the tce51 bit to 0. 2. during cascade connection, ti50 input, to50 output, and inttm50 signal output are used while ti51 input, to51 output, and inttm51 signal output are not, so set bits lvs51, lvr51, tmc511, and toe51 to 0. 3. do not change the value of the cr5 register during timer operation. chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 365 figure 8-35 shows a timing example of the cascade connection mode with 16-bit resolution. figure 8-7. cascade connection mode with 16-bit resolution 00h n ? 1 01h 00h ffh 00h 01h ffh 00h ffh m ? 1 01h 00h 00h na 01h 00h 02h m 00h 00h b n n m interval time operation enabled, count start interrupt occurrence, level inverted, counter cleared operation stopped count clock tm50 count value tm51 count value tce51 inttm50 cr51 tce50 cr50 t chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 366 8.4.6 operation as external event counter (16 bits) the v850es/kf1, v850es/kg1, and v850es/kj1 are provided with a 16-bit register that can be used only during cascade connection. the 16-bit resolution timer/event counter mode is selected by setting the tmc514 bit of 8-bit timer mode control register 51 (tmc51) to 1. the external event counter counts the number of clock pulses input to the ti50 pin from an external source using 16-bit timer counter 5 (tm5). setting method <1> set each register. ? tcl50 register: selects the ti50 input edge. (the tcl51 register does not have to be set during cascade connection.) falling edge of ti50 tcl50 = 00h rising edge of ti50 tcl50 = 01h ? cr50 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr51 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc50, tmc51 registers: stops count operation, selects the clear & stop mode entered on a match between the tm5 register and cr5 register, disables timer output f/f inversion, and disables timer output. ( : don ? t care) tmc50 register = 0000xx00b tmc51 register = 0001xx00b <2> set the tce51 bit of the tmc51 register to 1. then set the tce50 bit of the tmc50 register to 1 and count the number of pulses input from ti50. <3> when the values of the tm5 register and cr5 register connected in cascade match, inttm50 is generated (the tm5 register is cleared to 0000h). <4> inttm50 is then generated each time the values of the tm5 register and cr5 register match. inttm50 is generated when the valid edge of ti50 is input n + 1 times: n = 0000h to ffffh cautions 1. during external event counter operation, do not rewrite the value of the cr5n register. 2. to write using 8-bit access during cascade connection, set the tce51 bit to 1 and then set the tce50 bit to 1. when operation is stopped, set the tce50 bit to 0 and then set the tce51 bit to 0 (n = 0, 1). 3. during cascade connection, ti50 input and inttm50 signal output are used while ti51 input, to51 output, and inttm51 signal output are not, so set bits lvs51, lvr51, tmc511, and toe51 to 0. 4. do not change the value of the cr5 register during external counter operation. chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 367 8.4.7 square-wave output operation (16-bit resolution) the v850es/kf1, v850es/kg1, and v850es/kj1 are provided with a 16-bit register that can be used only during cascade connection. the 16-bit resolution timer/event counter mode is selected by setting the tmc514 bit of 8-bit timer mode control register 51 (tmc51) to 1. 8-bit timer/event counter 5n outputs a square wave of any frequency using the interval preset in 16-bit timer compare register 5 (cr5). setting method <1> set each register. ? tcl50 register: tcl50 selects the count clock (t) (the tcl51 register does not have to be set in cascade connection) ? cr50 register: compare value (n) ... lower 8 bits (settable from 00h to ffh) ? cr51 register: compare value (n) ... higher 8 bits (settable from 00h to ffh) ? tmc50, tcm51 registers: stops count operation, selects the mode in which clear & start occurs on a match between the tm5 register and cr5 register. lvs50 lvr50 timer output f/f status settings 1 0 high-level output 0 1 low-level output enables timer output f/f inversion, and enables timer output. tmc50 register = 00001011b or 00000111b tmc51 register = 00010000b <2> set the tce51 bit of the tmc51 register to 1. then set the tce50 bit of the tmc50 register to 1 to start the count operation. <3> when the values of the tm5 register and the cr5 register connected in cascade match, the to50 timer output f/f is inverted. moreover, inttm50 is generated and the tm5 register is cleared to 0000h. <4> then, the timer f/f is inverted during the same interval and a square wave is output from the to50 pin. frequency = 1/2t(n + 1): n = 0000h to ffffh chapter 8 8-bit timer/event counters 50 and 51 user ? s manual u15862ej3v0ud 368 8.4.8 cautions (1) error on starting timer an error of up to 1 clock occurs before the match signal is generated after the timer has been started. this is because 8-bit timer counter 5n (tm5n) is started asynchronously to the count pulse. figure 8-8. start timing of timer 5n 00h timer start 01h 02h 03h 04h count pulse tm5n count value remark n = 0, 1 user?s manual u15862ej3v0ud 369 chapter 9 8-bit timers h0 and h1 two 8-bit timer h0 and h1 channels are incorporated in each product. product name v850es/kf1 v850es/kg1 v850es/kj1 number of channels 2 channels (tmh0, tmh1) 9.1 functions 8-bit timers h0 and h1 have the following functions. ? interval timer with 8-bit accuracy ? pwm pulse generator mode with 8-bit accuracy ? carrier generator mode with 8-bit accuracy 9.2 configuration 8-bit timers h0 and h1 consist of the following hardware. table 9-1. configuration of 8-bit timers h0 and h1 item configuration timer registers 8-bit timer counter hn: 1 each register 8-bit timer h compare register n0 (cmpn0): 1 each 8-bit timer h compare register n1 (cmpn1): 1 each timer outputs 1 each (tohn) control registers note 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register n (tmcycn) note to use the tohn pin function, refer to table 4-28 settings when port pins are used for alternate functions . remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user?s manual u15862ej3v0ud 370 figure 9-1 shows the block diagram. figure 9-1. block diagram of 8-bit timers h0 and h1 match selector internal bus tmhen ckshn2 ckshn1 ckshn0 tmmdn1tmmdn0 tolevn toenn decoder 8-bit timer h compare register n0 (cmpn0) reload/ interrupt control tohn inttmhn inttm5n selector rmc n nrzb n f xx f xx /2 f xx /2 2 f xx /2 4 f xx /2 6 f xx /2 10 f xt interrupt generator output controller level inversion nrz n 1 0 f/f r 8-bit timer counter hn carrier generator mode signal pwm mode signal timer h enable signal clear 3 2 8-bit timer h compare register n1 (cmpn1) 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register n (tmcycn) remarks 1. ? ? indicates a signal that can be directly connected to a port. 2. n = 0, 1 chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 371 (1) 8-bit timer h compare register n0 (cmpn0) the cmpn0 register can be read and written by an 8-bit memory manipulation instruction. reset input clears cmpn0 to 00h. cmpn0 after reset: 00h r/w address: fffff582h, fffff592h 76 54 32 1 0 caution rewriting the cmpn0 register during timer count operation is prohibited. remark n = 0, 1 (2) 8-bit timer h compare register n1 (cmpn1) the cpmn1 register can be read and written by an 8-bit memory manipulation instruction. reset input clears cmpn1 to 00h. cmpn1 after reset: 00h r/w address: fffff583h, fffff593h 76 54 32 1 0 the cmpn1 register can be rewritten during timer count operation. after the cmpn1 register is set, if the count value of 8-bit timer counter hn and the value of the cmpn1 register match, an interrupt request signal (inttmhn) is generated. at the same time, the value of 8-bit timer counter hn is cleared to 00h. if the value of the cmpn1 register is rewritten during timer operation, the reload timing is when the count value of 8-bit timer counter hn and the value of the cmpn1 register match. if the transfer timing and write to the cmpn1 register from the cpu conflict, transfer is not performed. caution in the pwm pulse generator mode and carrier generator mode, be sure to set the cmpn1 register when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to the cmpn1 register). chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 372 9.3 control registers the registers that control 8-bit timers h0 and h1 are as follows. ? 8-bit timer h mode register n (tmhmdn) ? 8-bit timer h carrier control register n (tmcycn) remarks 1. to use the tohn pin function, refer to table 4-28 settings when port pins are used for alternate functions . 2. n = 0, 1 (1) 8-bit timer h mode registers 0 and 1 (tmhmd0, tmhmd1) these registers control the mode of the 8-bit timers h0 and h1. tmhmd0 and tmhmd1 registers are set by an 8-bit or 1-bit memory manipulation instruction. reset input clears tmhmd0 and tmhmd1 to 00h. chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 373 (a) 8-bit timer h mode register 0 (tmhmd0) tmhe0 stop timer count operation (8-bit timer counter h0 = 00h) enable timer count operation (counting starts when clock is input) tmhe0 0 1 8-bit timer h0 operation enable tmhmd0 cksh02 cksh01 cksh00 tmmd01 tmmd00 tolev0 toen0 after reset: 00h r/w address: fffff580h f xx f xx /2 f xx /4 f xx /16 f xx /64 f xx /1024 cksh02 0 0 0 0 1 1 cksh01 0 0 1 1 0 0 cksh00 0 1 0 1 0 1 62.5 ns 125 ns 250 ns 1 s 4 s 64 s selection of count clock count clock note interval timer mode carrier generator mode pwm pulse generator mode setting prohibited tmmd01 0 0 1 1 tmmd00 0 1 0 1 8-bit timer h0 operation mode other than above low level high level tolev0 0 1 timer output level control (default) disable output enable output toen0 0 1 timer output control f xx = 16.0 mhz <7> 6 5 4 3 2 1 <0> setting prohibited note set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 v to 4.0 v: count clock 5 mhz cautions 1. when tmhe0 = 1, setting bits other than those of the tmhmd0 register is prohibited. 2. in the pwm pulse generator mode and carrier generator mode, be sure to set 8-bit timer h compare register 01 (cmp01) when starting the timer count operation (tmhe0 = 1) after the timer count operation was stopped (tmhe0 = 0) (be sure to set again even if setting the same value to the cmp01 register). 3. when using the carrier generator mode, set the tmh0 count clock frequency to six times the tm50 count clock frequency or higher. chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 374 (b) 8-bit timer h mode register 1 (tmhmd1) tmhe1 stop timer count operation (8-bit timer counter h1 = 00h) enable timer count operation (counting starts when clock is input) tmhe1 0 1 8-bit timer h1 operation enable tmhmd1 cksh12 cksh11 cksh10 tmmd11 tmmd10 tolev1 toen1 after reset: 00h r/w address: fffff590h f xx f xx /2 f xx /4 f xx /16 f xx /64 cksh12 0 0 0 0 1 1 cksh11 0 0 1 1 0 0 cksh10 0 1 0 1 0 1 62.5 ns 125 ns 250 ns 1 s 4 s selection of count clock count clock note interval timer mode carrier generator mode pwm pulse generator mode setting prohibited tmmd11 0 0 1 1 tmmd10 0 1 0 1 8-bit timer h1 operation mode f xt (subclock) setting prohibited other than above low level high level tolev1 0 1 timer output level control (default) disable output enable output toen1 0 1 timer output control f xx = 16.0 mhz <7> 6 5 4 3 2 1 <0> note set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: count clock 10 mhz v dd = 2.7 v to 4.0 v: count clock 5 mhz cautions 1. when tmhe1 = 1, setting bits other than those of the tmhmd1 register is prohibited. 2. in the pwm pulse generator mode and carrier generator mode, be sure to set 8-bit timer h compare register 11 (cmp11) when starting timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to the cmp11 register). 3. when using the carrier generator mode, set the tmh1 count clock frequency to six times the tm51 count clock frequency or higher. chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 375 (2) 8-bit timer h carrier control register n (tmcycn) this register controls the 8-bit timer hn remote control output and carrier pulse output status. tmcycn register is set by an 8- bit or 1-bit memory manipulation instruction. the nrzn bit is a read-only bit. reset input clears tmcycn to 00h. remark n = 0, 1 0 tmcycn 0 0 0 0 rmcn nrzbn nrzn after reset: 00h r/w address: fffff581h, fffff591h low level output high level output low level output carrier pulse output rmcn 0 0 1 1 nrzbn 0 1 0 1 remote control output carrier output disabled status (low level status) carrier output enable status nrzn 0 1 carrier pulse output status flag (n = 0, 1) 76 54 32 1 0 chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 376 9.4 operation 8-bit timers h0 and h1 can operate in the following three modes. ? interval timer mode ? carrier generator mode ? pwm pulse generator mode caution rewriting the values of 8-bit timer h compare registers 00 and 10 (cmp00 and cmp10) while 8-bit timers h0 and h1 are operating is prohibited. 9.4.1 operation as interval timer when the count value of 8-bit timer counter hn and the value of 8-bit timer h compare register n0 (cmpn0) match, an interrupt request signal (inttmhn) is generated and 8-bit timer counter hn is cleared to 00h. 8-bit timer h compare register n1 (cmpn1) cannot be used in the interval timer mode. even if the cmpn1 register is set, this has no effect on the timer output because matches between 8-bit timer counter hn and the cmpn1 register are not detected. (1) usage method the inttmhn signal is repeatedly generated in the same interval. <1> set each register. figure 9-2. register settings in interval timer mode (i) 8-bit timer h mode register n (tmhmdn) settings 0 0/1 0/1 0/1 0 sets timer output sets timer output level inversion sets interval timer mode selects count clock (f cnt ) stops count operation 0 0/1 0/1 tmmdn0 tolevn toenn ckshn1 ckshn2 tmhen tmhmdn ckshn0 tmmdn1 (ii) cmpn0 register settings ? compare value (n) <2> when tmhen = 1 is set, counting starts. chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 377 <3> when the count value of 8-bit timer counter hn and the value of the cmpn0 register match, the inttmhn signal is generated and 8-bit timer counter hn is cleared to 00h. interval time = (n + 1)/f cnt <4> then, the inttmhn signal is generated in the same interval. to stop the count operation, set the tmhen bit to 0. (2) timing chart the timing in the interval timer mode is as follows. figure 9-3. timing of interval timer operation (1/2) basic operation 00h count clock count start 8-bit timer counter hn count value cmpn0 tmhen inttmhn tohn 01h n clear clear n 00h 01h n 00h 01h 00h <1> <2> level inversion, match interrupt occurrence, 8-bit timer counter clear <2> level inversion, match interrupt occurrence, 8-bit timer counter clear <3> interval time <1> when tmhen = 1 is set, counting starts. <2> when the count value of 8-bit timer counter hn and the value of the cmpn0 register match, the value of 8-bit timer counter hn is cleared, the tohn output level is inverted, and the inttmhn signal is output. <3> the inttmhn signal and tohn output become inactive when the tmhen bit is set to 0 during 8-bit timer hn operation. if the level is already inactive, it remains unchanged. remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 378 figure 9-3. timing of interval timer operation (2/2) operation when cmpn0 = ffh 00h count clock count start cmpn0 tmhen inttmhn tohn 01h feh clear clear ffh 00h feh ffh 00h ffh interval time 8-bit timer counter hn count value operation when cmpn0 = 00h count clock count start cmpn0 tmhen inttmhn tohn 00h 00h interval time 8-bit timer counter hn count value remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 379 9.4.2 pwm pulse generator mode operation in the pwm mode, a pulse of any duty and cycle can be output. 8-bit timer h compare register n0 (cmpn0) controls the timer output (tohn) cycle. rewriting the cmpn0 register during timer operation is prohibited. 8-bit timer h compare register n1 (cmpn1) controls the timer output (tohn) duty. the cmpn1 register can be rewritten during timer operation. the operation in the pwm mode is as follows. after timer counting starts, when the count value of 8-bit timer counter hn and the value of the cmpn0 register match, the tohn output becomes active and 8-bit timer counter hn is cleared to 00h. when the count value of 8-bit timer counter hn and the cmpn1 register match, tohn output becomes inactive. (1) usage method in the pwm mode, a pulse of any duty and cycle can be output. <1> set each register. figure 9-4. register settings in pwm pulse generator mode (i) 8-bit timer h mode register n (tmhmdn) settings 0 0/1 0/1 0/1 1 enables timer output sets timer output level inversion selects pwm mode selects count clock (f cnt ) stops count operation 0 0/1 1 tmmdn0 tolevn toenn ckshn1 ckshn2 tmhen tmhmdn ckshn0 tmmdn1 (ii) cmpn0 register setting ? compare value (n): sets cycle (ii) cmpn1 register setting ? compare value (n): sets duty remarks 1. n = 0, 1 2. 00h cmpn1 (m) < cmpn0 (n) ffh <2> when tmhen = 1 is set, counting starts. chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 380 <3> after the count operation is enabled, the first compare register to be compared is the cmpn0 register. when the count value of 8-bit timer counter hn and the value of the cmpn0 register match, 8-bit timer counter hn is cleared, an interrupt request signal (inttmhn) is generated, and the tohn output becomes active. at the same time, the register that is compared with 8-bit timer counter hn changes from the cmpn0 register to the cmpn1 register. <4> when the count value of 8-bit timer counter hn and the value of the cmpn1 register match, the tohn output becomes inactive, and at the same time the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. at this time, 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <5> a pulse of any duty ratio can be obtained through the repetition of steps <3> and <4> above. <6> to stop the count operation, set tmhen = 0. designating the setting value of the cmpn0 register as (n), the setting value of the cmpn1 register as (m), and the count clock frequency as f cnt , the pwm pulse output cycle and duty ratio are as follows. pwm pulse output cycle = (n + 1)/f cnt duty ratio = inactive width: active width = (m + 1) : (n ? m) cautions 1. in the pwm mode, three operating clocks (signal selected by ckshn0 to ckshn2 bits of tmhmdn register) are required for actual transfer of the new value to the register after the cmpn1 register has been rewritten. 2. be sure to set the cmpn1 register when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to the cmpn1 register). chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 381 (2) timing chart the operation timing in the pwm mode is as follows. caution the setting value (m) of the cmpn1 register and the setting value (n) of the cmpn0 register must always be set within the following range. 00h cmpn1 (m) < cmpn0 (n) ffh figure 9-5. operation timing in pwm pulse generator mode (1/4) basic operation count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) tohn (tolevn = 1) 00h 01h a5h 00h 01h 02h a5h 00h a5h 00h 01h 02h <1> <3> <2> cmpn1 <4> a5h 01h 8-bit timer counter hn count value <1> when tmhen = 1 is set, counting starts. at this time tohn output stays inactive (tolevn = 0). <2> when the count value of 8-bit timer counter hn and the value of the cmpn0 register match, the tohn output level is inverted, 8-bit timer counter hn is cleared, and the inttmhn signal is output. <3> when the count value of 8-bit timer counter hn and the value of the cmpn1 register match, the tohn output level is returned to its former level. at this time, the value of 8-bit timer counter hn is not cleared and the inttmhn signal is not output. <4> when the tmhen bit is set to 0 during 8-bit timer hn operation, the inttmhn signal and tohn output becomes inactive. remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 382 figure 9-5. operation timing in pwm pulse generator mode (2/4) operation when cmpn0 = ffh, cmpn1 = 00h count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmpn1 ffh 00h 8-bit timer counter hn count value operation when cmpn0 = ffh, cmpn1 = feh count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmpn1 ffh feh 8-bit timer counter hn count value remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 383 figure 9-5. operation timing in pwm pulse generator mode (3/4) operation when cmpn0 = 01h, cmpn1 = 00h count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmpn1 00h 8-bit timer counter hn count value remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 384 figure 9-5. operation timing in pwm pulse generator mode (4/4) operation based on cmpn1 transitions (cmpn1 = 01h 03h, cmpn0 = a5h) count clock cmpn0 tmhen inttmhn tohn (tolevn = 0) 00h 01h 02h a5h 00h 01h 02h 03h a5h 00h 01h 02h 03h a5h 00h <1> <4> <3> <2> cmpn1 <6> <5> 01h a5h 03h 01h (03h) <2>' 8-bit timer counter hn count value <1> when tmhen = 1 is set, counting starts. at this time, the tohn output remains inactive (tolevn = 0). <2> the setting value of the cmpn1 register can be changed during count operation. this operation is asynchronous to the count clock. <3> when the count value of 8-bit timer counter hn and the value of the cmpn0 register match, 8-bit timer counter hn is cleared, the tohn output becomes active, and the inttmhn signal is generated. <4> even if the value of the cmpn1 register is changed, that value is latched and not transferred to the register. when the count value of 8-bit timer counter hn and the value of the cmpn1 register prior to the change match, the changed value is transferred to the cmpn1 register and the value of the cmpn1 register is changed (<2>'). however, three or more count clocks are required from the time the value of the cmpn1 register is changed until it is transferred to the register. even if a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> when the count value of 8-bit timer counter hn matches the changed value of the cmpn1 register, the tohn output becomes inactive. 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <6> when the tmhen bit is set to 0 during 8-bit timer hn operation, the inttmhn signal and tohn output become inactive. chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 385 9.4.3 carrier generator mode operation the carrier clock generated by 8-bit timer hn is output using the cycle set with 8-bit timer/event counter 5n. in the carrier generator mode, 8-bit timer/event counter 5n is used to control the extent to which the carrier pulse of 8-bit timer hn is output, and the carrier pulse is output from the tohn output. in the carrier generator mode, the connection diagram of 8-bit timer hn and 8-bit timer/event counter 5n is as follows. figure 9-6. connection example of 8-bit timer hn and 8-bit timer/event counter 5n 8-bit timer/event counter 5n prescaler cpu intc inttm5n inttm5n inttm5hn inttmhn 8-bit timer hn to5n tohn selector tmmdn0, tmmdn1 remark n = 0, 1 (1) carrier generation in the carrier generator mode, 8-bit timer h compare register n0 (cmpn0) generates a waveform with the low- level width of the carrier pulse and 8-bit timer h compare register n1 (cmpn1) generates a waveform with the high-level width of the carrier pulse. during 8-bit timer hn operation, the cmpn1 register can be rewritten, but rewriting of the cmpn0 register is prohibited. (2) carrier output control carrier output control is performed with the interrupt request signal (inttm5n) of 8-bit timer/event counter 5n and the nrzn and rmcn bits of 8-bit timer h carrier control register (tmcycn). the output relationships are as follows. rmcn bit nrzn bit output 0 0 low level output 0 1 high level output 1 0 low level output 1 1 carrier pulse output remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 386 to control carrier pulse output during count operation, the nrzn and nrzbn bits of the tmcycn register have a master and slave bit configuration. the nrzn bit is read-only while the nrzbn bit can be read and written. the inttm5n signal is synchronized with the 8-bit timer hn clock and output as the inttm5hn signal. the inttm5hn signal becomes the data transfer signal of the nrzn bit and the value of the nrzbn bit is transferred to the nrzn bit. the transfer timing from the nrzbn bit to the nrzn bit is as follows. figure 9-7. transfer timing 8-bit timer hn count clock tmhen inttm5n inttm5hn nrzn nrzbn rmcn 1 1 1 0 00 <1> <2> <1> the inttm5n signal is synchronized with the count clock of 8-bit timer hn and is output as the inttm5hn signal. <2> the value of the nrzbn bit is transferred to the nrzn bit at the second clock from the rising edge of the inttm5hn signal. cautions 1. do not rewrite the nrzbn bit again until at least the second clock after it has been rewritten, or else transfer from the nrzbn bit to the nrzn bit is not guaranteed. 2. when using 8-bit timer/event counter 5n in the carrier generator mode, an interrupt occurs at the timing of <1>. an interrupt occurs at a different timing when it is used in other than the carrier generator mode. remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 387 (3) usage method any carrier clock can be output from the tohn pin. <1> set each register. figure 9-8. register settings in carrier generator mode ? 8-bit timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 0 enables timer output sets timer output level inversion selects carrier generator mode selects count clock (f cnt ) stops count operation 1 0/1 0/1 tmmdn0 tolevn toenn ckshn1 ckshn2 tmhen tmhmdn ckshn0 tmmdn1 ? cmpn0 register: compare value ? cmpn1 register: compare value ? tmcycn register: rmcn = 1 ... remote control output enable bit nrzbn = 0/1 ... carrier output enable bit ? tcl5n, tmc5n registers: refer to 8.3 control registers . remark n = 0, 1 <2> when tmhen = 1 is set, 8-bit timer hn count operation starts. <3> when the tce5n bit of 8-bit timer mode control register 5n (tmc5n) is set to 1, 8-bit timer/event counter 5n count operation starts. <4> after the count operation is enabled, the first compare register to be compared is the cmpn0 register. when the count value of 8-bit timer counter hn and the value of the cmpn0 register match, the inttmhn signal is generated, 8-bit timer counter hn is cleared, and at the same time, the register that is compared with 8-bit timer counter hn changes from the cmpn0 register to the cmpn1 register. <5> when the count value of 8-bit timer counter hn and the value of the cmpn1 register match, the inttmhn signal is generated, 8-bit timer counter hn is cleared, and at the same time, the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. <6> the carrier clock is obtained through the repetition of steps <4> and <5> above. <7> the inttm5n signal is synchronized with 8-bit timer hn and output as the inttm5hn signal. this signal becomes the data transfer signal of the nrzbn bit and the value of the nrzbn bit is transferred to the nrzn bit. <8> when the nrzn bit becomes high level, the carrier clock is output from the tohn pin. <9> any carrier clock can be obtained through the repetition of the above steps. to stop the count operation, set tmhen = 0. chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 388 designating the setting value of the cmpn0 register as (n), the setting value of the cmpn1 register as (m), and the count clock frequency as f cnt , the carrier clock output cycle and duty ratio are as follows. carrier clock output cycle = (n + m + 2)/f cnt duty ratio = high level width: low level width = (m + 1) : (n + 1) caution be sure to set the cmpn1 register when starting the timer count operation (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to the cmpn1 register). (4) timing chart the carrier output control timing is as follows. cautions 1. set the values of the cmpn0 and cmpn1 registers in the range of 01h to ffh. 2. in the carrier generator mode, three operating clocks (signal selected by ckshn0 to ckshn2 bits of tmhmdn register) are required for actual transfer of the new value to the register after the cmpn1 register has been rewritten. 3. be sure to perform the rmcn bit setting before the start of the count operation. 4. when using the carrier generator mode, set the tmhn count clock frequency to six times the tm5n count clock frequency or higher. chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 389 figure 9-9. carrier generator mode (1/3) operation when cmpn0 = n, cmpn1 = n is set cmpn0 cmpn1 tmhen inttmhn carrier clock 00h n 00h n 00h n 00h n 00h n 00h n n n 8-bit timer 5n count clock tm5n count value cr5n tce5n tohn 0 0 1 1 0 0 1 1 0 0 inttm5n nrzbn nrzn carrier clock 00h 01h l 00h 01h l 00h 01h l 00h 01h 00h 01h l l <1> <2> <3> <4> <5> <6> <7> 8-bit timer hn count clock 8-bit timer counter hn count value <1> when tmhen = 0 and tce5n = 0, the operation of 8-bit timer hn is stopped. <2> when tmhen = 1 is set, 8-bit timer hn starts counting. the carrier clock is maintained inactive at this time. <3> when the count value of 8-bit timer counter hn and the value of the cmpn0 register match, the first inttmhn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer counter hn changes from the cmpn0 register to the cmpn1 register. 8-bit timer counter hn is cleared to 00h. <4> when the count value of 8-bit timer counter hn and the value of the cmpn1 register match, the inttmhn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. 8-bit timer counter hn is cleared to 00h. a carrier clock with a duty ratio of 50% is generated through the repetition of steps <3> and <4>. <5> when the inttm5n signal is generated, this signal is synchronized with 8-bit timer hn and output as the inttm5hn signal. <6> the inttm5hn signal becomes the data transfer signal of the nrzbn bit, and the value of the nrzbn bit is transferred to the nrzn bit. <7> the tohn output is made low level by setting nrzn = 0. remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 390 figure 9-9. carrier generator mode (2/3) operation when cmpn0 = n, cmpn1 = m is set (operation with carrier clock phase asynchronous to nrzn phase) n l cmpn0 cmpn1 tmhen inttmhn carrier clock tm5n count value 00h n 00h 01h m 00h n 00h 01h m 00h 00h n m cr5n tce5n tohn 0 0 1 1 0 0 1 1 0 0 inttm5n nrzbn nrzn carrier clock 00h 01h l 00h 01h l 00h 01h l 00h 01h 00h 01h l <1> <2> <3> <4> <5> <6> <7> 8-bit timer 5n count clock 8-bit timer hn count clock 8-bit timer counter hn count value <1> when tmhen = 0 and tce5n = 0, the operation of 8-bit timer hn is stopped. <2> when tmhen = 1 is set, 8-bit timer hn starts counting. the carrier clock is maintained inactive at this time. <3> when the count value of 8-bit timer counter hn and the value of the cmpn0 register match, the first inttmhn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer counter hn changes from the cmpn0 register to the cmpn1 register. 8-bit timer counter hn is cleared to 00h. <4> when the count value of 8-bit timer counter hn and the value of the cmpn1 register match, the inttmhn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer counter hn changes from the cmpn1 register to the cmpn0 register. 8-bit timer counter hn is cleared to 00h. a carrier clock with a fixed duty ratio (other than 50%) is generated through the repetition of steps <3> and <4>. <5> the inttm5n signal is generated. this signal is synchronized with 8-bit timer hn and output as the inttm5hn signal. <6> when the carrier clock phase becomes asynchronous to the phase of the nrzn bit, the carrier is output from the rising edge of the first carrier clock by setting nrzn = 1. <7> by setting nrzn = 0, the tohn output is also maintained high level while the carrier clock is high level, and does not change to low level (the high level width of the carrier waveform is guaranteed through steps <6> and <7>). remark n = 0, 1 chapter 9 8-bit timers h0 and h1 user ? s manual u15862ej3v0ud 391 figure 9-9. carrier generator mode (3/3) operation based on cmpn1 transitions 8-bit timer hn count clock cmpn0 tmhen inttmhn carrier clock 00h 01h n 00h 01h 01h m 00h n 00h l 00h <1> <3>' <4> <3> <2> cmpn1 <5> m n l m (l) 8-bit timer counter hn count value <1> when tmhen = 1 is set, counting starts. the carrier clock is maintained inactive at this time. <2> when the count value of 8-bit timer counter hn and the value of the cmpn0 register match, 8-bit timer counter hn is cleared and the inttmhn signal is output. <3> the cmpn1 register can be rewritten during 8-bit timer hn operation, but the changed value (l) is latched. the value of the cmpn1 register is changed when the count value of 8-bit timer counter hn and the value of the cmpn1 register prior to the change (m) match (<3>'). <4> when the count value of 8-bit timer counter hn and the value (m) of the cmpn1 register match, the inttmhn signal is output, the carrier signal is inverted, and 8-bit timer counter hn is cleared to 00h. <5> the timing at which the count value of 8-bit timer counter hn and the value of the cmpn1 register match again is the changed value (l). remark n = 0, 1 user?s manual u15862ej3v0ud 392 chapter 10 real-time output function (rto) 10.1 function the real-time output function (rto) transfers preset data to real-time output buffer registers n (rtbln, rtbhn), and then transfers this data with hardware to an external device via the real-time output latches, upon occurrence of an external interrupt or external trigger. the pins through which the data is output to an external device constitute a port called a real-time output port. because rto can output signal without jitter, it is suitable for controlling a stepping motor. in the v850es/kf1 and v850es/kg1, one 6-bit real-time output port channel is provided. in the v850es/kj1, two 6-bit real-time output port channels are provided. the real-time output port can be set in the port mode or real-time output port mode in 1-bit units. the block diagram of rto is shown below. figure 10-1. block diagram of rto real-time buffer register nh (rtbhn) real-time output latch nh selector inttm000 (inttm020 note ) inttm50 inttm51 real-time output latch nl rtpoen rtpegn byten extrn real-time output port control register n (rtpcn) transfer trigger (h) transfer trigger (l) rtpmn5 rtpmn4 rtpmn3 rtpmn2 rtpmn1 rtpmn0 real-time output port mode register n (rtpmn) 4 2 2 4 internal bus real-time buffer register nl (rtbln) rtpoutn4, rtpoutn5 rtpoutn0 to rtpoutn3 note when n = 0, inttm000 when n = 1, inttm020 chapter 10 real-time output function (rto) user ? s manual u15862ej3v0ud 393 10.2 configuration rto consists of the following hardware. table 10-1. configuration of rto item configuration registers real-time output buffer register n (rtbln, rtbhn) control registers real-time output port mode register n (rtpmn) real-time output port control register n (rtpcn) (1) real-time output buffer register n (rtbln, rtbhn) rtbln and rtbhn are 4-bit registers that hold output data in advance. these registers are mapped to independent addresses in the peripheral i/o register area. they can be read/written in 8-bit or 1-bit units. if an operation mode of 4 bits 2 channels is specified (byten = 0), data can be individually set to the rtbln and rtbhn registers. the data of both these registers can be read at once by specifying the address of either of these registers. if an operation mode of 6 bits 1 channel is specified (byten = 1), 8-bit data can be set to both the rtbln and rtbhn registers by writing the data to either of these registers. moreover, the data of both these registers can be read at once by specifying the address of either of these registers. table 10-2 shows the operation when the rtbln and rtbhn registers are manipulated. 0 rtbln rtbhn 0 rtbhn5 rtbhn4 rtbln3 rtbln2 rtbln1 rtbln0 after reset : 00h r/w address : rtbln : rtbhn : fffff6e0h, fffff6f0 fffff6e2h, fffff6f2 caution when writing to bits 6 and 7 of the rtbhn register, always write 0. remark n = 0, 1 n = 1 only for the v850es/kj1. table 10-2. operation during manipulation of real-time output buffer registers n read write note operation mode register to be manipulated higher 4 bits lower 4 bits higher 4 bits lower 4 bits rtbln rtbhn rtbln invalid rtbln 4 bits 1 channel, 2 bits 1 channel rtbhn rtbhn rtbln rtbhn invalid rtbln rtbhn rtbln rtbhn rtbln 6 bits 1 channel rtbhn rtbhn rtbln rtbhn rtbln note after setting the real-time output port, set output data to the rtbln and rtbhn registers by the time a real- time output trigger is generated. chapter 10 real-time output function (rto) user ? s manual u15862ej3v0ud 394 10.3 rto control registers rto is controlled using the following two types of registers. ? real-time output port mode register n (rtpmn) ? real-time output port control register n (rtpcn) (1) real-time output port mode register n (rtpmn) this register selects the real-time output port mode or port mode in 1-bit units. the rtpmn register is set by an 8-bit or 1-bit memory manipulation instruction. reset input clears rtpmn to 00h. 0 rtpmn 0 1 port mode real-time output port mode selection of real-time output port (n = 0 to 5) rtpmn (n = 0, 1) 0 rtpmn5 rtpmn4 rtpmn3 rtpmn2 rtpmn1 rtpmn0 after reset : 00h r/w address : fffff6e4h, ffff6f4h cautions 1. to reflect real-time output signals (rtpoutn0 to rtpoutn5) to the pins (rtpn0 to rtpn5), set them to the real-time output port with the pmc and pfc registers. 2. by enabling real-time output operation (rtpoen = 1), the bits specified for the real-time output port mode perform real-time output, and the bits specified for the port mode output 0. 3. if real-time output is disabled (rtpoen = 0), real-time output signals (rtpoutn0 to rtpoutn5) all output 0, regardless of the rtpmn register setting. remark n = 1 only for the v850es/kj1. chapter 10 real-time output function (rto) user ? s manual u15862ej3v0ud 395 (2) real-time output port control register n (rtpcn) rtpcn are registers used to set the operation mode and output trigger of the real-time output port. the relationship between the operation mode and output trigger of the real-time output port is as shown in tables 10-3 and 10-4. the rtpcn register is set by an 8-bit or 1-bit memory manipulation instruction. reset input clears rtpcn to 00h. rtpoen disables operation note 1 enables operation rtpoen 0 1 control of real-time output operation rtpcn (n = 0, 1) rtpegn byten extrn 0 0 0 0 falling edge note 2 rising edge rtpegn 0 1 valid edge of inttm000 (n = 0), inttm020 (n = 1) signal 4 bits 2 channels 8 bits 1 channel byten 0 1 specification of channel configuration for real-time output after reset : 00h r/w address : fffff6e5h, fffff6f5h notes 1. when real-time output operation is disabled (rtpoen = 0), real-time output signals (rtpoutn0 to rtpoutn5) all output 0. 2. inttm000 and inttm020 are output for 1 clock of the count clock selected with the respective timers. caution perform the settings for the rtpegn, byten, and extrn bits only when rtpoen = 0. remark n = 1 only for the v850es/kj1 table 10-3. operation modes and output triggers of real-time output port (n = 0) byte0 extr0 operation mode rtbh0 (rtp04, rtp05) rtbl0 (rtp00 to rtp03) 0 inttm51 inttm50 0 1 4 bits 1 channel, 2 bits 1 channel inttm50 inttm000 0 inttm50 1 1 6 bits 1 channel inttm000 table 10-4. operation modes and output triggers of real-time output port (n = 1, v850es/kj1 only) byte1 extr1 operation mode rtbh1 (rtp14, rtp15) rtbl1 (rtp10 to rtp13) 0 inttm50 inttm51 0 1 4 bits 1 channel, 2 bits 1 channel inttm51 inttm020 0 inttm51 1 1 6 bits 1 channel inttm020 chapter 10 real-time output function (rto) user ? s manual u15862ej3v0ud 396 10.4 operation if the real-time output operation is enabled by setting bit 7 (rtpoen) of real-time output port control register n (rtpcn) to 1, the data of real-time output buffer register n (rtbhn, rtbln) is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by extrn and byten note ). of the transferred data, only the data of the bits specified in the real-time output port mode by real-time output port mode registers n (rtpmn) is output from bits rtpoutn0 to rtpoutn5. the bits specified in the port mode by the rtpmn register output 0. if the real-time output operation is disabled by clearing rtpoen to 0, rtpoutn0 to rtpoutn5 output 0 regardless of the setting of the rtpmn register. note extrn: bit 4 of the real-time output port control register n (rtpcn) byten: bits 5 of the real-time output port control register n (rtpcn) figure 10-2. example of operation timing of rto0 (when extr0 = 0, byte0 = 0) abababab d01 d02 d03 d04 d11 d12 d13 d14 d11 d12 d13 d14 d01 d02 d03 d04 inttm51 (internal) inttm50 (internal) cpu operation rtbh0 rtbl0 rt output latch 0 (h) rt output latch 0 (l) a: software processing by interrupt request input to inttm51 (rtbh0 write) b: software processing by interrupt request input to inttm50 (rtbl0 write) remark for the operation during standby, refer to chapter 21 standby function . chapter 10 real-time output function (rto) user ? s manual u15862ej3v0ud 397 10.5 usage (1) disable real-time output. clear bit 7 (rtpoen) of real-time output port control register n (rtpcn) to 0. (2) perform initialization as follows. ? specify the real-time output port mode or port mode in 1-bit units. set real-time output port mode register n (rtpmn). ? channel configuration: select the trigger and valid edge. set bits 4 to 6 (extrn, byten, and rtpegn) of the rtpcn register. ? set the initial values to real-time output buffer register n (rtbhn, rtbln) note 1 . (3) enable real-time output. set rtpoen = 1. (4) set the next output value to the rtbhn and rtbln registers by the time the selected transfer trigger is generated note 2 . (5) set the next real-time output value to the rtbhn and rtbln registers through interrupt servicing corresponding to the selected trigger. notes 1. if write to the rtbhn and rtbln registers is performed when rtpoen = 0, that value is transferred to real-time output latches nh and nl, respectively. 2. even if write is performed to the rtbhn and rtbln registers when rtpoen = 1, data transfer to real- time output latches nh and nl is not performed. caution to reflect the real-time output signals (rtpoutn0 to rtpoutn5) to the pins, set the real-time output ports (rtpn0 to rtpn5) with the pmc and pfc registers. 10.6 cautions (1) prevent the following conflicts by software. ? conflict between real-time output disable/enable switching (rtpoen bit) and selected real-time output trigger ? conflict between write to the rtbhn and rtbln registers in the real-time output enabled status and the selected real-time output trigger. (2) before performing initialization, disable real-time output (rtpoen = 0). (3) once real-time output has been disabled (rtpoen = 0), be sure to initialize the real-time output buffer registers (rtbhn and rtbln) before enabling real-time output again (rtpoen = 0 1). chapter 10 real-time output function (rto) user ? s manual u15862ej3v0ud 398 10.7 security function a circuit that sets the pin outputs to high impedance as a security function for when malfunctions of a stepping motor controlled by rto occur is provided on chip. it forcibly resets the pins allocated to rtp00 to rtp05 via external interrupt intp0 edge detection, and the pins allocated to rtp10 to rtp15 via intp1 edge detection note 1 , placing them in the high-impedance state. the ports (p50 to 55, p60 to 65 note 1 ) placed in high impedance by intp0 and intp1 note 1 are initialized note 2 , so settings for these ports must be performed again. notes 1. only for the v850es/kj1 2. regardless of the port settings, p50 to 55 and p60 to 65 are all placed in high impedance via intpn. 3. the bits that are initialized are all the bits corresponding to p50 to 55 and p60 to 65 of the following registers. ? p5, p6l ? pm5, pm6l ? pmc5, pmc6l ? pu5, pu6l ? pfc5 ? pf5 the block diagram of the security function is shown below. figure 10-3. block diagram of security function edge detection intc intpn rtostn rtpoutn0 to rtpoutn5 rtpn0 to rtpn5 ev dd r 6 remark n = 0, 1 n = 1 only for the v850es/kj1. this function is set with bits 3 and 2 (rtost1, rtost0) of the pll control register (pllctl). chapter 10 real-time output function (rto) user ? s manual u15862ej3v0ud 399 (1) pll control register (pllctl) pllctl is an 8-bit register that controls the pll. this register can be read/written in 8-bit or 1-bit units. reset input clears pllctl to 00h. 0 pllctl 0 0 0 rtost1 n ote 1 rtost0 selpll n ote 2 pllon n ote 2 intpn is not used as trigger for security function intpn is used as trigger for security function rtostn 0 1 control of rtpn0 to rtpn5 security function after reset : 01h r/w address : fffff806h < > < > < > < > notes 1. the rtost1 bit is valid only for the v850es/kj1. in the v850es/kg1 and v850es/kf1, this bit is fixed to 0. changing the value of this bit does not affect the operation. 2. for details on the selpll bit and the pllon bit, refer to chapter 6 clock generation function . cautions 1. before outputting a value to the real-time output ports (rtpn0 to rtpn5), select intpn interrupt edge detection and then set the rtost0 and rtos1 bits. 2. to set again the ports (p50 to p55, p60 to p65) as real-time output ports after placing them in high impedance via intpn, first cancel the security function. [procedure to set ports again] <1> cancel the security function and enable port setting by setting rtostn = 0. <2> set rtostn = 1 (only if required) <3> set again as rtp pin. 3. be sure to set bits 4 to 7 to 0. remark n = 0 (v850es/kf1, v850es/kg1) n = 0, 1 (v850es/kj1) user?s manual u15862ej3v0ud 400 chapter 11 watch timer functions 11.1 functions the watch timer has the following functions. ? watch timer ? interval timer the watch timer and interval timer functions can be used at the same time. figure 11-1. block diagram of watch timer internal bus watch timer operation mode register (wtm) f brg f x f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f xt 11-bit prescaler prescaler 3 note clear clear intwt intwti wtm0 wtm1 wtm2 wtm3 wtm4 wtm5 wtm6 wtm7 5-bit counter f w 3 selector selector selector selector note for details about prescaler 3, refer to figure 11-2 block diagram of prescaler 3 . remark f brg : prescaler 3 clock frequency f x : oscillation frequency f xt : subclock frequency f w : watch timer clock frequency intwt: watch timer interrupt inwti: interval timer interrupt chapter 11 watch timer functions user ? s manual u15862ej3v0ud 401 figure 11-2. block diagram of prescaler 3 f x f x /8 f x /4 f x /2 f x bgcs0 bgcs1 todis bgce 3-bit prescaler 8-bit counter output control match f bgcs f brg prescaler mode register (prsm) prescaler compare register (prscm) 2 selector clear intbrg remark f brg : prescaler 3 clock frequency f x : oscillation frequency intbrg: prescaler 3 interval timer interrupt (1) watch timer the watch timer generates an interrupt request (intwt) at time intervals of 0.5 or 0.25 seconds by using the main clock or subclock. (2) interval timer the watch timer generates an interrupt request (intwti) at time intervals specified in advance. table 11-1. interval time of interval timer interval time operating at f w = 32.768 khz 2 4 1/f w 488 s 2 5 1/f w 977 s 2 6 1/f w 1.95 ms 2 7 1/f w 3.91 ms 2 8 1/f w 7.81 ms 2 9 1/f w 15.6 ms 2 10 1/f w 31.3 ms 2 11 1/f w 62.5 ms remark f w : watch timer clock frequency chapter 11 watch timer functions user ? s manual u15862ej3v0ud 402 11.2 configuration the watch timer consists of the following hardware. table 11-2. configuration of watch timer item configuration counter 5 bits 1 prescaler 11 bits 1 control register watch timer operation mode register (wtm) 11.3 watch timer control registers two registers control the watch timer, the watch timer operation mode register (wtm). before operating the watch timer, set the count clock and the interval time. (1) watch timer operation mode register (wtm) this register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag. the wtm register is set by an 8-bit or 1-bit memory manipulation instruction. reset input clears wtm to 00h. chapter 11 watch timer functions user ? s manual u15862ej3v0ud 403 wtm7 2 4 /f w (488 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 6 /f w (1.95 ms: f w = f xt ) 2 7 /f w (3.91 ms: f w = f xt ) 2 8 /f w (7.81 ms: f w = f xt ) 2 9 /f w (15.6 ms: f w = f xt ) 2 10 /f w (31.3 ms: f w = f xt ) 2 11 /f w (62.5 ms: f w = f xt ) 2 4 /f w (488 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 6 /f w (1.95 ms: f w = f brg ) 2 7 /f w (3.91 ms: f w = f brg ) 2 8 /f w (7.81 ms: f w = f brg ) 2 9 /f w (15.6 ms: f w = f brg ) 2 10 /f w (31.3 ms: f w = f brg ) 2 11 /f w (62.5 ms: f w = f brg ) wtm7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 wtm6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 selection of interval time of prescaler wtm wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 wtm5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 wtm4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 after reset: 00h r/w address: fffff680h < > < > 2 14 /f w (0.5 s: f w = f xt ) 2 13 /f w (0.25 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 4 /f w (488 s: f w = f xt ) 2 14 /f w (0.5 s: f w = f brg ) 2 13 /f w (0.25 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 4 /f w (488 s: f w = f brg ) wtm7 0 0 0 0 1 1 1 1 selection of set time of watch flag clears after operation stops starts wtm1 0 1 control of 5-bit counter operation wtm3 0 0 1 1 0 0 1 1 wtm2 0 1 0 1 0 1 0 1 stops operation (clears both prescaler and 5-bit counter) enables operation wtm0 0 1 watch timer operation enable caution rewrite the wtm2 to wtm7 bits while both the wtm0 and wtm1 bits are 0. remarks 1. f w : watch timer clock frequency 2. values in parentheses apply when f w = 32.768 khz chapter 11 watch timer functions user ? s manual u15862ej3v0ud 404 11.4 operation 11.4.1 operation as watch timer the watch timer generates an interrupt request at fixed time intervals. the watch timer operates using time intervals of 0.5 seconds with the subclock (32.768 khz). the count operation starts when bit 0 (wtm0) and bit 1 (wtm1) of the watch timer operation mode register (wtm) are set to 1. when these bits are set to 0, the 11-bit prescaler and 5-bit counter are cleared and the count operation stops. the 5-bit counter of the watch timer can be cleared to synchronize the time by setting the wtm1 bit to 0. at this time, an error of up to 15.6 ms may occur. the interval timer may be cleared by setting the wtm0 bit to 0. however, because the 5-bit counter is cleared at the same time, an error of up to 0.5 seconds may occur when the watch timer overflows (intwt). 11.4.2 operation as interval timer the watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a count value set in advance. the interval time can be selected by bits 4 to 7 (wtm4 to wtm7) of the watch timer operation mode register (wtm). table 11-3. interval time of interval timer wtm7 wtm6 wtm5 wtm4 interval time 00002 4 1/fw 488 s (operating at f w = f xt = 32.768 khz) 00012 5 1/fw 977 s (operating at f w = f xt = 32.768 khz) 00102 6 1/fw 1.95 ms (operating at f w = f xt = 32.768 khz) 00112 7 1/fw 3.91 ms (operating at f w = f xt = 32.768 khz) 01002 8 1/fw 7.81 ms (operating at f w = f xt = 32.768 khz) 01012 9 1/fw 15.6 ms (operating at f w = f xt = 32.768 khz) 01102 10 1/fw 31.3 ms (operating at f w = f xt = 32.768 khz) 01112 11 1/fw 62.5 ms (operating at f w = f xt = 32.768 khz) 10002 4 1/fw 488 s (operating at f w = f brg = 32.768 khz) 10012 5 1/fw 977 s (operating at f w = f brg = 32.768 khz) 10102 6 1/fw 1.95 ms (operating at f w = f brg = 32.768 khz) 10112 7 1/fw 3.91 ms (operating at f w = f brg = 32.768 khz) 11002 8 1/fw 7.81 ms (operating at f w = f brg = 32.768 khz) 11012 9 1/fw 15.6 ms (operating at f w = f brg = 32.768 khz) 11102 10 1/fw 31.3 ms (operating at f w = f brg = 32.768 khz) 11112 11 1/fw 62.5 ms (operating at f w = f brg = 32.768 khz) remark f w : watch timer clock frequency chapter 11 watch timer functions user ? s manual u15862ej3v0ud 405 figure 11-3. operation timing of watch timer/interval timer start overflow overflow 0h interrupt time of watch timer (0.5 s) interrupt time of watch timer (0.5 s) interval time (t) interval time (t) nt nt 5-bit counter count clock f w or f w /2 9 watch timer interrupt intwt interval timer interrupt intwti remark f w : watch timer clock frequency values in parentheses apply when count clock f w = 32.768 khz. n: number of interval timer operations 11.4.3 cautions some time is required before the first watch timer interrupt request (intwt) is generated after operation is enabled (wtm1 and wtm0 bits of wtm register = 1). figure 11-4. example of generation of watch timer interrupt request (intwt) (when interrupt period = 0.5 s) it takes 0.515625 seconds for the first intwt to be generated (2 9 1/32768 = 0.015625 s longer). intwt is then generated every 0.5 seconds. 0.5 s 0.5 s 0.515625 s wtnm0, wtnm1 intwt chapter 11 watch timer functions user ? s manual u15862ej3v0ud 406 11.5 prescaler 3 the prescaler 3 has the following functions. ? generation of watch timer count clock (source clock: main oscillation clock) ? interval timer (intbrg) 11.5.1 control registers (1) prescaler mode register (prsm) the prsm register controls the generation of the count clock for the watch timer. prsm can be read and written in 8-bit units. 0 prsm 0 0 bgce 0 todis bgcs1 bgcs0 fixed to 0 operates fixed to 0 bgce 0 1 1 todis 0 1 prescaler output fixed to 0 operates operates prescaler interrupt signal (intbrg) f x f x /2 f x /4 f x /8 10 mhz 100 ns 200 ns 400 ns 800 ns 4 mhz 250 ns 500 ns 1 s 2 s bgcs1 0 0 1 1 bgcs0 0 1 0 1 selection of input clock (f bgcs ) note after reset: 00h r/w address: fffff8b0h < > note set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: bgcs 10 mhz v dd = 2.7 to 4.0 v: bgcs 5 mhz cautions 1. do not change the values of the bgcs0 and bgcs1 bits during prescaler 3 operation. 2. set the prsm register before setting the bgce bit to 1. 3. the 8-bit counter is cleared by clearing (0) the bgce bit. chapter 11 watch timer functions user ? s manual u15862ej3v0ud 407 (2) prescaler compare register (prscm) this is an 8-bit compare register. prscm can be read and written in 8-bit units. prscm7 prscm prscm6 prscm5 prscm4 prscm3 prscm2 prscm1 prscm0 after reset: 00h r/w address: fffff8b1h cautions 1. do not rewrite the prscm register during prescaler operation. 2. set the prscm register before setting the bgce bit of the prsm register to 1. 11.5.2 generation of count clock (1) watch timer count clock the clock (f brg ) input to the watch timer can be corrected to approximate 32.768 khz. the relationships among the main oscillation clock (f x ), input clock selection bit bgcsn setting value (m), prscm register setting value (n) and output clock (f brg ) are as follows. example: when f x = 4.00 mhz, m = 0 (bgcs1 = bgcs = 0), and n = 3dh, f brg = 32.787 khz f brg = remark f brg : count clock n: prscm register setting value (1 to ffh) in the case of prscm register setting value 00h, n = 256 m: bgcs1 and bgcs0 bit setting values (0 to 3) (2) interval timer a prescaler 3 interrupt request (intbrg) is generated at a time interval set in advance. the interval time can be set with bits 0 and 1 (bgcs0, bgcs1) of the prescaler mode register (prsm) and the prescaler compare register (prscm). the interval time is obtained with the following equation. interval time = f x 2 m n 2 2 m n f x user?s manual u15862ej3v0ud 408 chapter 12 watchdog timer functions 12.1 watchdog timer 1 12.1.1 functions watchdog timer 1 has the following operation modes. ? watchdog timer 1 ? interval timer ? selecting the oscillation stabilization time the following functions are realized from the above-listed operation modes. ? generation of non-maskable interrupt request signal (intwdt1) upon overflow of watchdog timer 1 note ? generation of system reset signal (wdtres1) upon overflow of watchdog timer 1 ? generation of maskable interrupt request signal (intwdtm1) upon overflow of interval timer note ? securing of oscillation stabilization time for main clock note restoring using the reti instruction following a non-maskable interrupt servicing due to non-maskable interrupt request (intwdt1) is not possible. therefore, following completion of interrupt servicing, perform system reset. remark select whether to use watchdog timer 1 in the watchdog timer 1 mode or the interval timer mode with watchdog timer mode register 1 (wdtm1). chapter 12 watchdog timer functions user?s manual u15862ej3v0ud 409 figure 12-1. block diagram of watchdog timer 1 internal bus wdtm14 wdtm13 run1 watchdog timer mode register 1 (wdtm1) watchdog timer clock selection register (wdcs) oscillation stabilization time selection register (osts) 2 intwdtm1 wdtres1 osc 3 output controller prescaler wdcs1 wdcs0 wdcs2 osts1 osts0 osts2 f xw /2 21 f xw /2 15 f xw /2 16 f xw /2 17 f xw /2 18 f xw /2 19 f xw /2 14 f xw /2 13 f xw /2 13 f xw /2 15 f xw /2 16 f xx /2 17 f xw /2 18 f xw /2 19 f xw /2 20 f xw /2 21 intwdt1 f xw clear 3 selector selector remark intwdtm1: request signal for maskable interrupt through watchdog timer 1 overflow intwdt1: request signal for non-maskable interrupt through watchdog timer 1 overflow wdtres1: reset signal through watchdog timer 1 overflow f xw = f x : watchdog timer 1 clock frequency chapter 12 watchdog timer functions user ? s manual u15862ej3v0ud 410 12.1.2 configuration watchdog timer 1 consists of the following hardware. table 12-1. configuration of watchdog timer 1 item configuration control register oscillation stabilization time selection register (osts) watchdog timer clock selection register (wdcs) watchdog timer mode register 1 (wdtm1) 12.1.3 watchdog timer 1 control register the registers that control watchdog timer 1 are as follows. ? oscillation stabilization time selection register (osts) ? watchdog timer clock selection register (wdcs) ? watchdog timer mode register 1 (wdtm1) (1) oscillation stabilization time selection register (osts) this register selects the oscillation stabilization time following reset or cancellation of the stop mode. the osts register is set by an 8-bit or 1-bit memory manipulation instruction. reset input sets osts to 01h. 0 osts 0 0 0 0 osts2 osts1 osts0 2 13 /f x 2 15 /f x 2 16 /f x 2 17 /f x 2 18 /f x 2 19 /f x 2 20 /f x 2 21 /f x osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 5 mhz 10 mhz 0.819 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 4 mhz 2.048 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 262.1 ms 524.3 ms 1.638 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms f x after reset: 01h r/w address: fffff6c0h chapter 12 watchdog timer functions user ? s manual u15862ej3v0ud 411 (2) watchdog timer clock selection register (wdcs) this register sets the overflow time of watchdog timer 1 and the interval timer. the wdcs register is set by an 8-bit or 1-bit memory manipulation instruction. reset input clears wdcs to 00h. 0 wdcs 0 0 0 0 wdcs2 wdcs1 wdcs0 2 13 /f xw 2 14 /f xw 2 15 /f xw 2 16 /f xw 2 17 /f xw 2 18 /f xw 2 19 /f xw 2 21 /f xw wdcs2 0 0 0 0 1 1 1 1 overflow time of watchdog timer 1/interval timer wdcs1 0 0 1 1 0 0 1 1 wdcs0 0 1 0 1 0 1 0 1 4 mhz 10 mhz 5 mhz 2.048 ms 4.096 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 524.3 ms 1.638 ms 3.276 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 419.4 ms 0.819 ms 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.2 ms 52.43 ms 209.7 ms f xw after reset: 00h r/w address: fffff6c1h remark f xw = f x : watchdog timer 1 clock frequency chapter 12 watchdog timer functions user ? s manual u15862ej3v0ud 412 (3) watchdog timer mode register 1 (wdtm1) this register sets the watchdog timer 1 operation mode and enables/disables count operations. this register is a special register that can be written only in a special sequence (refer to 3.4.7 special registers ). the wdtm1 register is set by an 8-bit or 1-bit memory manipulation instruction. reset input clears wdtm1 to 00h. run1 stops counting clears counter and starts counting run1 0 1 selection of operation mode of watchdog timer 1 note 1 wdtm1 0 0 wdtm14 wdtm13 0 0 0 after reset: 00h r/w address: fffff6c2h interval timer mode (upon overflow, maskable interrupt intwdtm1 is generated.) watchdog timer mode 1 note 3 (upon overflow, non-maskable interrupt intwdt1 is generated.) watchdog timer mode 2 (upon overflow, reset operation wdtres1 is started.) wdtm14 0 0 1 1 wdtm13 0 1 0 1 selection of operation mode of watchdog timer 1 note 2 < > notes 1. once run1 bit is set (to 1), it cannot be cleared (to 0) by software. therefore, when counting is started, it cannot be stopped except through reset input. 2. once the wdtm13 and wdtm14 bits are set (to 1), they cannot be cleared (to 0) by software and can be cleared only through reset input. 3. restoring using the reti instruction following a non-maskable interrupt servicing due to non- maskable interrupt request (intwdt1) is not possible. therefore, following completion of interrupt servicing, perform system reset. chapter 12 watchdog timer functions user ? s manual u15862ej3v0ud 413 12.1.4 operation (1) oscillation stabilization time selection function the wait time until the oscillation stabilizes after the stop mode is released is controlled by the oscillation stabilization time register (osts). the osts register is set by an 8-bit memory manipulation instruction. reset input sets osts to 01h. 0 osts 0 0 0 0 osts2 osts1 osts0 2 13 /f x 2 15 /f x 2 16 /f x 2 17 /f x 2 18 /f x 2 19 /f x 2 20 /f x 2 21 /f x osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 5 mhz 10 mhz 0.819 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 4 mhz 2.048 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 262.1 ms 524.3 ms 1.638 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms f x after reset: 01h r/w address: fffff6c0h cautions 1. the wait time following release of the stop mode does not include the time until the clock oscillation starts (figure a below) following release of the stop mode, even if the stop mode is released through reset input or the occurrence of an interrupt request signal. a stop mode release voltage waveform of x1 pin v ss 2. be sure to set bits 3 to 7 to 0. 3. the oscillation stabilization time following reset release is 2 15 /f x (because the initial value of the osts register = 01h). 4. the oscillation stabilization time is also inserted during external clock input. remark f x = oscillation frequency chapter 12 watchdog timer functions user ? s manual u15862ej3v0ud 414 (2) operation as watchdog timer 1 watchdog timer 1 operation to detect a program loop is selected by setting bit 4 (wdtm14) of watchdog timer mode register 1 (wdtm1) to 1. the count clock (program loop detection time interval) of watchdog timer 1 can be selected using bits wdcs0 to wdcs2 of the watchdog timer clock selection register (wdcs). the count operation is started by setting bit 7 (run1) of the wdtm1 register to 1. when, after the count operation is started, the run1 bit is again set to 1 within the set program loop detection time interval, watchdog timer 1 is cleared and the count operation starts again. if the program loop detection time is exceeded without run1 bit being set to 1, reset (wdtres1) through the value of bit wdtm13 of the wdtm1 register or a non-maskable interrupt request signal (intwdt1) is generated. the count operation of watchdog timer 1 stops in the stop mode and idle mode. therefore, set the run1 bit to 1 before the stop mode or idle mode is entered in order to clear watchdog timer 1. because watchdog timer 1 operates in the halt mode, do not use watchdog timer 1 when using the halt mode. cautions 1. when the subclock is selected for the cpu clock, the count operation of watchdog timer 1 is stopped (the value of watchdog timer 1 is maintained). 2. restoring using the reti instruction following a non-maskable interrupt servicing due to intwdt1 is not possible. therefore, following completion of interrupt servicing, perform system reset. table 12-2. program loop detection time of watchdog timer 1 program loop detection time clock f xw = 4 mhz f xw = 5 mhz f xw = 10 mhz 2 13 /f xw 2.048 ms 1.638 ms 0.819 ms 2 15 /f xw 8.192 ms 6.554 ms 3.277 ms 2 16 /f xw 16.38 ms 13.11 ms 6.554 ms 2 17 /f xw 32.77 ms 26.21 ms 13.11 ms 2 18 /f xw 65.54 ms 52.43 ms 26.21 ms 2 19 /f xw 131.1 ms 104.9 ms 52.43 ms 2 20 /f xw 262.1 ms 209.7 ms 104.9 ms 2 21 /f xw 524.3 ms 419.4 ms 209.7 ms remark f xw = f x : watchdog timer 1 clock frequency chapter 12 watchdog timer functions user ? s manual u15862ej3v0ud 415 (3) operation as interval timer watchdog timer 1 can be made to operate as an interval timer that repeatedly generates interrupts using the count value set in advance as the interval, by setting bit 4 (wdtm14) of watchdog timer mode register 1 (wdtm1) to 0. when watchdog timer 1 operates as an interval timer, the interrupt mask flag (wdtmk) and priority specification flags (wdtpr0 to wdtpr2) of the wdtic register are valid and maskable interrupt request signals (intwdtm1) can be generated. the default priority of the intwdtm1 signal is set to the highest level among the maskable interrupt request signals. the interval timer continues to operate in the halt mode, but it stops operating in the stop mode and the idle mode. therefore, set the run1 bit of the wdtm1 register to 1 before the stop mode or idle mode is entered in order to clear the interval timer. cautions 1. once the wdtm14 bit is set to 1 (thereby selecting the watchdog timer 1 mode), the interval timer mode is not entered as long as reset is not input. 2. when the subclock is selected for the cpu clock, the count operation of the watchdog timer 1 stops (the value of the watchdog timer is maintained). table 12-3. interval time of interval timer interval time clock f xw = 4 mhz f xw = 5 mhz f xw = 10 mhz 2 13 /f xw 2.048 ms 1.638 ms 0.819 ms 2 14 /f xw 4.096 ms 3.276 ms 1.638 ms 2 15 /f xw 8.192 ms 6.554 ms 3.277 ms 2 16 /f xw 16.38 ms 13.11 ms 6.554 ms 2 17 /f xw 32.77 ms 26.21 ms 13.11 ms 2 18 /f xw 65.54 ms 52.43 ms 26.21 ms 2 19 /f xw 131.1 ms 104.9 ms 52.43 ms 2 21 /f xw 524.3 ms 419.4 ms 209.7 ms remark f xw = f x : watchdog timer 1 clock frequency chapter 12 watchdog timer functions user ? s manual u15862ej3v0ud 416 12.2 watchdog timer 2 12.2.1 functions watchdog timer 2 has the following functions. ? default start watchdog timer note 1 reset mode: reset operation upon overflow of watchdog timer 2 (generation of wdtres2) non-maskable interrupt request mode: nmi operation upon overflow of watchdog timer 2 (generation of intwdt2) note 2 ? input selectable from main clock and subclock as the source clock notes 1. watchdog timer 2 automatically starts in the reset mode following reset release. when watchdog timer 2 is not used, either stop its operation before reset is executed through this function, or clear once watchdog timer 2 and stop it within the next interval time. also, write to the wdtm2 register for verification purposes only once, even if the default settings (reset mode, interval time: f xx /2 25 ) need not be changed. 2. restoring using the reti instruction following a non-maskable interrupt servicing due to a non- maskable interrupt request (intwdt2) is not possible. therefore, following completion of interrupt servicing, perform system reset. figure 12-2. block diagram of watchdog timer 2 f xx /2 9 clock input controller output controller wdtres2 (internal reset signal) wdcs22 internal bus intwdt2 wdcs21 wdcs20 f xt wdcs23 wdcs24 0 wdm21 wdm20 selector 16-bit counter f xx /2 18 to f xx /2 25 or f xt /2 9 to f xt /2 16 watchdog timer enable register (wdte) watchdog timer mode register 2 (wdtm2) 3 3 2 clear remark f xx : internal system clock frequency f xt : subclock frequency intwdt2: non-maskable interrupt request signal through watchdog timer 2 wdtres2: watchdog timer 2 reset signal chapter 12 watchdog timer functions user ? s manual u15862ej3v0ud 417 12.2.2 configuration watchdog timer 2 consists of the following hardware. table 12-4. configuration of watchdog timer 2 item configuration control register watchdog timer mode register 2 (wdtm2) watchdog timer enable register (wdte) 12.2.3 watchdog timer 2 control register (1) watchdog timer mode register 2 (wdtm2) this register sets the overflow time and operation clock of watchdog timer 2. wdtm2 is set with an 8-bit memory manipulation instruction. this register can be read any number of times, but it can be written only once following reset release. reset input sets wdtm2 to 67h. 0 wdtm2 wdm21 wdm20 wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 after reset: 67h r/w address: fffff6d0h stops operation non-maskable interrupt request mode (generation of intwdt2) reset mode (generation of wdtres2) wdm21 0 0 1 wdm20 0 1 ? selection of operation mode of watchdog timer 2 cautions 1. to stop the operation of watchdog timer 2, write ?1fh? to the wdtm2 register. 2. for details about bits wdcs0 to wdcs4, refer to table 12-5 watchdog timer 2 clock selection. 3. if the wdtm2 register is written twice after a reset, an overflow signal is forcibly output. chapter 12 watchdog timer functions user ? s manual u15862ej3v0ud 418 table 12-5. watchdog timer 2 clock selection wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 selected clock f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz 000002 18 /f xx 13.1 ms 16.4 ms 26.2 ms 000012 19 /f xx 26.2 ms 32.8 ms 52.4 ms 000102 20 /f xx 52.4 ms 65.5 ms 104.9 ms 000112 21 /f xx 104.9 ms 131.1 ms 209.7 ms 001002 22 /f xx 209.7 ms 262.1 ms 419.4 ms 001012 23 /f xx 419.4 ms 524.3 ms 838.9 ms 001102 24 /f xx 838.9 ms 1048.6 ms 1677.7 ms 001112 25 /f xx 1677.7 ms 2097.2 ms 3355.4 ms 010002 9 /f xt 15.625 ms (f xt = 32.768 khz) 010012 10 /f xt 31.25 ms (f xt = 32.768 khz) 010102 11 /f xt 62.5 ms (f xt = 32.768 khz) 010112 12 /f xt 125 ms (f xt = 32.768 khz) 011002 13 /f xt 250 ms (f xt = 32.768 khz) 011012 14 /f xt 500 ms (f xt = 32.768 khz) 011102 15 /f xt 1000 ms (f xt = 32.768 khz) 011112 16 /f xt 2000 ms (f xt = 32.768 khz) 1 operation stopped (2) watchdog timer enable register (wdte) the counter of watchdog timer 2 is cleared and counting restarted by writing ? ach ? to wdte. wdte is set by an 8-bit memory manipulation instruction. reset input sets wdte to 9ah. wdte after reset: 9ah r/w address: fffff6d1h cautions 1. when a value other than ?ach? is written to the wdte register, an overflow signal is forcibly output. 2. when a 1-bit memory manipulation instruction is executed for the wdte register, an overflow signal is forcibly output (an error results in the assembler). 3. the read value of the wdte register is ?9ah? (value that differs from written value ?ach?). chapter 12 watchdog timer functions user ? s manual u15862ej3v0ud 419 12.2.4 operation watchdog timer 2 automatically starts in the reset mode following reset release. the wdtm2 register can be written to only once following reset through byte access. to use watchdog timer 2, write the operation mode and the interval time to the wdtm2 register using 8-bit memory manipulation instructions. after this is done, the operation of watchdog timer 2 cannot be stopped. the watchdog timer 2 program loop detection time interval can be selected by the wdcs24 to wdcs20 bits of the wdtm2 register. writing ach to the wdte register clears the counter of watchdog timer 2 and starts the count operation again. after the count operation starts, write ach to the wdte register within the set program loop detection time interval. if the program loop detection time is exceeded without ach being written to the wdte register, a reset signal (wdtres2) or non-maskable interrupt request signal (intwdt2) is generated depending on the set value of the wdm21 and wdm20 bits of the wdtm2 register. to not use watchdog timer 2, write 1fh to the wdtm2 register. if the non-maskable interrupt request mode has been set, restoring using the reti instruction following a non- maskable interrupt servicing is not possible. therefore, following completion of interrupt servicing, perform system reset. user?s manual u15862ej3v0ud 420 chapter 13 a/d converter 13.1 function the a/d converter converts analog input signals into digital values with a resolution of 10 bits. in the v850es/kf1 and v850es/kg1, it has an 8-channel (ani0 to ani7) configuration, and in the v850es/kj1, it has a 16-channel (ani0 to ani15) configuration. the a/d converter supports a power fail monitoring function (conversion result comparison function). conversion is started by selecting one analog input channel and setting the a/d converter mode register (adm). the a/d conversion operation is repeated and each time a/d conversion has been completed, intad is generated. the block diagram is shown below. figure 13-1. block diagram of a/d converter ani0 ani1 ani2 ani3 ani4 ani11 note ani12 note ani13 note ani14 note ani15 note ani5 ani6 ani7 ani8 note ani9 note ani10 note av ref0 av ss intad 4 ads3 ads2 ads1 ads0 ads3 ads2 ads1 ads1 ads0 sample & hold circuit av ss voltage comparator controller a/d conversion result registers (adcr/adcrh) power fail comparison threshold register (pft) analog input channel specification register (ads) a/d converter mode register (adm) pfen pfcm power fail comparison mode register (pfm) internal bus successive approximation register (sar) controller tap selector selector note v850es/kj1 only chapter 13 a/d converter user ? s manual u15862ej3v0ud 421 13.2 configuration the a/d converter consists of the following hardware. table 13-1. configuration of a/d converter item configuration analog input v850es/kf1, v850es/kg1: 8 channels (ani0 to ani7) v850es/kj1: 16 channels (ani0 to ani15) registers successive approximation register (sar) a/d conversion result register (adcr) a/d conversion result register h (adcrh): only higher 8 bits can be read power fail comparison threshold register (pft) control registers a/d converter mode register (adm) analog input channel specification register (ads) power fail comparison mode register (pfm) (1) successive approximation register (sar) this register compares the voltage value of the analog input signal with the voltage tap (compare voltage) value from the series resistor string, and holds the comparison result starting from the most significant bit (msb). when the comparison result has been saved down to the least significant bit (lsb) (a/d conversion completion), the contents of the sar are transferred to the a/d conversion result register. (2) a/d conversion result register (adcr), a/d conversion result register h (adcrh) each time a/d conversion has been completed, the result of the conversion is loaded to this register from the successive approximation register, and the higher 10 bits of this register hold the result of the a/d conversion (the lower 6 bits are fixed to 0). the adcr register is read by a 16-bit memory manipulation instruction. reset input sets adcr to 0000h. when using only the higher 8 bits of the a/d conversion result, the adcrh register is read by an 8-bit memory manipulation instruction. reset input clears adcrh to 00h. (3) power fail comparison threshold register (pft) this register sets the threshold when comparing with the a/d conversion result register. the 8-bit data set in the pft register and the higher 8 bits (adcrh) of the a/d conversion result register are compared. the pft register is read and written by an 8-bit memory manipulation instruction. reset input clears pft to 00h. (4) sample & hold circuit the sample & hold circuit samples the analog input signals selected by the input circuit and sends the sampled data to the voltage comparator. this circuit holds the sampled analog input voltage during a/d conversion. (5) voltage comparator the voltage comparator compares the value that is sampled and held with the output voltage of the series resistor string. chapter 13 a/d converter user ? s manual u15862ej3v0ud 422 (6) series resistor string the series resistor string is connected between av ref0 and av ss and generates a voltage for comparison with the analog input signal. (7) ani0 to ani15 pins note these are analog input pins for the 16 channels note of the a/d converter that are used to input analog signals to be converted into digital signals. pins other than those selected as analog input with the analog input channel specification register (ads) can be used as input ports. note the v850es/kf1 and v850es/kg1 provide only 8 channels, ani0 to ani7. caution make sure that the voltage input to ani0 to ani15 does not exceed the rated values. if a voltage higher than av ref0 or lower than av ss (even within the absolute maximum ratings) is input to a channel, the conversion value of the channel is undefined and the conversion values of the other channels may also be affected. (8) av ref0 pin this is the analog power supply pin/reference voltage input pin of the a/d converter. always use the same potential as the v dd pin even when not using the a/d converter. the signals input to the ani0 to ani15 pins are converted into digital signals based on the voltage applied across av ref0 and av ss . chapter 13 a/d converter user ? s manual u15862ej3v0ud 423 13.3 control registers the a/d converter is controlled by the following registers. ? a/d converter mode register (adm) ? analog input channel specification register (ads) ? power fail comparison mode register (pfm) (1) a/d converter mode register (adm) this register sets the conversion time of the analog input signal to be converted into a digital signal as well as conversion start and stop. the adm register is set by an 8-bit or 1-bit memory manipulation instruction. reset input clears adm to 00h. adcs adcs 0 1 stops conversion enables conversion a/d conversion control adm 0 fr2 fr1 fr0 0 0 adcs2 after reset: 00h r/w address: fffff200h fr2 0 0 0 0 1 1 1 1 fr1 0 0 1 1 0 0 1 1 fr0 0 1 0 1 0 1 0 1 288/f xx 240/f xx 192/f xx setting prohibited 144/f xx 120/f xx 96/f xx setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited 14.4 s setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited 18.0 s 15.0 s setting prohibited setting prohibited conversion time note conversion time selection 20 mhz 16 mhz 14.4 s setting prohibited setting prohibited setting prohibited 28.8 s 24.0 s 19.2 s setting prohibited 10 mhz f xx adcs2 0 1 comparator off comparator on comparator control < > < > note setting the conversion time (time actually required for a/d conversion) as follows is prohibited. av ref0 4.0 v: less than 14 s av ref0 < 4.0 v: less than 17 s cautions 1. always set bits 1, 2, and 6 to 0. 2. changing bits fr0 to fr2 while adcs = 1 is prohibited (write access to the adm register is enabled and rewriting of bits fr0 to fr2 is prohibited). chapter 13 a/d converter user ? s manual u15862ej3v0ud 424 table 13-2. operation mode control adcs adcs2 0 0 stopped status dc power consumption path does not exist. 0 1 conversion standby mode only the comparator consumes power. 1 0 conversion mode note 1 1 conversion mode note note when a/d conversion is started as follows, the first conversion result is invalid. <1> (adcs, adcs2) = (0, 0) (1, 0) <2> (adcs, adcs2) = (0, 0) (1, 1) in the case of <1>, when adcs bit is set (to 1) and a/d conversion starts, the comparator is automatically switched on regardless of whether the adcs2 bit is set. the comparator is automatically switched off when the adcs bit is cleared (to 0) following conversion. similarly, in the case of <2>, the comparator is automatically switched on when the adcs bit is set (to 1) and a/d conversion starts. however, the comparator remain switched on even if the adcs bit is cleared. caution the operation of the comparator is controlled with the adcs2 bit, and 14 s are required from the start of operation until the operation stabilizes. therefore, when adcs = 1 (a/d conversion operation start) is set after 14 s have elapsed from the time adcs2 = 1 (comparator on) is set, the conversion results are valid from the first result. figure 13-2. operation sequence comparator control conversion operation conversion wait conversion operation conversion stop adcs adcs2 note reference voltage generator for boosting: operating note 14 s or more are required as the time from the rising edge of the adcs2 bit to the rising edge of the adcs bit to allow the comparator operation to stabilize. chapter 13 a/d converter user ? s manual u15862ej3v0ud 425 (2) analog input channel specification register (ads) this register specifies the analog voltage input ports for a/d conversion. the ads register is set by an 8-bit or 1-bit memory manipulation. reset input clears ads to 00h. 0 ads 0 0 0 ads3 ads2 ads1 ads0 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 note 2 ani9 note 2 ani10 note 2 ani11 note 2 ani12 note 2 ani13 note 2 ani14 note 2 ani15 note 2 ads3 note 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ads2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ads1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ads0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 specification of analog input channel after reset: 00h r/w address: fffff201h notes 1. because v850es/kf1 and v850es/kg1 have 8 channels (ani0 to ani7), be sure to set the ads3 bit to 0. 2. the ani8 to ani15 channels are available only in the v850es/kj1. in the v850es/kf1 and v850es/kg1, setting these channels is prohibited. chapter 13 a/d converter user ? s manual u15862ej3v0ud 426 (3) power fail comparison mode register (pfm) this register sets the power fail monitoring mode. it compares the value of the power fail comparison threshold register (pft) and the value of the a/d conversion result register (adcrh). the pfm register is set by an 8-bit or 1-bit memory manipulation instruction. reset input clears pfm to 00h. pfen pfen 0 1 disables power fail comparison enables power fail comparison selection of power fail comparison enable/disable pfm pfcm 0 0 0 0 0 0 pfcm 0 1 generates interrupt request signal (intad) when adcr pft generates interrupt request signal (intad) when adcr < pft selection of power fail comparison mode after reset: 00h r/w address: fffff202h < > chapter 13 a/d converter user ? s manual u15862ej3v0ud 427 13.4 relationship between analog input voltage and a/d conversion result the relationship between the analog voltage input to an analog input pin (ani0 to ani15) and the value of the a/d conversion result register (adcr) is as follows: v in adcr = int ( 1,024 + 0.5) av ref0 or, av ref0 av ref0 (adcr ? 0.5) v in < (adcr + 0.5) 1,024 1,024 int ( ): function that returns integer of value in ( ) v in : analog input voltage av ref0 : av ref0 pin voltage adcr: value of a/d conversion result register (adcr) figure 13-3 illustrates the relationship between the analog input voltages and a/d conversion results. figure 13-3. relationship between analog input voltages and a/d conversion results 1,023 1,022 1,021 3 2 1 0 input voltage/av ref0 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 a/d conversion result (adcr) chapter 13 a/d converter user ? s manual u15862ej3v0ud 428 13.5 operation 13.5.1 basic operation <1> select one channel whose analog signal is to be converted into a digital signal using the analog input channel specification register (ads). <2> the sample & hold circuit samples the voltage input to the selected analog input channel. <3> after sampling for a specific time, the sample & hold circuit enters the hold status and holds the input analog voltage until it has been converted into a digital signal. <4> set bit 9 of the successive approximation register (sar). the tap selector sets the voltage tap of the series resistor string to (1/2)av ref0 . <5> the voltage comparator compares the voltage difference between the voltage tap of the series resistor string and the analog input voltage. if the analog input voltage is greater than (1/2)av ref0 , the msb of the sar remains set. if the analog input voltage is less than the (1/2)av ref0 , the msb is reset. <6> next, bit 8 of sar is automatically set and the next comparison starts. depending on the value of bit 9 to which the result of the preceding comparison has been set, the voltage tap of the series resistor string is selected as follows. ? bit 9 = 1: (3/4)av ref0 ? bit 9 = 0: (1/4)av ref0 the analog input voltage is compared with one of these voltage taps and bit 8 of sar is manipulated as follows depending on the result of the comparison. analog input voltage voltage tap: bit 8 = 1 analog input voltage voltage tap: bit 8 = 0 <7> the above steps are repeated until bit 0 of sar has been manipulated. <8> when comparison of all 10 bits of sar has been completed, the valid digital value remains in sar, and the value of sar is transferred and latched to the a/d conversion result register (adcr). at the same time, an a/d conversion end interrupt request (intad) can be generated. caution the first conversion value immediately following the start of a/d conversion may not satisfy the ratings. chapter 13 a/d converter user ? s manual u15862ej3v0ud 429 13.5.2 conversion operation (software trigger mode) ? setting adcs of the a/d converter mode register (adm) to 1 starts conversion of the signal input to the channel specified with the analog input channel specification register (ads). upon completion of the conversion, the conversion result is stored to the adcr register and a new conversion starts. ? if adm, ads, the power fail comparison threshold value register (pft), or the power fail comparison mode register (pfm) is written to during conversion, conversion is interrupted and the conversion operation starts again from the beginning. ? if adcs is set to 0 during conversion, conversion is interrupted and the conversion operation is stopped. ? for whether or not the conversion end interrupt request signal (intad) is generated, refer to 13.5.3 power fail monitoring function . 13.5.3 power fail monitoring function the conversion end interrupt request signal (intad) can be controlled as follows using the pfm and pft registers. ? if pfen = 0, intad is generated each time conversion ends. ? if pfen = 1 and pfcm = 0, the conversion result and the value of the pft register are compared when conversion ends, and intad is output only if adcrh pft. ? if pfen and pfcm = 1, the conversion result and the value of the pft register are compared when conversion ends and intad is output only if adcrh < pft. ? because, when pfen = 1, the conversion result is overwritten after intad has been output, unless the conversion result is read by the time the next conversion ends, in some cases it may appear as if the actual operation differs from the operation described above (refer to figure 13-4 ). figure 13-4. power fail monitoring function (pfcm = 0) conversion operation adcrh pft intad ani0 80h 80h 7fh 80h ani0 ani0 ani0 note note if reading is not performed during this interval, the conversion result changes to the next conversion result. chapter 13 a/d converter user ? s manual u15862ej3v0ud 430 13.6 cautions (1) power consumption in standby mode the operation of the a/d converter stops in the stop and idle modes (operation of the a/d converter is possible in the halt mode). at this time, the power consumption can be reduced by stopping the conversion operation (bit 7 (adcs) and bit 0 (adcs2) of the a/d converter mode register (adm) = 0). (2) changing bits fr0 to fr2 stops while adcs = 1 is prohibited. (write access to the adm register is enabled and overwriting bits fr0 to fr2 is prohibited.) (3) a/d converter sampling time and a/d conversion start delay time the a/d converter sampling time differs depending on the set value of the a/d converter mode register (adm). the delay time exists until actual sampling is started after a/d converter operation is enabled. when using a set in which the a/d conversion time must be strictly observed, care is required for the contents shown in figure 13-5 and table 13-3. figure 13-5. timing of a/d converter sampling and a/d conversion start delay adcs wait period conversion time a/d conversion start delay time sampling time sampling timing intad adcs 1 or ads rewrite chapter 13 a/d converter user ? s manual u15862ej3v0ud 431 table 13-3. a/d converter sampling time and a/d conversion start delay time (adm set value) a/d conversion start delay time note fr2 fr1 fr0 conversion time sampling time min. max. 0 0 0 288/f xx 40/f xx 32/f xx 36/f xx 0 0 1 240/f xx 32/f xx 28/f xx 32/f xx 0 1 0 192/f xx 24/f xx 24/f xx 28/f xx 1 0 0 144/f xx 20/f xx 16/f xx 18/f xx 1 0 1 120/f xx 16/f xx 14/f xx 16/f xx 1 1 0 96/f xx 12/f xx 12/f xx 14/f xx other than above setting prohibited ??? note the a/d conversion start delay time is the time after wait period. for the wait function, refer to 3.4.8 (2) access to special on-chip peripheral i/o register . remark f xx : internal system clock frequency chapter 13 a/d converter user ? s manual u15862ej3v0ud 432 13.7 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input voltage that can be identified. that is, the percentage of the analog input voltage per bit of digital output is called 1lsb (least significant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). %fsr indicates the ratio of analog input voltage that can be converted as a percentage, and is always represented by the following formula regardless of the resolution. 1%fsr = (max. value of analog input voltage that can be converted ? min. value of analog input voltage that can be converted)/100 = (av ref0 ? 0)/100 = av ref0 /100 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, linearity error and errors that are combinations of these express the overall error. note that the quantization error is not included in the overall error in the characteristics table. figure 13-6. overall error ideal line 0 ?? 0 1 ?? 1 digital output overall error analog input av ref0 0 chapter 13 a/d converter user ? s manual u15862ej3v0ud 433 (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is converted to the same digital code, so a quantization error cannot be avoided. note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 13-7. quantization error 0 ?? 0 1 ?? 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av ref0 (4) zero-scale error this shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2 lsb) when the digital output changes from 0 ?? 000 to 0 ?? 001. figure 13-8. zero-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref0 digital output (lower 3 bits) analog input (lsb) -1 100 chapter 13 a/d converter user ? s manual u15862ej3v0ud 434 (5) full-scale error this shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2lsb) when the digital output changes from 1 ?? 110 to 1 ?? 111. figure 13-9. full-scale error 100 011 010 000 0 av ref0 av ref0 ? 1 av ref0 ? 2 av ref0 ? 3 digital output (lower 3 bits) analog input (lsb) full-scale error 111 (6) differential linearity error while the ideal width of code output is 1lsb, this indicates the difference between the actual measurement value and the ideal value. figure 13-10. differential linearity error 0 av ref0 digital output analog input differential linearity error 1 ?? 1 0 ?? 0 ideal 1lsb width chapter 13 a/d converter user ? s manual u15862ej3v0ud 435 (7) integral linearity error this shows the degree to which the conversion characteristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. figure 13-11. integral linearity error 0 av ref0 digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 (8) conversion time this expresses the time from when the analog input voltage was applied to the time when the digital output was obtained. the sampling time is included in the conversion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. figure 13-12. sampling time sampling time conversion time user?s manual u15862ej3v0ud 436 chapter 14 d/a converter 14.1 functions v850es/kg1 and v850es/kj1 incorporate two d/a converter channels (dac0, dac1). the d/a converter has the following functions. { 8-bit resolution 2 channels { r-2r ladder string method { conversion time: 20 s (max.) (av ref1 = 2.7 to 5.5 v) { analog output voltage: av ref1 m/256 (m = 0 to 255; value set to dacsn register) { operation modes: normal mode, real-time output mode caution the v850es/kf1 does not have a d/a converter. remark n = 0, 1 the d/a converter configuration is shown below. figure 14-1. block diagram of d/a converter dacs0 selector selector dacs1 ano0 ano1 dace0 dace1 dacs0 write damd0 inttmh0 dacs1 write damd1 inttmh1 av ref1 av ss notes 1. dac0 and dac1 share the av ref1 pin. 2. dac0 and dac1 share the av ss pin. the av ss pin is also shared by the a/d converter. chapter 14 d/a converter user ? s manual u15862ej3v0ud 437 14.2 configuration the d/a converter consists of the following hardware. table 14-1. configuration of d/a converter item configuration control register d/a converter mode register (dam) d/a conversion value setting registers 0 and 1 (dacs0, dacs1) 14.3 d/a converter control register the registers that control the d/a converter are as follows. ? d/a converter mode register (dam) ? d/a conversion value setting registers 0 and 1 (dacs0, dacs1) (1) d/a converter mode register (dam) this register controls the operation of the d/a converter. the dam is set by an 8-bit or 1-bit memory manipulation instruction. reset input clears dam to 00h. 0 normal mode real-time output mode note damdn 0 1 selection of d/a converter operation mode (n = 0, 1) dam 0 0 0 damd1 dace1 damd0 dace0 after reset: 00h r/w address: fffff284h disables operation enables operation dacen 0 1 d/a converter operation enable/disable control (n = 0, 1) < > < > note the output trigger in the real-time output mode (damdn bit = 1) is as follows. ? when n = 0: inttmh0 signal ? when n = 1: inttmh1 signal chapter 14 d/a converter user ? s manual u15862ej3v0ud 438 (2) d/a conversion value setting registers 0 and 1 (dacs0, dacs1) these registers set the analog voltage value output to the ano0 and ano1 pins. these register are set by an 8-bit memory manipulation instruction. reset input clears dacs0 and dacs1 to 00h. da07 dacs0 da06 da05 da04 da03 da02 da01 da00 after reset: 00h r/w address: fffff280h da17 dacs1 da16 da15 da14 da13 da12 da11 da10 after reset: 00h r/w address: fffff282h caution in the real-time output mode (damdn bit = 1), set the dacs0 and dacs1 registers before the inttmh0/inttmh1 signals are generated. d/a conversion starts when the inttmh0/inttmh1 signals are generated. chapter 14 d/a converter user ? s manual u15862ej3v0ud 439 14.4 operation 14.4.1 operation in normal mode d/a conversion is performed using a write operation to the d/a conversion value setting register (dacsn) as the trigger. the setting method is described below. <1> set the damdn bit of the d/a converter mode register (dam) to 0 (normal mode). <2> set the analog voltage value to be output to the anon pin to the dacsn register. steps <1> and <2> above constitute the initial settings. <3> set the dacen bit of the dam register to 1 (d/a conversion enable). d/a conversion starts when this setting is performed. <4> to perform subsequent d/a conversions, write to the dacsn register. the previous d/a conversion result is held until the next d/a conversion is performed. 14.4.2 operation in real-time output mode d/a conversion is performed using the interrupt request signals (inttmh0, inttmh1) of 8-bit timers h0 and h1 (tmh0, tmh1) as the trigger. the setting method is described below. <1> set the damdn bit of the dam register to 1 (real-time output mode). <2> set the analog voltage value to be output to the anon pin to the dacsn register. <3> set the dacen bit of the dam register to 1 (d/a conversion enable). steps <1> to <3> above constitute the initial settings. <4> operate 8-bit timers h0 and h1 (tmh0, tmh1). <5> d/a conversion starts when the inttmh0 and inttmh1 signals are generated. <6> the inttmh0 and inttmh1 signals are generated when subsequent d/a conversions are performed. before performing the next d/a conversion (generation of inttmh0, inttmh1 signals), set the analog voltage value to be output to the anon pin to the dacsn register. chapter 14 d/a converter user ? s manual u15862ej3v0ud 440 14.4.3 cautions observe the following cautions when using the d/a converter of the v850es/kg1 and v850es/kj1. ? when using the d/a converter, set the port pins to the input mode (pm1n bit = 1; n = 0, 1) ? when using the d/a converter, reading of the port is prohibited. ? when using the d/a converter, use both p10 and p11 as d/a outputs. using one of the port 1 for d/a output and the other as a port is prohibited. ? in the real-time output mode, do not change the setting value of the dacsn register while the trigger signal is output. ? make sure that av ref1 v dd and av ref1 = 2.7 v to 5.5 v. the operation is not guaranteed if ranges other than the above are used. user?s manual u15862ej3v0ud 441 chapter 15 asynchronous serial interface (uart) the number of asynchronous serial interface (uart) channels incorporated differs as follows depending on the product. product name v850es/kf1 v850es/kg1 v850es/kj1 number of channels 2 channels (uart0, uart1) 3 channels (uart0 to uart2) 15.1 selecting uart2 or i 2 c1 mode uart2 and i 2 c1 of the v850es/kj1 share pins, and therefore these interfaces cannot be used at the same time. select uart2 or i 2 c1 in advance by using the port 8 mode control register (pmc8) and port 8 function control register (pfc8) (refer to 4.3.8 port 8 ). caution uart2 or i 2 c1 transmission/reception operations are not guaranteed if the mode is changed during transmission or reception. be sure to disable the operation of the unit that is not used. figure 15-1. selecting mode of uart2 or i 2 c1 7 0 pmc8 6 0 5 0 4 0 3 0 2 0 1 pmc81 0 pmc80 7 0 pfc8 6 0 5 0 4 0 3 0 2 0 1 pfc81 0 pfc80 after reset: 00h r/w address: fffff450h after reset: 00h r/w address: fffff470h pfc8n pmc8n operation mode 0 0 port i/o mode 0 1 uart2 mode 1 0 port i/o mode 11i 2 c1 mode remark n = 0, 1 chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 442 15.2 features ? full-duplex communications on-chip reception buffer register n (rxbn) on-chip transmission buffer register n (txbn) ? two-pin configuration note txdn: transmit data output pin rxdn: receive data input pin ? reception error detection functions ? parity error ? framing error ? overrun error ? interrupt sources: 3 types ? reception error interrupt (intsren): interrupt is generated according to the logical or of the three types of reception errors ? reception completion interrupt (intsrn): interrupt is generated when receive data is transferred from the shift register to reception buffer register n after serial transfer is completed during a reception enabled state ? transmission completion interrupt (intstn): interrupt is generated when the serial transmission of transmit data (8 or 7 bits) from the shift register is completed ? the character length of transmit/receive data is specified by to the asimn register ? character length: 7 or 8 bits ? parity functions: odd, even, 0, or none ? transmission stop bits: 1 or 2 bits ? on-chip dedicated baud rate generator note the asck0 pin is available only for uart0. chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 443 15.3 configuration uartn is controlled by asynchronous serial interface mode register n (asimn), asynchronous serial interface status register n (asisn), and asynchronous serial interface transmission status register n (asifn). receive data is maintained in reception buffer register n (rxbn), and transmit data is written to transmission buffer register n (txbn). figure 15-2 shows the configuration of asynchronous serial interface n (uartn). (1) asynchronous serial interface mode register n (asimn) the asimn register is an 8-bit register for specifying the operation of the asynchronous serial interface. (2) asynchronous serial interface status register n (asisn) the asisn register consists of a set of flags that indicate the error contents when a reception error occurs. the various reception error flags are set (1) when a reception error occurs and are reset (0) when the asisn register is read. (3) asynchronous serial interface transmission status register n (asifn) the asifn register is an 8-bit register that indicates the status when a transmit operation is performed. this register consists of a transmission buffer data flag, which indicates the hold status of txbn data, and the transmission shift register data flag, which indicates whether transmission is in progress. (4) reception control parity check the receive operation is controlled according to the contents set in the asimn register. a check for parity errors is also performed during a receive operation, and if an error is detected, a value corresponding to the error contents is set in the asisn register. (5) reception shift register this is a shift register that converts the serial data that was input to the rxdn pin to parallel data. one byte of data is received, and if a stop bit is detected, the receive data is transferred to the reception buffer register n (rxbn). this register cannot be directly manipulated. (6) reception buffer register n (rxbn) rxbn is an 8-bit buffer register for holding receive data. when 7 characters are received, 0 is stored in the msb. during a reception enabled state, receive data is transferred from the reception shift register to the rxbn, synchronized with the end of the shift-in processing of one frame. also, the reception completion interrupt request (intsrn) is generated by the transfer of data to the rxbn. (7) transmission shift register this is a shift register that converts the parallel data that was transferred from the transmission buffer register n (txbn) to serial data. when one byte of data is transferred from the txbn, the shift register data is output from the txdn pin. this register cannot be directly manipulated. chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 444 (8) transmission buffer register n (txbn) txbn is an 8-bit buffer for transmit data. a transmit operation is started by writing transmit data to txbn. the transmission completion interrupt request (intstn) is generated synchronized with the completion of transmission of one frame. (9) addition of transmission control parity a transmit operation is controlled by adding a start bit, parity bit, or stop bit to the data that is written to the txbn register, according to the contents that were set in the asimn register. figure 15-2. block diagram of asynchronous serial interface n parity framing overrun internal bus asynchronous serial interface mode register n (asimn) reception buffer register n (rxbn) reception shift register reception control parity check transmission buffer register n (txbn) transmission shift register addition of transmission control parity brgn intsren intsrn intstn rxdn txdn chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 445 15.4 control registers (1) asynchronous serial interface mode register n (asimn) the asimn register is an 8-bit register that controls the uartn transfer operation. this register can be read/written in 8-bit or 1-bit units. caution when using uartn, be sure to set the external pins related to uartn functions to the control made before setting clock select register n (cksrn) and the baud rate generator control register n (brgcn), and then set the uarten bit to 1. then set the other bits. (1/3) <7> uarten asimn <6> txen <5> rxen 4 psn1 3 psn0 2 cln 1 sln 0 isrmn after reset: 01h r/w address: fffffa00h, fffffa10h, fffffa20h uarten controls the operating clock 0 stops clock supply to uartn. 1 supplies clock to uartn. ? if uarten = 0, uartn is asynchronously reset. ? if uarten = 0, uartn is reset. to operate uartn, first set uarten to 1. ? if the uarten bit is changed from 1 to 0, all the registers of uartn are initialized. to set uarten to 1 again, be sure to re-set the registers of uartn. the output of the txdn pin goes high when transmission is disabled, regardless of the setting of the uarten bit. txen enables/disables transmission 0 disables transmission 1 enables transmission ? set the txen bit to 1 after setting the uarten bit to 1 at startup. set the uarten bit to 0 after setting the txen bit to 0 to stop. ? to initialize the transmission unit, clear (0) the txen bit, and after letting 2 clock cycles (base clock) elapse, set (1) the txen bit again. if the txen bit is not set again, initialization may not be successful. (for details about the base clock, refer to 15.7.1 (1) base clock (clock) .) chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 446 (2/3) rxen enables/disables reception 0 disables reception note 1 enables reception ? set the rxen bit to 1 after setting the uarten bit to 1 at startup. set the uarten bit to 0 after setting the rxen bit to 0 to stop. ? to initialize the reception unit status, clear (0) the rxen bit, and after letting 2 clock cycles (base clock) elapse, set (1) the rxen bit again. if the rxen bit is not set again, initialization may not be successful. (for details about the base clock, refer to 15.7.1 (1) base clock (clock) .) psn1 psn0 transmit operation receive operation 00don ? t output parity bit receive with no parity 0 1 output 0 parity receive as 0 parity 1 0 output odd parity judge as odd parity 1 1 output even parity judge as even parity ? to overwrite the psn1 and psn0 bits, first clear (0) the txen and rxen bits. ? if ? 0 parity ? is selected for reception, no parity judgment is performed. therefore, no error interrupt is generated because the pen bit of the asisn register is not set. ? even parity if the transmit data contains an odd number of bits with the value ? 1 ? , the parity bit is set (1). if it contains an even number of bits with the value ? 1 ? , the parity bit is cleared (0). this controls the number of bits with the value ? 1 ? contained in the transmit data and the parity bit so that it is an even number. during reception, the number of bits with the value ? 1 ? contained in the receive data and the parity bit is counted, and if the number is odd, a parity error is generated. ? odd parity in contrast to even parity, odd parity controls the number of bits with the value ? 1 ? contained in the transmit data and the parity bit so that it is an odd number. during reception, the number of bits with the value ? 1 ? contained in the receive data and the parity bit is counted, and if the number is even, a parity error is generated. ? 0 parity during transmission, the parity bit is cleared (0) regardless of the transmit data. during reception, no parity error is generated because no parity bit is checked. ? no parity no parity bit is added to transmit data. during reception, the receive data is considered to have no parity bit. no parity error is generated because there is no parity bit. note when reception is disabled, the reception shift register does not detect a start bit. no shift-in processing or transfer processing to reception buffer register n (rxbn) is performed, and the contents of the rxbn register are retained. when reception is enabled, the reception shift operation starts, synchronized with the detection of the start bit, and when the reception of one frame is completed, the contents of the reception shift register are transferred to the rxbn register. a reception completion interrupt (intsrn) is also generated in synchronization with the transfer to the rxbn register. chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 447 (3/3) cln specifies character length of 1 frame of transmit/receive data 07 bits 18 bits ? to overwrite the cln bit, first clear (0) the txen and rxen bits. sln specifies stop bit length of transmit data 01 bit 12 bits ? to overwrite the sln bit, first clear (0) the txen bit. ? since reception is always done with a stop bit length of 1, the sln bit setting does not affect receive operations. isrmn enables/disables generation of reception completion interrupt requests when an error occurs 0 generate a reception error interrupt request (intsren) as an interrupt when an error occurs. in this case, no reception completion interrupt request (intsrn) is generated. 1 generate a reception completion interrupt request (intsrn) as an interrupt when an error occurs. in this case, no reception error interrupt request (intsren) is generated. ? to overwrite the isrmn bit, first clear (0) the rxen bit. remark n = 0, 1 (v850es/kf1, v850es/kg1) n = 0 to 2 (v850es/kj1) chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 448 (2) asynchronous serial interface status register n (asisn) the asisn register, which consists of 3 error flag bits (pen, fen and oven), indicates the error status when uartn reception is complete. the status flag, which indicates a reception error, always indicates the status of the error that occurred most recently. that is, if the same error occurred several times before the receive data was read, this flag would hold only the status of the error that occurred last. the asisn register is cleared to 00h by a read operation. when a reception error occurs, reception buffer register n (rxbn) should be read and the error flag should be cleared after the asisn register is read. this register is read-only in 8-bit units. cautions 1. when the uarten bit or rxen bit of the asimn register is set to 0, or when the asisn register is read, the pen, fen, and oven bits of the asisn register are cleared (0). 2. operation using a bit manipulation instruction is prohibited. 7 0 asisn 6 0 5 0 4 0 3 0 2 pen 1 fen 0 oven after reset: 00h r address: fffffa03h, fffffa13h, fffffa23h pen status flag indicating a parity error 0 when the asimn register ? s uarten or rxen bit is set to 0, or after the asisn register has been read 1 when reception was completed, the receive data parity did not match the parity bit ? the operation of the pen bit differs according to the settings of the psn1 and psn0 bits of the asimn register. fen status flag indicating framing error 0 when the asimn register ? s uarten or rxen bit is set to 0, or after the asisn register has been read 1 when reception was completed, no stop bit was detected ? for receive data stop bits, only the first bit is checked regardless of the stop bit length. oven status flag indicating an overrun error 0 when the asimn register ? s uarten or rxen bit is set to 0, or after the asisn register has been read. 1 uartn completed the next receive operation before reading the rxbn receive data. ? when an overrun error occurs, the next receive data value is not written to the rxbn register and the data is discarded. remark n = 0, 1 (v850es/kf1, v850es/kg1) n = 0 to 2 (v850es/kj1) chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 449 (3) asynchronous serial interface transmission status register n (asifn) the asifn register, which consists of 2 status flag bits, indicates the status during transmission. by writing the next data to the txbn register after data is transferred from the txbn register to the transmission shift register, transmit operations can be performed continuously without suspension even during an interrupt interval. when transmission is performed continuously, data should be written after referencing the txbfn bit of the asifn register to prevent writing to the txbn register by mistake. this register is read-only in 8-bit units. 7 0 asifn 6 0 5 0 4 0 3 0 2 0 <1> txbfn <0> txsfn after reset: 00h r address: fffffa05h, fffffa15h, fffffa25h txbfn transmission buffer data flag 0 data to be transferred next to txbn register does not exist (when the asimn register ? s uarten or txen bits is 0, or when data has been transferred to the transmission shift register) 1 data to be transferred next exists in txbn register (data exists in txbn register when the txbn register has been written to) ? when transmission is performed continuously, data should be written to the txbn register after confirming that this flag is 0. if writing to txbn register is performed when this flag is 1, transmit data cannot be guaranteed. txsfn transmission shift register data flag (indicates the transmission status of uartn) 0 initial status or a waiting transmission (when the asimn register ? s uarten or txen bits is set to 0, or when following transfer completion, the next data transfer from the txbn register is not performed) 1 transmission in progress (when data has been transferred from the txbn register) ? when the transmission unit is initialized, initialization should be executed after confirming that this flag is 0 following the occurrence of a transmission completion interrupt. if initialization is performed when this flag is 1, transmit data cannot be guaranteed. remark n = 0, 1 (v850es/kf1, v850es/kg1) n = 0 to 2 (v850es/kj1) chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 450 (4) reception buffer register n (rxbn) the rxbn register is an 8-bit buffer register for storing parallel data that had been converted by the reception shift register. when reception is enabled (rxen bit = 1 in the asimn register), receive data is transferred from the reception shift register to the rxbn register, synchronized with the completion of the shift-in processing of one frame. also, a reception completion interrupt request (intsrn) is generated by the transfer to the rxbn register. for information about the timing for generating this interrupt request, refer to 15.6.4 receive operation . if reception is disabled (rxen bit = 0 in the asimn register), the contents of the rxbn register are retained, and no processing is performed for transferring data to the rxbn register even when the shift-in processing of one frame is completed. also, no reception completion interrupt is generated. when 7 bits is specified for the data length, bits 6 to 0 of the rxbn register are transferred for the receive data and the msb (bit 7) is always 0. however, if an overrun error (oven bit = 1 in the asisn register) occurs, the receive data at that time is not transferred to the rxbn register. except when a reset is input, the rxbn register becomes ffh even when uarten bit = 0 in the asimn register. this register is read-only in 8-bit units. 7 rxbn7 rxbn 6 rxbn6 5 rxbn5 4 rxbn4 3 rxbn3 2 rxbn2 1 rxbn1 0 rxbn0 after reset: ffh r address: fffffa02h, fffffa12h, fffffa22h remark n = 0, 1 (v850es/kf1, v850es/kg1) n = 0 to 2 (v850es/kj1) chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 451 (5) transmission buffer register n (txbn) the txbn register is an 8-bit buffer register for setting transmit data. when transmission is enabled (txen bit = 1 in the asimn register), the transmit operation is started by writing data to txbn register. when transmission is disabled (txen bit = 0 in the asimn register), even if data is written to txbn register, the value is ignored. the txbn register data is transferred to the transmission shift register, and a transmission completion interrupt request (intstn) is generated, synchronized with the completion of the transmission of one frame from the transmission shift register. for information about the timing for generating this interrupt request, refer to 15.6.2 transmit operation . when txbfn bit = 1 in the asifn register, writing must not be performed to txbn register. this register can be read or written in 8-bit units. 7 txbn7 txbn 6 txbn6 5 txbn5 4 txbn4 3 txbn3 2 txbn2 1 txbn1 0 txbn0 after reset: ffh r/w address: fffffa04h, fffffa14h, fffffa24h remark n = 0, 1 (v850es/kf1, v850es/kg1) n = 0 to 2 (v850es/kj1) chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 452 15.5 interrupt requests the following three types of interrupt requests are generated from uartn. ? reception error interrupt (intsren) ? reception completion interrupt (intsrn) ? transmission completion interrupt (intstn) the default priorities among these three types of interrupt requests is, from high to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt. table 15-1. generated interrupts and default priorities interrupt priority reception error 1 reception completion 2 transmission completion 3 (1) reception error interrupt (intsren) when reception is enabled, a reception error interrupt is generated according to the logical or of the three types of reception errors explained for the asisn register. whether a reception error interrupt (intsren) or a reception completion interrupt (intsrn) is generated when an error occurs can be specified according to the isrmn bit of the asimn register. when reception is disabled, no reception error interrupt is generated. (2) reception completion interrupt (intsrn) when reception is enabled, a reception completion interrupt is generated when data is shifted in to the reception shift register and transferred to reception buffer register n (rxbn). a reception completion interrupt request can be generated in place of a reception error interrupt according to the isrmn bit of the asimn register even when a reception error has occurred. when reception is disabled, no reception completion interrupt is generated. (3) transmission completion interrupt (intstn) a transmission completion interrupt is generated when one frame of transmit data containing 7-bit or 8-bit characters is shifted out from the transmission shift register. chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 453 15.6 operation 15.6.1 data format full-duplex serial data transmission and reception can be performed. the transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in figure 15-3. the character bit length within one data frame, the type of parity, and the stop bit length are specified according to asynchronous serial interface mode register n (asimn). also, data is transferred with lsb first. figure 15-3. format of asynchronous serial interface transmit/receive data 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bits character bits ? start bit 1 bit ? character bits 7 bits or 8 bits ? parity bit even parity, odd parity, 0 parity, or no parity ? stop bits 1 bit or 2 bits chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 454 15.6.2 transmit operation when the uarten bit is set to 1 in the asimn register, a high level is output from the txdn pin. then, when the txen bit is set to 1 in the asimn register, transmission is enabled, and the transmit operation is started by writing transmit data to transmission buffer register n (txbn). (1) transmission enabled state this state is set by the txen bit in the asimn register. ? txen = 1: transmission enabled state ? txen = 0: transmission disabled state since uartn does not have a cts (transmission enabled signal) input pin, a port should be used to confirm whether the destination is in a reception enabled state. (2) starting a transmit operation in the transmission enabled state, a transmit operation is started by writing transmit data to transmission buffer register n (txbn). when a transmit operation is started, the data in txbn is transferred to transmission shift register. then, the transmission shift register outputs data to the txdn pin (the transmit data is transferred sequentially starting with the start bit). the start bit, parity bit, and stop bits are added automatically. (3) transmission interrupt request when the transmission shift register becomes empty, a transmission completion interrupt request (intstn) is generated. the timing for generating the intstn interrupt differs according to the specification of the stop bit length. the intstn interrupt is generated at the same time that the last stop bit is output. if the data to be transmitted next has not been written to the txbn register, the transmit operation is suspended. caution normally, when the transmission shift register becomes empty, a transmission completion interrupt (intstn) is generated. however, no transmission completion interrupt (intstn) is generated if the transmission shift register becomes empty due to the input of reset. chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 455 figure 15-4. asynchronous serial interface transmission completion interrupt timing start stop d0 d1 d2 d6 d7 parity parity txdn (output) intstn (output) start d0 d1 d2 d6 d7 txdn (output) intstn (output) (a) stop bit length: 1 (b) stop bit length: 2 stop chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 456 15.6.3 continuous transmission operation uartn can write the next transmit data to the txbn register at the timing that the transmission shift register starts the shift operation. this enables an efficient transmission rate to be realized by continuously transmitting data even during the intstn interrupt service after the transmission of one data frame. in addition, reading the txsfn bit of the asifn register after the occurrence of a transmission completion interrupt enables the txbn register to be efficiently written twice (2 bytes) without waiting for the transmission of 1 data frame. when continuous transmission is performed, data should be written after referencing the asifn register to confirm the transmission status and whether or not data can be written to the txbn register. txbfn whether or not writing to txbn register is enabled 0 writing is enabled 1 writing is not enabled caution when transmission is performed continuously, write the first transmit data (first byte) to the txbn register and confirm that the txbfn bit is 0, and then write the next transmit data (second byte) to txbn register. if writing to the txbn register is performed when the txbfn bit is 1, transmit data cannot be guaranteed. while transmission is being performed continuously, whether writing to the txbn register later is enabled can be judged by confirming the txsfn bit after the occurrence of a transmission completion interrupt. txsfn transmission status 0 transmission is completed. however, the cautions concerning the txbfn bit must be observed. writing transmit data can be performed twice (2 bytes). 1 under transmission. transmit data can be written once (1 byte). cautions 1. when initializing the transmission unit when continuous transmission is completed, confirm that the txsfn bit is 0 after the occurrence of the transmission completion interrupt, and then execute initialization. if initialization is performed when the txsfn bit is 1, transmit data cannot be guaranteed. 2. while transmission is being performed continuously, an overrun error may occur if the next transmission is completed before the intstn interrupt servicing following the transmission of 1 data frame is executed. an overrun error can be detected by embedding a program that can count the number of transmit data and referencing txsfn bit. chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 457 figure 15-5. continuous transmission processing flow set registers interrupt occurrence wait for interrupt required number of transfers performed? write transmit data to txbn register write transmit data to txbn register when reading asifn register, txbfn = 0? when reading asifn register, txsfn = 1? when reading asifn register, txsfn = 0? no no no no yes yes yes yes end of transmission processing chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 458 (1) starting procedure the procedure to start continuous transmission is shown below. figure 15-6. continuous transmission starting procedure txdn (output) data (1) data (2) <5> <1> <2> <4> intstn (output) txbn register ffh ffh data (1) data (2) data (3) data (1) data (2) data (3) <3> asifn register (txbfn, txsfn bits) 00 11 11 01 01 11 01 11 txsn register start bit stop bit stop bit start bit 10 asifn register transmission starting procedure internal operation txbfn txsfn ? set transmission mode <1> start transmission unit 0 0 ? write data (1) 10 <2> generate start bit ? read asifn register (confirm that txbfn bit = 0) start data (1) transmission 1 0 0 0 1 1 1 1 ? write data (2) < chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 459 (2) ending procedure the procedure for ending continuous transmission is shown below. figure 15-7. continuous transmission end procedure txdn (output) data (m ? 1) data (m) <11> <7> <6> <8> <10> intstn (output) txbn register data (m ? 1) data (m ? 1) data (m) ffh data (m) <9> asifn register (txbfn, txsfn bits) uarten bit or txen bit 11 01 11 01 00 txsn register start bit start bit stop bit stop bit asifn register transmission end procedure internal operation txbfn txsfn <6> transmission of data (m ? 2) is in progress 11 <7> intstn interrupt occurs ? read asifn register (confirm that txbfn bit = 0) 0 0 1 1 ? write data (m) <8> generate start bit start data (m ? 1) transmission < chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 460 15.6.4 receive operation the awaiting reception state is set by setting the uarten bit to 1 in the asimn register and then setting the rxen bit to 1 in the asimn register. to start the receive operation, first perform start bit detection. the start bit is detected by sampling the rxdn pin. when the receive operation begins, serial data is stored sequentially in the reception shift register according to the baud rate that was set. a reception completion interrupt (intsrn) is generated each time the reception of one frame of data is completed. normally, the receive data is transferred from reception buffer register n (rxbn) to memory by this interrupt servicing. (1) reception enabled state the receive operation is set to the reception enabled state by setting the rxen bit in the asimn register to 1. ? rxen bit = 1: reception enabled state ? rxen bit = 0: reception disabled state in reception disabled state, the reception hardware stands by in the initial state. at this time, the contents of reception buffer register n (rxbn) are retained, and no reception completion interrupt or reception error interrupt is generated. (2) starting a receive operation a receive operation is started by the detection of a start bit. the rxdn pin is sampled using the serial clock from baud rate generator n (brgn). (3) reception completion interrupt when rxen = 1 in the asimn register and the reception of one frame of data is completed (the stop bit is detected), a reception completion interrupt (intsrn) is generated and the receive data within the reception shift register is transferred to rxbn at the same time. also, if an overrun error (oven bit = 1 in the asynchronous serial interface status register (asisn)) occurs, the receive data at that time is not transferred to reception buffer register n (rxbn), and either a reception completion interrupt (intsrn) or a reception error interrupt (intsren) is generated according to the isrmn bit setting in the asimn register. even if a parity error (pen bit = 1 in the asisn register) or framing error (fen bit = 1 in the asisn register) occurs during a reception operation, the receive operation continues until stop bit is received, and after reception is completed, either a reception completion interrupt (intsrn) or a reception error interrupt (intsren) is generated according to the isrmn bit setting in the asimn register (the receive data within the reception shift register is transferred to rxbn). if the rxen bit is reset (0) during a receive operation, the receive operation is immediately stopped. the contents of reception buffer register n (rxbn) and of the asynchronous serial interface status register (asisn) at this time do not change, and no reception completion interrupt (intsrn) or reception error interrupt (intsren) is generated. no reception completion interrupt is generated when rxen = 0 (reception is disabled). chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 461 figure 15-8. asynchronous serial interface reception completion interrupt timing start d0 d1 d2 d6 d7 rxdn (input) intsrn (output) rxbn register parity stop cautions 1. be sure to read reception buffer register n (rxbn) even when a reception error occurs. if rxbn is not read, an overrun error will occur at the next data reception and the reception error status will continue infinitely. 2. reception is always performed assuming a stop bit length of 1. a second stop bit is ignored. 15.6.5 reception error the three types of errors that can occur during a receive operation are a parity error, framing error, and overrun error. as a result of data reception, the various flags of the asisn register are set (1), and a reception error interrupt (intsren) or a reception completion interrupt (intsrn) is generated at the same time. the isrmn bit of the asimn register specifies whether intsren or intsrn is generated. the type of error that occurred during reception can be detected by reading the contents of the asisn register during the intsren or intsrn interrupt servicing. the contents of the asisn register are reset (0) by reading the asisn register. table 15-2. reception error causes error flag reception error cause pen parity error the parity specification during transmission did not match the parity of the reception data fen framing error no stop bit was detected oven overrun error the reception of the next data was completed before data was read from reception buffer register n (rxbn) chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 462 (1) separation of reception error interrupt a reception error interrupt can be separated from the intsrn interrupt and generated as the intsren interrupt by clearing the isrmn bit of the asimn register to 0. figure 15-9. when reception error interrupt is separated from intsrn interrupt (isrmn bit = 0) (a) no error occurs during reception (b) an error occurs during reception intsrn (output) (reception completion interrupt) intsren (output) (reception error interrupt) intsrn (output) (reception completion interrupt) intsren (output) (reception error interrupt) intsrn does not occur figure 15-10. when reception error interrupt is included in intsrn interrupt (isrmn bit = 1) (a) no error occurs during reception (b) an error occurs during reception intsrn (output) (reception completion interrupt) intsren (output) (reception error interrupt) intsrn (output) (reception completion interrupt) intsren (output) (reception error interrupt) intsren does not occur chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 463 15.6.6 parity types and corresponding operation a parity bit is used to detect a bit error in communication data. normally, the same type of parity bit is used on the transmission and reception sides. (1) even parity (i) during transmission the parity bit is controlled so that the number of bits with the value ? 1 ? within the transmit data including the parity bit is even. the parity bit value is as follows. ? if the number of bits with the value ? 1 ? within the transmit data is odd: 1 ? if the number of bits with the value ? 1 ? within the transmit data is even: 0 (ii) during reception the number of bits with the value ? 1 ? within the receive data including the parity bit is counted, and a parity error is generated if this number is odd. (2) odd parity (i) during transmission in contrast to even parity, the parity bit is controlled so that the number of bits with the value ? 1 ? within the transmit data including the parity bit is odd. the parity bit value is as follows. ? if the number of bits with the value ? 1 ? within the transmit data is odd: 0 ? if the number of bits with the value ? 1 ? within the transmit data is even: 1 (ii) during reception the number of bits with the value ? 1 ? within the receive data including the parity bit is counted, and a parity error is generated if this number is even. (3) 0 parity during transmission the parity bit is set to ? 0 ? regardless of the transmit data. during reception, no parity bit check is performed. therefore, no parity error is generated regardless of whether the parity bit is ? 0 ? or ? 1 ? . (4) no parity no parity bit is added to the transmit data. during reception, the receive operation is performed as if there were no parity bit. since there is no parity bit, no parity error is generated. chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 464 15.6.7 receive data noise filter the rxdn signal is sampled at the rising edge of the prescaler output base clock (clock). if the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see figure 15-12 ). refer to 15.7.1 (1) base clock (clock) regarding the base clock. also, since the circuit is configured as shown in figure 15-11, internal processing during a receive operation is delayed by up to 2 clocks according to the external signal status. figure 15-11. noise filter circuit rxdn q clock in ld_en q in internal signal a internal signal b match detector figure 15-12. timing of rxdn signal judged as noise internal signal a clock rxdn (input) internal signal b match mismatch (judged as noise) mismatch (judged as noise) match chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 465 15.7 dedicated baud rate generator n (brgn) a dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception by uartn. the dedicated baud rate generator output can be selected as the serial clock for each channel. separate 8-bit counters exist for transmission and for reception. 15.7.1 baud rate generator n (brgn) configuration figure 15-13. configuration of baud rate generator n (brgn) f xx /2 note 2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 external input asck0 note 3 clock (f clk ) selector uarten 8-bit counter match detector baud rate brgcn: mdln7 to mdln0 1/2 uarten and txen (or rxen) cksrn: tpsn3 to tpsn0 f xx note 1 notes 1. v dd = 4.0 to 5.5 v: selectable when f xx 12 mhz v dd = 2.7 to 4.0 v: selectable when f xx 6 mhz 2. v dd = 2.7 to 4.0 v: selectable when f xx 12 mhz 3. asck0 can be used only by uart0. remark f xx : internal system clock (1) base clock (clock) when the uarten bit = 1 in the asimn register, the clock selected according to the tpsn3 to tpsn0 bits of the cksrn register is supplied to the transmission/reception unit. this clock is called the base clock (clock), and its frequency is referred to as f clk . when uarten = 0, clock is fixed to low level. chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 466 15.7.2 serial clock generation a serial clock can be generated according to the settings of the cksrn and brgcn registers. the base clock to the 8-bit counter is selected by the tpsn3 to tpsn0 bits of the cksrn register. the 8-bit counter divisor value can be set by the mdln7 to mdln0 bits of the brgcn register. (1) clock select register n (cksrn) the cksrn register is an 8-bit register for selecting the basic block using the tpsn3 to tpsn0 bits. the clock selected by the tpsn3 to tpsn0 bits becomes the base clock (clock) of the transmission/ reception module. its frequency is referred to as f clk . this register can be read or written in 8-bit units. caution set the uarten bit of the asimn register to 0 before rewriting the tpsn3 to tpsn0 bits. 7 0 cksrn 6 0 5 0 4 0 3 tpsn3 2 tpsn2 1 tpsn1 0 tpsn0 after reset: 00h r/w address: fffffa06h, fffffa16h, fffffa26h tpsn3 tpsn2 tpsn1 tpsn0 receive operation (f clk ) note 1 0000f xx 0001f xx /2 0010f xx /4 0011f xx /8 0100f xx /16 0101f xx /32 0110f xx /64 0111f xx /128 1000f xx /256 1001f xx /512 1010f xx /1,024 1011asck0 note 2 (external input) other than above setting prohibited notes 1. set so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: f clk 12 mhz v dd = 2.7 to 4.0 v: f clk 6 mhz 2. asck0 input clock can be used only by uart0. setting of uart1 and uart2 is prohibited. remark n: 0 to 2 chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 467 (2) baud rate generator control register n (brgcn) the brgcn register is an 8-bit register that controls the baud rate (serial transfer speed) of uartn. this register can be read or written in 8-bit units. caution if the mdln7 to mdln0 bits are to be overwritten, the txen and rxen bits should be set to 0 in the asimn register first. 7 mdln7 brgcn 6 mdln6 5 mdln5 4 mdln4 3 mdln3 2 mdln2 1 mdln1 0 mdln0 after reset: ffh r/w address: fffffa07h, fffffa17h, fffffa27h mdln7 mdln6 mdln5 mdln4 mdln3 mdln2 mdln1 mdln0 setting value (k) serial clock 00000 ? setting prohibited 000010008 f clk /8 000010019 f clk /9 0000101010 f clk /10 11111010250 f clk /250 11111011251 f clk /251 11111100252 f clk /252 11111101253 f clk /253 11111110254 f clk /254 11111111255 f clk /255 remarks 1. f clk : frequency [hz] of base clock (clock) selected by tpsn3 to tpsn0 bits of cksrn register 2. k: value set by mdln7 to mdln0 bits (k = 8, 9, 10, ..., 255) 3. the baud rate is the output clock for the 8-bit counter divided by 2 4. : don ? t care chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 468 (3) baud rate the baud rate is the value obtained by the following formula. baud rate = [bps] f clk = frequency [hz] of base clock (clock) selected by tpsn3 to tpsn0 bits of cksrn register. k = value set by mdln7 to mdln0 bits of brgcn register (k = 8, 9, 10, ..., 255) (4) baud rate error the baud rate error is obtained by the following formula. [%] 100 1 rate) baud (normal rate baud desired error) with rate (baud rate baud actual (%) error ? ? ? ? ? ? ? ? ? = cautions 1. make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination. 2. make sure that the baud rate error during reception is within the allowable baud rate range during reception, which is described in (4) allowable baud rate during reception. example: base clock frequency = 10 mhz = 10,000,000 hz setting of mdln7 to mdln0 bits in brgcn register = 00100001b (k = 33) target baud rate = 153,600 bps baud rate = 10m/(2 33) = 10,000,000/(2 33) = 151,515 [bps] error = (151,515/153,600 ? 1) 100 = ? 1.357 [%] f clk 2 k chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 469 15.7.3 baud rate setting example table 15-3. baud rate generator setting data f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz baud rate (bps) f clk kerrf clk kerrf clk kerr 300 f xx /512 41h (65) 0.16 f xx /1024 1ah (26) 0.16 f xx /256 41h (65) 0.16 600 f xx /256 41h (65) 0.16 f xx /1024 0dh (13) 0.16 f xx /128 41h (65) 0.16 1200 f xx /128 41h (65) 0.16 f xx /512 0dh (13) 0.16 f xx /64 41h (65) 0.16 2400 f xx /64 41h (65) 0.16 f xx /256 0dh (13) 0.16 f xx /32 41h (65) 0.16 4800 f xx /32 41h (65) 0.16 f xx /128 0dh (13) 0.16 f xx /16 41h (65) 0.16 9600 f xx /16 41h (65) 0.16 f xx /64 0dh (13) 0.16 f xx /8 41h (65) 0.16 10400 f xx /64 0fh (15) 0.16 f xx /64 0ch (12) 0.16 f xx /32 0fh (15) 0.16 19200 f xx /8 41h (65) 0.16 f xx /32 0dh (13) 0.16 f xx /4 41h (65) 0.16 24000 f xx /32 0dh (13) 0.16 f xx /2 a7h (167) ? 0.20 f xx /16 0dh (13) 0.16 31250 f xx /32 0ah (10) 0.00 f xx /32 08h (8) 0.00 f xx /16 0ah (10) 0 33600 f xx /2 95h (149) ? 0.13 f xx /2 77h (119) 0.04 f xx 95h (149) ? 0.13 38400 f xx /4 41h (65) 0.16 f xx /16 0dh (13) 0.16 f xx /2 41h (65) 0.16 48000 f xx /16 0dh (13) 0.16 f xx /2 53h (83) 0.40 f xx /8 0dh (13) 0.16 56000 f xx /2 59h (89) 0.32 f xx /2 47h (71) 0.60 f xx 59h (89) 0.32 62500 f xx /16 0ah (10) 0.00 f xx /16 08h (8) 0.00 f xx /8 0ah (10) 0.00 76800 f xx /2 41h (65) 0.16 f xx /8 0dh (13) 0.16 f xx 41h (65) 0.16 115200 f xx /2 2bh (43) 0.94 f xx /2 23h (35) ? 0.79 f xx 2bh (43) 0.94 153600 f xx /2 21h (33) ? 1.36 f xx /4 0dh (13) 0.16 f xx 21h (33) ? 1.36 312500 f xx /4 08h (8) 0 f xx /2 0dh (13) ? 1.54 f xx /2 08h (8) 0.00 caution the maximum allowable frequency of the base clock (f clk ) is 12 mhz. remark f xx : internal system clock frequency f clk : base clock frequency k: setting values of mdln7 to mdln0 bits in brgcn register err: baud rate error [%] n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 470 15.7.4 allowable baud rate range during reception the degree to which a discrepancy from the transmission destination ? s baud rate is allowed during reception is shown below. caution the equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range. figure 15-14. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartn transfer rate latch timing start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 15-14, after the start bit is detected, the receive data latch timing is determined according to the counter that was set by the brgcn register. if all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. if this is applied to 11-bit reception, the following is theoretically true. fl = (brate) ? 1 brate: uartn baud rate k: brgcn register setting value fl: 1-bit data length when the latch timing margin is 2 base clocks (clock), the minimum allowable transfer rate (flmin) is as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 min fl + = ? ? = chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 471 therefore, the transfer destination ? s maximum receivable baud rate (brmax) is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum allowable transfer rate (flmax) can be obtained as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 max fl 11 10 ? = + ? = 11 fl k 20 2 k 21 max fl ? = therefore, the transfer destination ? s minimum receivable baud rate (brmin) is as follows. brmin = (flmax/11) ? 1 = brate the allowable baud rate error of uartn and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. table 15-4. maximum and minimum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 8 +3.53% ? 3.61% 20 +4.26% ? 4.31% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.73% remarks 1. the reception precision depends on the number of bits in one frame, the base clock frequency, and the division ratio (k). the higher the base clock frequency and the larger the division ratio (k), the higher the precision. 2. k: brgcn setting value 22k 21k + 2 20k 21k ? 2 chapter 15 asynchronous serial interface (uart) user ? s manual u15862ej3v0ud 472 15.7.5 transfer rate during continuous transmission during continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the base clock (clock) longer than normal. however, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit. figure 15-15. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame bit 0 fl fl fl fl fl fl flstp start bit of second byte start bit representing the 1-bit data length by fl, the stop bit length by flstp, and the base clock frequency by f clk yields the following equation. flstp = fl + 2/f clk therefore, the transfer rate during continuous transmission is as follows (when the stop bit length = 1). transfer rate = 11 fl = 2/f clk 15.8 cautions cautions to be observed when using uartn are shown below. (1) when the supply of clocks to uartn is stopped (for example, in idle or stop mode), operation stops with each register retaining the value it had immediately before the supply of clocks was stopped. the txdn pin output also holds and outputs the value it had immediately before the supply of clocks was stopped. however, operation is not guaranteed after the supply of clocks is restarted. therefore, after the supply of clocks is restarted, the circuits should be initialized by setting uarten = 0, rxen = 0, and txen = 0 in the asimn register. (2) uartn has a 2-stage buffer configuration consisting of transmission buffer register n (txbn) and the transmission shift register, and has status flags (the txbfn and txsfn bits of the asifn register) that indicate the status of each buffer. if the txbfn and txsfn bits are read in continuous transmission, the value changes 10 11 01. read only the txbfn bit during continuous transmission. user?s manual u15862ej3v0ud 473 chapter 16 clocked serial interface 0 (csi0) the number of clocked serial interface 0 (csi0) channels incorporated differs as follows depending on the product. product name v850es/kf1 v850es/kg1 v850es/kj1 number of channels 2 channels (csi00, csi01) 3 channels (csi00 to csi02) 16.1 features ? half-duplex communications ? master mode/slave mode selectable ? transmission data length: 8 bits or 16 bits can be set ? msb/lsb-first selectable for transfer data ? eight clock signals can be selected (7 master clocks and 1 slave clock) ? 3-wire type so0n: serial transmit data output si0n: serial receive data input sck0n: serial clock i/o ? interrupt sources: 1 type ? transmission/reception completion interrupt (intcsi0n) ? transmission/reception mode or reception-only mode selectable ? two transmission buffers (sotbfn/sotbfln, sotbn/sotbln) and two reception buffers (sirbn/sirbln, sirben/sirbeln) are provided on chip ? single transfer mode/repeat transfer mode selectable remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) chapter 16 clocked serial interface 0 (csi0) user?s manual u15862ej3v0ud 474 16.2 configuration csi0n is controlled via clocked serial interface mode register 0n (csim0n). (1) clocked serial interface mode register 0n (csim0n) the csim0n register is an 8-bit register that specifies the operation of csi0n. (2) clocked serial interface clock selection register n (csicn) the csicn register is an 8-bit register that controls the csi0n serial transfer operation. (3) serial i/o shift register 0n (sio0n) the sio0n register is a 16-bit shift register that converts parallel data into serial data. the sio0n register is used for both transmission and reception. data is shifted in (reception) and shifted out (transmission) from the msb or lsb side. the actual transmission/reception operations are started up by accessing the buffer register. (4) serial i/o shift register 0nl (sio0nl) the sio0nl register is an 8-bit shift register that converts parallel data into serial data. the sio0nl register is used for both transmission and reception. data is shifted in (reception) and shifted out (transmission) from the msb or lsb side. the actual transmission/reception operations are started up by access of the buffer register . (5) clocked serial interface reception buffer register n (sirbn) the sirbn register is a 16-bit buffer register that stores receive data. (6) clocked serial interface reception buffer register nl (sirbnl) the sirbnl register is an 8-bit buffer register that stores receive data. (7) clocked serial interface read-only reception buffer register n (sirben) the sirben register is a 16-bit buffer register that stores receive data. the sirben register is the same as the sirbn register. it is used to read the contents of the sirbn register. (8) clocked serial interface read-only reception buffer register nl (sirbenl) the sirbenl register is an 8-bit buffer register that stores receive data. the sirbenl register is the same as the sirbnl register. it is used to read the contents of the sirbnl register. (9) clocked serial interface transmission buffer register n (sotbn) the sotbn register is a 16-bit buffer register that stores transmit data. (10) clocked serial interface transmission buffer register nl (sotblnl) the sotbnl register is an 8-bit buffer register that stores transmit data. (11) clocked serial interface initial transmission buffer register n (sotbfn) the sotbfn register is a 16-bit buffer register that stores the initial transmit data in the repeat transfer mode. chapter 16 clocked serial interface 0 (csi0) user?s manual u15862ej3v0ud 475 (12) clocked serial interface initial transmission buffer register nl (sotbfnl) the sotbfnl register is an 8-bit buffer register that stores initial transmit data in the repeat transfer mode. (13) selector the selector selects the serial clock to be used. (14) serial clock controller controls the serial clock supply to the shift register. also controls the clock output to the sck0n pin when the internal clock is used. (15) serial clock counter counts the serial clock output or input during transmission/reception operation, and checks whether 8-bit or 16-bit data transmission/reception has been performed. (16) interrupt controller controls the interrupt request timing. remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) chapter 16 clocked serial interface 0 (csi0) user?s manual u15862ej3v0ud 476 figure 16-1. block diagram of clocked serial interface selector transmission control so selection so latch transmit buffer register (sotbn/sotbnl) receive buffer register (sirbn/sirbnl) shift register (sion/sio0nl) initial transmit buffer register (sotbfn/sotbfnl) interrupt controller clock start/stop control & clock phase control serial clock controller sck0n intcsi0n so0n si0n control signal transmission data control f xx /2 6 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 f xx /2 to50, to51 external input sck0n remarks 1. n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) 2. f xx : internal system clock chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 477 16.3 control registers (1) clocked serial interface mode register 0n (csim0n) the csim0n register controls the csi0n operation. these registers can be read/written in 8-bit or 1-bit units (however, bit 0 is read-only). caution overwriting the trmdn, ccln, dirn, csitn, and auton bits of the csim0n register can be done only when the csotn bit = 0. if these bits are overwritten at any other time, the operation cannot be guaranteed. chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 478 <7> csi0en csim0n <6> trmdn 5 ccln <4> dirn 3 csitn 2 auton 1 0 <0> csotn after reset: 00h r/w address: fffffd00h, fffffd10h, fffffd20h csi0en enables/disables csi0n operation 0 enables csi0n operation. 1 disables csi0n operation. the internal csi0n circuit can be reset asynchronously by setting the csi0en bit to 0. for the sck0n and so0n pin output status when the csi0en bit = 0, refer to 16.5 output pins . trmdn specifies transmission/reception mode 0 receive-only mode 1 transmission/reception mode when the trmdn bit = 0, receive-only transfer is performed and the so0n pin output is fixed to low level. data reception is started by reading the sirbn register. when the trmdn bit = 1, transmission/reception is started by writing data to the sotbn register. ccln specifies data length 08 bits 1 16 bits dirn specifies transfer direction mode (msb/lsb) 0 first bit of transfer data is msb 1 first bit of transfer data is lsb csitn controls delay of interrupt request signal 0 no delay 1 delay mode (interrupt request signal is delayed 1/2 cycle) the delay mode (csitn bit = 1) is valid only in the master mode (cks0n2 to csk0n0 bits of the csicn register are not 111b). in the slave mode (cks0n2 to cks0n0 bits are 111b), do not set the delay mode. auton specifies single transfer mode or repeat transfer mode 0 single transfer mode 1 repeat transfer mode csotn flag indicating transfer status 0 idle status 1 transfer execution status the csotn bit is cleared (0) by writing 0 to the csi0en bit. remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 479 (2) clocked serial interface clock selection register n (csicn) the csicn register is an 8-bit register that controls the csi0n transfer operation. these registers can be read/written in 8-bit or 1-bit units. caution the csicn register can be overwritten only when the csi0en bit of the csim0n register = 0. 7 0 csicn 6 0 5 0 4 ckpn 3 dapn 2 cks0n2 1 cks0n1 0 cks0n0 after reset: 00h r/w address: fffffd01h, fffffd11h, fffffd21h ckpn dapn operation mode 00 do7 do6 do5 do4 do3 do2 do1 do0 di7 so0n (output) sck0n (i/o) si0n (input) di6 di5 di4 di3 di2 di1 di0 01 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 so0n (output) sck0n (i/o) si0n (input) 10 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 so0n (output) sck0n (i/o) si0n (input) 11 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 so0n (output) sck0n (i/o) si0n (input) cks0n2 cks0n1 cks0n0 input clock mode 000f xx /2 note 1 master mode 001f xx /2 2 master mode 010f xx /2 3 master mode 011f xx /2 4 master mode 100f xx /2 5 master mode 101f xx /2 6 master mode 1 1 0 clock generated by to50, to51 note 2 master mode 1 1 1 external clock (sck0n) slave mode notes 1. selectable when f xx 10 mhz 2. csi00: to50 csi01: to51 csi02: to51 remarks 1. f xx : internal system clock frequency 2. n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 480 (3) clocked serial interface reception buffer register n (sirbn) the sirbn register is a 16-bit buffer register that stores receive data. when the receive-only mode is set (trmdn bit of csim0n register = 0), the reception operation is started by reading data from the sirbn register. these registers are read-only, in 16-bit units. in addition to reset input, these registers can also be initialized by clearing (0) the csi0en bit of the csim0n register. cautions 1. read the sirbn register only when the 16-bit data length has been set (ccln bit of csim0n register = 1). 2. when the single transfer mode has been set (auton bit of csim0n register = 0), perform a read operation only in the idle state (csotn bit of csim0n register = 0). if the sirbn register is read during data transfer, the data cannot be guaranteed. 14 sirbn 14 13 sirbn 13 12 sirbn 12 2 sirbn 2 3 sirbn 3 4 sirbn 4 5 sirbn 5 6 sirbn 6 7 sirbn 7 8 sirbn 8 9 sirbn 9 10 sirbn 10 11 sirbn 11 15 sirbn 15 1 sirbn 1 0 sirbn 0 sirbn after reset: 0000h r address: fffffd02h, fffffd12h, fffffd22h remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) (4) clocked serial interface reception buffer register nl (sirbnl) the sirbnl register is an 8-bit buffer register that stores receive data. when the receive-only mode is set (trmdn bit of csim0n register = 0), the reception operation is started by reading data from the sirbnl register. these registers are read-only, in 8-bit or 1-bit units. in addition to reset input, these registers can also be initialized by clearing (0) the csi0en bit of the csim0n register. the sirbnl register is the same as the lower bytes of the sirbn register. cautions 1. read the sirbnl register only when the 8-bit data length has been set (ccln bit of csim0n register = 0). 2. when the single transfer mode is set (auton bit of csim0n register = 0), perform a read operation only in the idle state (csotn bit of csim0n register = 0). if the sirbnl register is read during data transfer, the data cannot be guaranteed. 7 sirbn7 sirbnl 6 sirbn6 5 sirbn5 4 sirbn4 3 sirbn3 2 sirbn2 1 sirbn1 0 sirbn0 after reset: 00h r address: fffffd02h, fffffd12h, fffffd22h remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 481 (5) clocked serial interface read-only reception buffer register n (sirben) the sirben register is a 16-bit buffer register that stores receive data. these registers are read-only, in 16-bit units. in addition to reset input, this register can also be initialized by clearing (0) the csi0en bit of the csim0n register. the sirben register is the same as the sirbn register. it is used to read the contents of the sirbn register. cautions 1. the receive operation is not started even if data is read from the sirben register. 2. the sirben register can be read only if the 16-bit data length is set (ccln bit of csim0n register = 1). 14 sirben 14 13 sirben 13 12 sirben 12 2 sirben 2 3 sirben 3 4 sirben 4 5 sirben 5 6 sirben 6 7 sirben 7 8 sirben 8 9 sirben 9 10 sirben 10 11 sirben 11 15 sirben 15 1 sirben 1 0 sirben 0 sirben after reset: 0000h r address: fffffd06h, fffffd16h, fffffd26h remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) (6) clocked serial interface read-only reception buffer register nl (sirbenl) the sirbenl register is an 8-bit buffer register that stores receive data. these registers are read-only, in 8-bit or 1-bit units. in addition to reset input, this register can also be initialized by clearing (0) the csi0en bit of the csim0n register. the sirbenl register is the same as the sirbnl register. it is used to read the contents of the sirbnl register. cautions 1. the receive operation is not started even if data is read from the sirbenl register. 2. the sirbenl register can be read only if the 8-bit data length has been set (ccln bit of csim0n register = 0). 7 sirben7 sirbenl 6 sirben6 5 sirben5 4 sirben4 3 sirben3 2 sirben2 1 sirben1 0 sirben0 after reset: 00h r address: fffffd06h, fffffd16h, fffffd26h remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 482 (7) clocked serial interface transmission buffer register n (sotbn) the sotbn register is a 16-bit buffer register that stores transmit data. when the transmission/reception mode is set (trmdn bit of csim0n register = 1), the transmission operation is started by writing data to the sotbn register. this register can be read/written in 16-bit units. cautions 1. access the sotbn register only when the 16-bit data length is set (ccln bit of csim0n register = 1). 2. when the single transfer mode is set (auton bit of csim0n register = 0), perform access only in the idle state (csotn bit of csim0n register = 0). if the sotbn register is accessed during data transfer, the data cannot be guaranteed. 14 sotbn 14 13 sotbn 13 12 sotbn 12 2 sotbn 2 3 sotbn 3 4 sotbn 4 5 sotbn 5 6 sotbn 6 7 sotbn 7 8 sotbn 8 9 sotbn 9 10 sotbn 10 11 sotbn 11 15 sotbn 15 1 sotbn 1 0 sotbn 0 sotbn after reset: 0000h r/w address: fffffd04h, fffffd14h, fffffd24h remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) (8) clocked serial interface transmission buffer register nl (sotbnl) the sotbnl register is an 8-bit buffer register that stores transmit data. when the transmission/reception mode is set (trmdn bit of csim0n register = 1), the transmission operation is started by writing data to the sotbnl register. these registers can be read/written in 8-bit or 1-bit units. the sotbnl register is the same as the lower bytes of the sotbn register. cautions 1. access the sotbnl register only when the 8-bit data length has been set (ccln bit of csim0n register = 0). 2. when the single transfer mode is set (auton bit of csim0n register = 0), perform access only in the idle state (csotn bit of csim0n register = 0). if the sotbnl register is accessed during data transfer, the data cannot be guaranteed. 7 sotbn7 sotbnl 6 sotbn6 5 sotbn5 4 sotbn4 3 sotbn3 2 sotbn2 1 sotbn1 0 sotbn0 after reset: 00h r/w address: fffffd04h, fffffd14h, fffffd24h remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 483 (9) clocked serial interface initial transmission buffer register n (sotbfn) the sotbfn register is a 16-bit buffer register that stores initial transmission data in the repeat transfer mode. the transmission operation is not started even if data is written to the sotbfn register. these registers can be read/written in 16-bit units. caution access the sotbfn register only when the 16-bit data length has been set (ccln bit of csim0n register = 1), and only in the idle state (csotn bit of csim0n register = 0). if the sotbfn register is accessed during data transfer, the data cannot be guaranteed. 14 sotbfn 14 13 sotbfn 13 12 sotbfn 12 2 sotbfn 2 3 sotbfn 3 4 sotbfn 4 5 sotbfn 5 6 sotbfn 6 7 sotbfn 7 8 sotbfn 8 9 sotbfn 9 10 sotbfn 10 11 sotbfn 11 15 sotbfn 15 1 sotbfn 1 0 sotbfn 0 sotbfn after reset: 0000h r/w address: fffffd08h, fffffd18h, fffffd28h remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) (10) clocked serial interface initial transmission buffer register nl (sotbfnl) the sotbfnl register is an 8-bit buffer register that stores initial transmission data in the repeat transfer mode. the transmission operation is not started even if data is written to the sotbfnl register. these registers can be read/written in 8-bit or 1-bit units. the sotbfnl register is the same as the lower bytes of the sotbfn register. caution access the sotbfnl register only when the 8-bit data length has been set (ccln bit of csim0n register = 0), and only in the idle state (csotn bit of csim0n register = 0). if the sotbfnl register is accessed during data transfer, the data cannot be guaranteed. 7 sotbfn7 sotbfnl 6 sotbfn6 5 sotbfn5 4 sotbfn4 3 sotbfn3 2 sotbfn2 1 sotbfn1 0 sotbfn0 after reset: 00h r/w address: fffffd08h, fffffd18h, fffffd28h remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 484 (11) serial i/o shift register n (sio0n) the sio0n register is a 16-bit shift register that converts parallel data into serial data. the transfer operation is not started even if the sio0n register is read. these registers are read-only, in 16-bit units. in addition to reset input, this register can also be initialized by clearing (0) the csi0en bit of the csim0n register. caution access the sio0n register only when the 16-bit data length has been set (ccln bit of csim0n register = 1), and only in the idle state (csotn bit of csim0n register = 0). if the sio0n register is accessed during data transfer, the data cannot be guaranteed. 14 sion14 13 sion13 12 sion12 2 sion2 3 sion3 4 sion4 5 sion5 6 sion6 7 sion7 8 sion8 9 sion9 10 sion10 11 sion11 15 sion15 1 sion1 0 sion0 sio0n after reset: 0000h r address: fffffd0ah, fffffd1ah, fffffd2ah remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) (12) serial i/o shift register 0nl (sio0nl) the sio0nl register is an 8-bit shift register that converts parallel data into serial data. the transfer operation is not started even if the sio0nl register is read. these registers are read-only, in 8-bit or 1-bit units. in addition to reset input, this register can also be initialized by clearing (0) the csi0en bit of the csim0n register. the sio0nl register is the same as the lower bytes of the sio0n register. caution access the sio0nl register only when the 8-bit data length has been set (ccln bit of csim0n register = 0), and only in the idle state (csotn bit of csim0n register = 0). if the sio0nl register is accessed during data transfer, the data cannot be guaranteed. 7 sion7 sio0nl 6 sion6 5 sion5 4 sion4 3 sion3 2 sion2 1 sion1 0 sion0 after reset: 00h r address: fffffd0ah, fffffd1ah, fffffd2ah remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 485 16.4 operation 16.4.1 single transfer mode (1) usage in the receive-only mode (trmdn bit of csim0n register = 0), transfer is started by reading note 1 clocked serial interface receive buffer registers n and nl (sirbn/sirbnl). in the transmission/reception mode n and nl (trmdn bit of csim0n register = 1), transfer is started by writing note 2 to clocked serial interface transmit buffer registers n and nl (sotbn/sotbnl). in the slave mode, the operation must be enabled beforehand (csi0en bit of csim0n register = 1). when transfer is started, the value of the csotn bit of the csim0n register becomes 1 (transmission execution status). upon transfer completion, the transmission/reception completion interrupt (intcsi0n) is set (1), and the csotn bit is cleared (0). the next data transfer request is then waited for. notes 1. when the 16-bit data length (ccln bit of csim0n register = 1) has been set, read the sirbn register. when the 8-bit data length (ccln bit of csim0n register = 0) has been set, read the sirbnl register. 2. when the 16-bit data length (ccln bit of csim0n register = 1) has been set, write to the sotbn register. when the 8-bit data length (ccln bit of csim0n register = 0) has been set, write to the sotbnl register. caution when the csotn bit of the csim0n register = 1, do not manipulate the csi0n register. remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 486 figure 16-2. timing chart in single transfer mode (1/2) (a) in transmission/reception mode, data length: 8 bits, transfer direction: msb first, no interrupt delay, single transfer mode, operation mode: ckpn bit = 0, dapn bit = 0 01010101 10101010 (55h) (aah) aah aah abh 56h adh 5ah b5h 6ah d5h sck0n (i/o) so0n (output) si0n (input) reg_r/w sotbnl register sio0nl register sirbnl register csotn bit intcsi0n interrupt 55h (transmit data) write 55h to sotbnl register remarks 1. n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) 2. reg_r/w: internal signal. this signal indicates that a clocked serial interface receive buffer register n and nl (sirbn/sirbnl) read or clocked serial interface transmit buffer register n and nl (sotbn/sotbnl) write was performed. chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 487 figure 16-2. timing chart in single transfer mode (2/2) (b) in transmission/reception mode, data length: 8 bits, transfer direction: msb first, no interrupt delay, single transfer mode, operation mode: ckpn bit = 0, dapn bit = 1 01010101 10101010 aah aah abh 56h adh 5ah b5h 6ah d5h sck0n (i/o) so0n (output) si0n (input) reg_r/w sotbnl register sio0nl register sirbnl register csotn bit intcsi0n interrupt (55h) (aah) 55h (transmit data) write 55h to sotbnl register remarks 1. n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) 2. reg_r/w: internal signal. this signal indicates that a clocked serial interface receive buffer register n and nl (sirbn/sirbnl) read or clocked serial interface transmit buffer register n and nl (sotbn/sotbnl) write was performed. chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 488 (2) clock phase selection the following shows the timing when changing the conditions for clock phase selection (ckpn bit of csicn register) and data phase selection (dapn bit of csicn register) under the following conditions. ? data length = 8 bits (ccln bit of csim0n register = 0) ? first bit of transfer data = msb (dirn bit of csim0n register = 0) ? no interrupt request signal delay control (csitn bit of csim0n register = 0) figure 16-3. timing chart according to clock phase selection (1/2) (a) when ckpn bit = 0, dapn bit = 0 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 sck0n (i/o) si0n (input) so0n (output) reg_r/w intcsi0n interrupt csotn bit di0 do0 (b) when ckpn bit = 1, dapn bit = 0 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 sck0n (i/o) si0n (input) so0n (output) reg_r/w intcsi0n interrupt csotn bit di0 do0 remarks 1. n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) 2. reg_r/w: internal signal. this signal indicates that a clocked serial interface receive buffer register n and nl (sirbn/sirbnl) read or clocked serial interface transmit buffer register n and nl (sotbn/sotbnl) write was performed. chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 489 figure 16-3. timing chart according to clock phase selection (2/2) (c) when ckpn bit = 0, dapn bit = 1 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 sck0n (i/o) si0n (input) so0n (output) reg_r/w intcsi0n interrupt csotn bit di0 do0 (d) when ckpn bit = 1, dapn bit = 1 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 sck0n (i/o) si0n (input) so0n (output) reg_r/w intcsi0n interrupt csotn bit di0 do0 remarks 1. n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) 2. reg_r/w: internal signal. this signal indicates that a clocked serial interface receive buffer register n and nl (sirbn/sirbnl) read or clocked serial interface transmit buffer register n and nl (sotbn/sotbnl) write was performed. chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 490 (3) transmission/reception completion interrupt request signal (intcsi0n) intcsi0n is set (1) upon completion of data transmission/reception. intcsi0n is cleared (0) by reading from clocked serial interface receive buffer registers n and nl (sirbn, sirbnl) or writing to clocked serial interface transmit buffer registers n and nl (sotbn, sotbnl). writing to csim0n register also clears (0) intcsi0n. caution the delay mode (csitn bit = 1) is valid only in the master mode (bits cks0n2 to cks0n0 of the csicn register are not 111b). the delay mode cannot be set when the slave mode is set (bits cks0n2 to cks0n0 = 111b). figure 16-4. timing chart of interrupt request signal output in delay mode (1/2) (a) when ckpn bit = 0, dapn bit = 0 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input clock sck0n (i/o) si0n (input) so0n (output) reg_r/w intcsi0n interrupt csotn bit delay remarks 1. n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) 2. reg_r/w: internal signal. this signal indicates that a clocked serial interface receive buffer register n and nl (sirbn/sirbnl) read or clocked serial interface transmit buffer register n and nl (sotbn/sotbnl) write was performed. chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 491 figure 16-4. timing chart of interrupt request signal output in delay mode (2/2) (b) when ckpn bit = 1, dapn bit = 1 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input clock sck0n (i/o) si0n (input) so0n (output) reg_r/w intcsi0n interrupt csotn bit delay remarks 1. n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) 2. reg_r/w: internal signal. this signal indicates that a clocked serial interface receive buffer register n and nl (sirbn/sirbnl) read or clocked serial interface transmit buffer register n and nl (sotbn/sotbnl) write was performed. chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 492 16.4.2 repeat transfer mode (1) usage (receive-only) <1> set the repeat transfer mode (auton bit of csim0n register = 1) and the receive-only mode (trmdn bit of csim0n register = 0). <2> read the sirbn register (start transfer with dummy read). <3> wait for the transmission/reception completion interrupt request (intcsi0n). <4> when the transmission/reception completion interrupt request (intcsi0n) has been set (1), read the sirbn register note (reserve next transfer). <5> repeat steps <3> and <4> (n ? 2) times. (n: number of transfer data) <6> following output of the last transmission/reception completion interrupt request (intcsi0n), read the sirben register and the sio0n register note . note when transferring n number of data, receive data is loaded by reading the sirbn register from the first data to the (n ? 2)th data. the (n ? 1)th data is loaded by reading the sirben register, and the nth (last) data is loaded by reading the sio0n register. chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 493 figure 16-5. repeat transfer (receive-only) timing chart din-1 sck0n (i/o) si0n (input) so0n (output) l sio0nl register sirbnl register reg_rd csotn bit intcsi0n interrupt rq_clr trans_rq din-2 din-1 sirbn (dummy) sirbn (d1) sirbn (d2) sirbn (d3) sirben (d4) sio0n (d5) < 4 >< 6 > < 4 >< 3 > < 3 > < 4 > < 5 > period during which next transfer can be reserved < 3 > < 2 > < 1 > din-2 din-3 din-4 din-5 din-5 din-3 din-4 remarks 1. n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) 2. reg_rd: internal signal. this signal indicates that clocked serial interface receive buffer registers n and nl (sirbn/sirbnl) have been read. rq_clr: internal signal. transfer request clear signal. trans_rq: internal signal. transfer request signal. in the case of the repeat transfer mode, two transfer requests are set at the start of the first transfer. following the transmission/reception completion interrupt request (intcsi0n), transfer is continued if the sirbn register can be read within the next transfer reservation period. if the sirbn register cannot be read, transfer ends and the sirbn register does not receive the new value of the sio0n register. the last data can be obtained by reading the sio0n register following completion of the transfer. chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 494 (2) usage (transmission/reception) <1> set the repeat transfer mode (auton bit of csim0n register = 1) and the transmission/reception mode (trmdn bit of csim0n register = 1) <2> write the first data to the sotbfn register. <3> write the 2nd data to the sotbn register (start transfer). <4> wait for the transmission/reception completion interrupt request (intcsi0n). <5> when the transmission/reception completion interrupt request (intcsi0n) has been set (1), write the next data to the sotbn register (reserve next transfer), and read the sirbn register to load the receive data. <6> repeat steps <4> and <5> as long as data to be sent remains. <7> wait for the intcsi0n interrupt. when the interrupt request signal is set (1), read the sirbn register to load the (n ? 1)th receive data (n: number of transfer data). <8> following the last transmission/reception completion interrupt request (intcsi0n), read the sio0n register to load the nth (last) receive data. chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 495 figure 16-6. repeat transfer (transmission/reception) timing chart dout-1 dout-1 sck0n (i/o) so0n (output) si0n (input) sotbfnl register sotbnl register sio0nl register sirbnl register reg_wr reg_rd csotn bit intcsi0n interrupt rq_clr trans_rq dout-2 dout-3 dout-4 dout-5 dout-2 dout-3 dout-4 dout-5 din-1 din-1 sotbfn (d1) sotbn (d2) sotbn (d3) sotbn (d4) sotbn (d5) sirbn (d1) sirbn (d2) < 5 >< 7 >< 8 > < 4 > < 5 > < 4 > < 6 > period during which next transfer can be reserved < 5 > < 4 > < 3 > < 2 > < 1 > sirbn (d3) sirbn (d4) sion (d5) din-2 din-3 din-4 din-5 din-2 din-3 din-4 din-5 remarks 1. n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) 2. reg_wr: internal signal. this signal indicates that clocked serial interface transmit buffer registers n and nl (sotbn/sotbnl) have been written. reg_rd: internal signal. this signal indicates that clocked serial interface receive buffer registers n and nl (sirbn/sirbnl) have been read. rq_clr: internal signal. transfer request clear signal. trans_rq: internal signal. transfer request signal. in the case of the repeat transfer mode, two transfer requests are set at the start of the first transfer. following the transmission/reception completion interrupt request (intcsi0n), transfer is continued if the sotbn register can be written within the next transfer reservation period. if the sotbn register cannot be written, transfer ends and the sirbn register does not receive the new value of the sio0n register. the last receive data can be obtained by reading the sio0n register following completion of the transfer. chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 496 (3) next transfer reservation period in the repeat transfer mode, the next transfer must be prepared with the period shown in figure 16-7. figure 16-7. timing chart of next transfer reservation period (1/2) (a) when data length: 8 bits, operation mode: ckpn bit = 0, dapn bit = 0 sck0n (i/o) intcsi0n interrupt reservation period: 7 sck0n cycles (b) when data length: 16 bits, operation mode: ckpn bit = 0, dapn bit = 0 sck0n (i/o) intcsi0n interrupt reservation period: 15 sck0n cycles remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 497 figure 16-7. timing chart of next transfer reservation period (2/2) (c) when data length: 8 bits, operation mode: ckpn bit = 0, dapn bit = 1 sck0n (i/o) intcsi0n interrupt reservation period: 6.5 sck0n cycles (d) when data length: 16 bits, operation mode: ckpn bit = 0, dapn bit = 1 sck0n (i/o) intcsi0n interrupt reservation period: 14.5 sck0n cycles remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 498 (4) cautions to continue repeat transfers, it is necessary to either read the sirbn register or write to the sotbn register during the transfer reservation period. if access is performed to the sirbn register or the sotbn register when the transfer reservation period is over, the following occurs. (i) in case of conflict between transfer request clear and register access since request cancellation has higher priority, the next transfer request is ignored. therefore, transfer is interrupted, and normal data transfer cannot be performed. figure 16-8. transfer request clear and register access conflict sck0n (i/o) intcsi0n interrupt rq_clr reg_r/w transfer reservation period remarks 1. n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) 2. rq_clr: internal signal. transfer request clear signal. reg_r/w: internal signal. this signal indicates that a clocked serial interface receive buffer register n and nl (sirbn/sirbnl) read or clocked serial interface transmit buffer register n and nl (sotbn/sotbnl) write was performed. chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 499 (ii) in case of conflict between interrupt request and register access since continuous transfer has stopped once, executed as a new repeat transfer. in the slave mode, a bit phase error transfer error results (refer to figure 16-9 ). in the transmission/reception mode, the value of the sotbfn register is retransmitted, and illegal data is sent. figure 16-9. interrupt request and register access conflict sck0n (i/o) intcsi0n interrupt rq_clr reg_r/w transfer reservation period 01 234 remarks 1. n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) 2. rq_clr: internal signal. transfer request clear signal. reg_r/w: internal signal. this signal indicates that a clocked serial interface receive buffer register n and nl (sirbn/sirbnl) read or clocked serial interface transmit buffer register n and nl (sotbn/sotbnl) write was performed. chapter 16 clocked serial interface 0 (csi0) user ? s manual u15862ej3v0ud 500 16.5 output pins (1) sck0n pin when the csi0n operation is disabled (csi0en bit of csim0n register = 0), the sck0n pin output status is as follows. table 16-1. sck0n pin output status ckpn cks0n2 cks0n1 cks0n0 sck0n pin output 0don ? t care don ? t care don ? t care fixed to high level 1 1 1 fixed to high level 1 other than above fixed to low level remarks 1. n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) 2. when any of the ckpn and cks0n2 to cks0n0 bits of the csicn register is overwritten, the sck0n pin output changes. (2) so0n pin when the csi0n operation is disabled (csi0en bit of csim0n register = 0), the so0n pin output status is as follows. table 16-2. so0n pin output status trmdn dapn auton ccln dirn so0n pin output 0don ? t care don ? t care don ? t care don ? t care fixed to low level 0don ? t care don ? t care don ? t care so latch value (low level) 0sotbn7 bit value 0 1sotbn0 bit value 0 sotbn15 bit value 0 1 1sotbn0 bit value 0 sotbfn7 bit value 0 1 sotbfn0 bit value 0 sotbfn15 bit value 1 1 1 1 1 sotbfn0 bit value remarks 1. n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) 2. when any of the trmdn, ccln, dirn, and auton bits of the csim0n register or dapn bit of the csicn register is overwritten, the so0n pin output changes. user?s manual u15862ej3v0ud 501 chapter 17 clocked serial interface a (csia) with automatic transmit/receive function the number of csia channels incorporated differs as follows depending on the product. product name v850es/kf1 v850es/kg1 v850es/kj1 number of channels 1 channel (csia0) 2 channels (csia0, csia1) 17.1 functions csian has the following three modes. ? operation stop mode ? 3-wire serial i/o mode ? 3-wire serial i/o mode with automatic transmit/receive function (1) operation stop mode this mode is used when serial transfer is not performed and can enable a reduction in the power consumption. (2) 3-wire serial i/o mode (msb/lsb-first selectable) this mode is used to transfer 8-bit data using three lines: a serial clock pin (sckan) and two serial data pins (sian and soan). the processing time of data transfer can be shortened in the 3-wire serial i/o mode because transmission and reception can be simultaneously executed. in addition, whether 8-bit data is transferred msb or lsb first can be specified, so this interface can be connected to any device. (3) 3-wire serial i/o mode with automatic transmit/receive function (msb/lsb-first selectable) this mode is used to transfer 8-bit data using three lines: a serial clock pin (sckan) and two serial data pins (sian and soan). the processing time of data transfer can be shortened in the 3-wire serial i/o mode because transmission and reception can be simultaneously executed. in addition, whether 8-bit data is transferred msb or lsb first can be specified, so this interface can be connected to any device. data can be transferred to/from a display driver etc. without using software since a 32-byte transfer buffer ram is incorporated. ? master mode/slave mode selectable ? transfer data length: 8 bits ? msb/lsb-first selectable for transfer data ? automatic transmit/receive function: number of transfer bytes can be specified between 1 and 32 transfer interval can be specified (0 to 63 clocks) single transfer/repeat transfer selectable ? on-chip dedicated baud rate generator (6/8/16/32 divisions) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user?s manual u15862ej3v0ud 502 ? 3-wire soan: serial data output sian: serial data input sckan: serial clock i/o ? transmission/reception completion interrupt: intcsian ? internal 32-byte buffer ram remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) 17.2 configuration csian consists of the following hardware. table 17-1. configuration of csian item configuration register serial i/o shift register an (sioan) automatic data transfer address count register n (adtcn) csian buffer ram (csianbm, csianbml, csianbmh) (m = 0 to f) control registers serial operation mode specification register n (csiman) serial status register n (csisn) serial trigger register n (csitn) divisor selection register n (brgcan) automatic data transfer address point specification register n (adtpn) automatic data transfer interval specification register n (adtin) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user?s manual u15862ej3v0ud 503 figure 17-1. block diagram of csian f xx /6 to f xx /256 mastern sckan soan sian dirn atmn cksan1 cksan0 atstpn atstan tsfn intcsian rxen txen 2 2 f xx buffer ram automatic data transfer address point specification register n (adtpn) automatic data transfer address count register n (adtcn) internal bus divisor selection register n (brgcan) serial i/o shift register an (sioan) serial trigger register n (csitn) serial status register n (csisn) selector selector 6-bit counter interrupt generator serial transfer controller serial clock counter automatic data transfer interval specification register n (adtin) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 504 (1) serial i/o shift register an (sioan) this is an 8-bit register used to store transmit/receive data in 1-byte transfer mode (aten bit of serial operation mode specification register n (csiman) = 0). writing transmit data to sioan starts the transfer. in addition, after a transfer completion interrupt request signal (intcsian) is output tsfn bit of serial status register n (csisn) = 0), data can be received by reading data from sioan. this register can be written or read by an 8-bit memory manipulation instruction. however, writing to the sioan register is prohibited when tsfn bit of serial status register n (csisn) = 1 reset input sets this register 00h. cautions 1. a transfer operation is started by writing to sioan register. consequently, when transmission is disabled (txen bit of csiman register = 0), write dummy data to the sioan register to start the transfer operation, and then perform a receive operation. 2. do not write data to sioan while the automatic transmit/receive function is operating. remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) (2) automatic data transfer address count register n (adtcn) this is a register used to indicate buffer ram addresses during automatic transfer. when automatic transfer is stopped, the data position when transfer stopped can be ascertained by reading adtcn register value. this register can be set by an 8-bit memory manipulation instruction. reset input sets this register to 00h. however, reading from adtcn register is prohibited when tsfn bit of serial status register n (csisn) = 1. 7 adtcn7 adtcn 6 adtcn6 5 adtcn5 4 adtcn4 3 adtcn3 2 adtcn2 1 adtcn1 0 adtcn0 after reset: 00h r address: fffffd47h, ffffd57h remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) 17.3 control registers serial interface csian is controlled by the following six registers. ? serial operation mode specification register n (csiman) ? serial status register n (csisn) ? serial trigger register n (csitn) ? divisor selection register n (brgcan) ? automatic data transfer address point specification register n (adtpn) ? automatic data transfer interval specification register n (adtin) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 505 (1) serial operation mode specification register n (csiman) this is an 8-bit register used to control the serial transfer operation. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. <7> csiaen disable csian operation (soan: low level, sckan: high level) enable csian operation csiaen 0 1 csian operation enable/disable control csiman 6 aten 5 atmn 4 mastern 3 txen 2 rxen 1 dirn 0 0 1-byte transfer mode automatic transfer mode aten 0 1 automatic transfer operation enable/disable control single transfer mode (stops at address specified with adtpn register) repeat transfer mode (following transfer completion, the adtcn register is cleared to 00h and transmission starts again.) atmn 0 1 specification of automatic transfer mode slave mode (synchronized with sckan input clock) master mode (synchronized with internal clock) mastern 0 1 specification of csian master/slave mode disable transmission (soan: low level) enable transmission txen 0 1 transmission enable/disable control disable reception enable reception rxen 0 1 reception enable/disable control msb first lsb first dirn 0 1 specification of transfer data direction after reset: 00h r/w address: fffffd40h, ffffd50h when csiaen = 0, the csian unit is reset asynchronously. when csiaen = 0, the csian unit is reset, so to operate csian, first set csiaen = 1. if the csiaen bit is changed from 1 to 0, all the registers of the csian unit are initialized. to set csiaen to 1 again, first re-set the registers of the csian unit. if the csiaen bit is changed from 1 to 0, the buffer ram value is not held. also, when the csiaen bit is 0, the buffer ram cannot be accessed. when the txen bit is 0, read from the transfer buffer ram is not possible. when the rxen bit is 0, write to the transfer buffer ram is not possible. remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 506 (2) serial status register n (csisn) this is an 8-bit register used to select the input clock and to control the transfer operation of csian. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. however, rewriting the csisn register is prohibited when tsfn bit is 1. 7 cksan1 f xx f xx /2 f xx /4 f xx /8 20 mhz setting prohibited 100 ns 200 ns 400 ns 16 mhz setting prohibited 125 ns 250 ns 500 ns 10 mhz 100 ns 200 ns 400 ns 800 ns cksan1 0 0 1 1 cksan0 0 1 0 1 serial clock (f scka ) selection note csisn 6 cksan0 5 0 4 0 3 0 2 0 1 0 0 tsfn csiaen bit of csiman register = 0 at reset input at completion of specified transfer when transfer has been suspended by setting atstpn bit of csitn register to 1 from transfer start to completion of specified transfer rewriting csisn is prohibited when the csiaen bit of the csiman register is 1. tsfn 0 1 transfer status after reset: 00h r/w address: fffffd41h, ffffd51h note set f scka so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: f scka 10 mhz v dd = 2.7 to 4.0: f scka 5 mhz cautions 1. the tsfn bit is read-only. 2. when the tsfn bit = 1, rewriting the csiman, csisn, brgcan, adtpn, adtin, sioan registers is prohibited. however, the transfer buffer ram can be rewritten. 3. when writing to bits 1 to 5, always write 0. remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 507 (3) serial trigger register n (csitn) this is an 8-bit register used to control execution/stop of automatic data transfer. this register can be set by an 8-bit or 1-bit memory manipulation instruction. reset input sets this register to 00h. however, manipulate only when the aten bit of serial operation mode specification register n (csiman) is 1 (manipulation prohibited when aten bit = 0). 7 0 csitn 6 0 5 0 4 0 3 0 2 0 <1> atstpn <0> atstan normal mode stop automatic data transfer atstpn 0 1 automatic data transfer suspension even when atstpn = 1 is set, transfer does not stop until 1 byte has been transferred. 1 is held until immediately before the intcsian interrupt signal is generated. after transfer has been interrupted, the data address at which transfer stopped is stored in the adtcn register. moreover, transfer cannot be resumed from the point where it has been stopped. after reset: 00h r/w address: fffffd42h, ffffd52h normal mode start automatic data transfer atstan 0 1 automatic data transfer start even when atstan = 1, automatic data transfer does not start until 1 byte has been transferred. 1 is held until immediately before the intcsian interrupt signal is generated. remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 508 (4) divisor selection register n (brgcan) this is an 8-bit register used to control the serial transfer speed (divisor of csia clock). this register can be set by an 8-bit memory manipulation instruction. however, when the tsfn bit of serial status register n (csisn) is 1, rewriting the brgcan register is prohibited. 7 0 brgcn1 0 0 1 1 brgcn0 0 1 0 1 selection of csian serial clock (f scka division ratio) brgcan 6 0 5 0 4 0 3 0 2 0 1 brgcn1 0 brgcn0 after reset: 03h r/w address: fffffd43h, ffffd53h 6 (f scka /6) 8 (f scka /8) 16 (f scka /16) 32 (f scka /32) remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) (5) automatic data transfer address point specification register n (adtpn) this is an 8-bit register used to specify the buffer ram address that ends transfer during automatic data transfer the aten bit of serial operation mode specification register n (csiman) = 1). this register can be set by an 8-bit memory manipulation instruction. however, when the tsfn bit of serial status register n (csisn) is 1, rewriting the adtpn register is prohibited. in the v850es/kf1, v850es/kg1, and v850es/kj1, 00h to 1fh can be specified because 32 bytes of buffer ram are incorporated. example when the adtpn register is set to 07h 8 bytes of 00h to 07h are transferred. in repeat transfer mode (atmn bit of csiman register = 1), transfer is performed repeatedly up to the address value set in adtpn. example when 07h is transferred to adtpn (repeat transfer mode) transfer is repeated as 00h to 07h, 00h to 07h, ? . 7 0 adtpn 6 0 5 0 4 adtpn4 3 adtpn3 2 adtpn2 1 adtpn1 0 adtpn0 after reset: 00h r/w address: fffffd44h, ffffd54h caution be sure to set bits 5 to 7 to 0. remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 509 the relationship between buffer ram address values and the adtpn register setting values is shown below. table 17-2. relationship between buffer ram address values and adtp0 register setting values buffer ram address value adtp0 register setting value buffer ram address value adtp0 register setting value fe00h 00h fe10h 10h fe01h 01h fe11h 11h fe02h 02h fe12h 12h fe03h 03h fe13h 13h fe04h 04h fe14h 14h fe05h 05h fe15h 15h fe06h 06h fe16h 16h fe07h 07h fe17h 17h fe08h 08h fe18h 18h fe09h 09h fe19h 19h fe0ah 0ah fe1ah 1ah fe0bh 0bh fe1bh 1bh fe0ch 0ch fe1ch 1ch fe0dh 0dh fe1dh 1dh fe0eh 0eh fe1eh 1eh fe0fh 0fh fe1fh 1fh table 17-3. relationship between buffer ram address values and adtp1 register setting values buffer ram address value adtp1 register setting value buffer ram address value adtp1 register setting value fe20h 00h fe30h 10h fe21h 01h fe31h 11h fe22h 02h fe32h 12h fe23h 03h fe33h 13h fe24h 04h fe34h 14h fe25h 05h fe35h 15h fe26h 06h fe36h 16h fe27h 07h fe37h 17h fe28h 08h fe38h 18h fe29h 09h fe39h 19h fe2ah 0ah fe3ah 1ah fe2bh 0bh fe3bh 1bh fe2ch 0ch fe3ch 1ch fe2dh 0dh fe3dh 1dh fe2eh 0eh fe3eh 1eh fe2fh 0fh fe3fh 1fh chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 510 (6) automatic data transfer interval specification register n (adtin) this is an 8-bit register used to specify the interval period between 1-byte transfers during automatic data transfer (aten bit of serial operation mode specification register n (csiman) = 1). set this register when in master mode (mastern bit of csiman register = 1) (setting is unnecessary in slave mode). setting in 1-byte transfer mode (aten bit of csiman = 0) is also valid. when the interval time specified by the adtin register after the end of 1-byte transfer has elapsed, an interrupt request signal (intcsian) is output. the number of clocks for the interval can be set to between 0 and 63 clocks. the specified interval time is the transfer clock (specified by divisor selection register n (brgcan)) multiplied by an integer value. example when adtin register = 03h sckan interval time of 3 clocks this register can be set by an 8-bit memory manipulation instruction. however, when the tsfn bit of serial status register n (csisn) is 1, rewriting the adtin register is prohibited. adtin after reset: 00h r/w address: fffffd45h, ffffd55h 7 0 6 0 5 adtin5 4 adtin4 3 adtin3 2 adtin2 1 adtin1 0 adtin0 remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) (7) csian buffer ram (csianbm) this area holds transmit/receive data (up to 32 bytes) in automatic transfer mode in 1-bit units. the csianbm register can be read/written in 16-bit units only. however, when the higher 8 bits and the lower 8 bits of the csianbm register are used as the csianbmh register and csianbml register, respectively, these registers can be read/written in 8-bit units. after automatic transfer is started, only data of the number of adtpn register bytes is transmitted/received in sequence from the csiamb0l register. remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) m = 0 to f chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 511 table 17-4. csia0 buffer ram manipulatable bits address symbol r/w 816 after reset fffffe00h csia0b0 r/w undefined fffffe00h csia0b0l r/w undefined fffffe01h csia0b0h r/w undefined fffffe02h csia0b1 r/w undefined fffffe02h csia0b1l r/w undefined fffffe03h csia0b1h r/w undefined fffffe04h csia0b2 r/w undefined fffffe04h csia0b2l r/w undefined fffffe05h csia0b2h r/w undefined fffffe06h csia0b3 r/w undefined fffffe06h csia0b3l r/w undefined fffffe07h csia0b3h r/w undefined fffffe08h csia0b4 r/w undefined fffffe08h csia0b4l r/w undefined fffffe09h csia0b4h r/w undefined fffffe0ah csia0b5 r/w undefined fffffe0ah csia0b5l r/w undefined fffffe0bh csia0b5h r/w undefined fffffe0ch csia0b6 r/w undefined fffffe0ch csia0b6l r/w undefined fffffe0dh csia0b6h r/w undefined fffffe0eh csia0b7 r/w undefined fffffe0eh csia0b7l r/w undefined fffffe0fh csia0b7h r/w undefined fffffe10h csia0b8 r/w undefined fffffe10h csia0b8l r/w undefined fffffe11h csia0b8h r/w undefined fffffe12h csia0b9 r/w undefined fffffe12h csia0b9l r/w undefined fffffe13h csia0b9h r/w undefined fffffe14h csia0ba r/w undefined fffffe14h csia0bal r/w undefined fffffe15h csia0bah r/w undefined fffffe16h csia0bb r/w undefined fffffe16h csia0bbl r/w undefined fffffe17h csia0bbh r/w undefined fffffe18h csia0bc r/w undefined fffffe18h csia0bcl r/w undefined fffffe19h csia0bch r/w undefined fffffe1ah csia0bd r/w undefined fffffe1ah csia0bdl r/w undefined fffffe1bh csia0bdh r/w undefined fffffe1ch csia0be r/w undefined fffffe1ch csia0bel r/w undefined fffffe1dh csia0beh r/w undefined fffffe1eh csia0bf r/w undefined fffffe1eh csia0bfl r/w undefined fffffe1fh csia0bfh r/w undefined chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 512 table 17-5. csia1 buffer ram manipulatable bits address symbol r/w 816 after reset fffffe20h csia1b0 r/w undefined fffffe20h csia1b0l r/w undefined fffffe21h csia1b0h r/w undefined fffffe22h csia1b1 r/w undefined fffffe22h csia1b1l r/w undefined fffffe23h csia1b1h r/w undefined fffffe24h csia1b2 r/w undefined fffffe24h csia1b2l r/w undefined fffffe25h csia1b2h r/w undefined fffffe26h csia1b3 r/w undefined fffffe26h csia1b3l r/w undefined fffffe27h csia1b3h r/w undefined fffffe28h csia1b4 r/w undefined fffffe28h csia1b4l r/w undefined fffffe29h csia1b4h r/w undefined fffffe2ah csia1b5 r/w undefined fffffe2ah csia1b5l r/w undefined fffffe2bh csia1b5h r/w undefined fffffe2ch csia1b6 r/w undefined fffffe2ch csia1b6l r/w undefined fffffe2dh csia1b6h r/w undefined fffffe2eh csia1b7 r/w undefined fffffe2eh csia1b7l r/w undefined fffffe2fh csia1b7h r/w undefined fffffe30h csia1b8 r/w undefined fffffe30h csia1b8l r/w undefined fffffe31h csia1b8h r/w undefined fffffe32h csia1b9 r/w undefined fffffe32h csia1b9l r/w undefined fffffe33h csia1b9h r/w undefined fffffe34h csia1ba r/w undefined fffffe34h csia1bal r/w undefined fffffe35h csia1bah r/w undefined fffffe36h csia1bb r/w undefined fffffe36h csia1bbl r/w undefined fffffe37h csia1bbh r/w undefined fffffe38h csia1bc r/w undefined fffffe38h csia1bcl r/w undefined fffffe39h csia1bch r/w undefined fffffe3ah csia1bd r/w undefined fffffe3ah csia1bdl r/w undefined fffffe3bh csia1bdh r/w undefined fffffe3ch csia1be r/w undefined fffffe3ch csia1bel r/w undefined fffffe3dh csia1beh r/w undefined fffffe3eh csia1bf r/w undefined fffffe3eh csia1bfl r/w undefined fffffe3f csia1bfh r/w undefined remark v850es/kg1, v850es/kj1 only chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 513 17.4 operation csian can be used in the following three modes. operation stop mode 3-wire serial i/o mode ? 3-wire serial i/o mode with automatic transmit/receive function 17.4.1 operation stop mode serial transfer is not executed in this mode. therefore, the power consumption can be reduced. (1) register setting the operation stop mode is set by serial operation mode specification register n (csiman). (a) serial operation mode specification register n (csiman) this is an 8-bit register used to control the serial transfer operation. this register can be set by an 8-bit or 1-bit memory manipulation instruction. reset input sets this register to 00h. <7> csiaen disable csian operation (soan: low level, sckan: high level) enable csian operation csiaen 0 1 csian operation enable/disable control csiman 6 aten 5 atmn 4 mastern 3 txen 2 rxen 1 dirn 0 0 after reset: 00h r/w address: fffffd40h, ffffd50h 17.4.2 3-wire serial i/o mode the one-byte data transmission/reception is executed in the mode in which the aten bit of serial operation mode specification register n (csiman) is set to 0. in this mode, communication is executed by using three lines: serial clock (sckan), serial data output (soan), and serial data input (sian) pins. (1) register setting csian is controlled by the following three registers. serial operation mode specification register n (csiman) serial status register n (csisn) divisor selection register n (brgcan) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 514 (a) serial operation mode specification register n (csiman) this is an 8-bit register used to control the serial transfer operation. this register can be set by an 8-bit or 1-bit memory manipulation instruction. reset input sets this register to 00h. <7> csiaen disable csian operation (soan: low level, sckan: high level) enable csian operation csiaen 0 1 csian operation enable/disable control csiman 6 aten 5 atmn 4 mastern 3 txen 2 rxen 1 dirn 0 0 1-byte transfer mode automatic transfer mode aten 0 1 automatic transfer operation enable/disable control single transfer mode (stops at address specified with adtpn register) repeat transfer mode (following transfer completion, the adtcn register is cleared to 00h and transmission starts again.) atmn 0 1 specification of automatic transfer mode slave mode (synchronized with sckan input clock) master mode (synchronized with internal clock) mastern 0 1 specification of csian master/slave mode disable transmission (soan: low level) enable transmission txen 0 1 transmission enable/disable control disable reception enable reception rxen 0 1 reception enable/disable control msb first lsb first dirn 0 1 specification of transfer data direction after reset: 00h r/w address: fffffd40h, ffffd50h when csiaen = 0, the csian unit is reset asynchronously. when csiaen = 0, the csian unit is reset, so to operate csian, first set csiaen = 1. if the csiaen bit is changed from 1 to 0, all the registers of the csian unit are initialized. to set csiaen to 1 again, first re-set the registers of the csian unit. if the csiaen bit is changed from 1 to 0, the buffer ram value is not held. also, when the csiaen bit is 0, the buffer ram cannot be accessed. when the txen bit is 0, read from the transfer buffer ram is not possible. when the rxen bit is 0, write to the transfer buffer ram is not possible. remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 515 (b) serial status register n (csisn) this is an 8-bit register used to select the input clock and to control the transfer operation of csian. this register can be set by an 8-bit or 1-bit memory manipulation instruction. reset input sets this register to 00h. however, rewriting the csisn register is prohibited when the tsfn bit is 1. 7 cksan1 f xx f xx /2 f xx /4 f xx /8 20 mhz setting prohibited 100 ns 200 ns 400 ns 16 mhz setting prohibited 125 ns 250 ns 500 ns 10 mhz 100 ns 200 ns 400 ns 800 ns cksan1 0 0 1 1 cksan0 0 1 0 1 serial clock (f scka ) selection note csisn 6 cksan0 5 0 4 0 3 0 2 0 1 0 0 tsfn csiaen bit of csiman register = 0 at reset input at completion of specified transfer when transfer has been suspended by setting atstpn bit of csitn register to 1 from transfer start to completion of specified transfer rewriting csisn is prohibited when the csiaen bit of the csiman register is 1. tsfn 0 1 transfer status after reset: 00h r/w address: fffffd41h, ffffd51h note set f scka so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: f scka 10 mhz v dd = 2.7 to 4.0: f scka 5 mhz cautions 1. the tsfn bit is read-only. 2. when the tsfn bit = 1, rewriting the csiman, csisn, brgcan, adtpn, adtin, sioan registers is prohibited. however, the transfer buffer ram can be rewritten. 3. when writing to bits 1 to 5, always write 0. remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 516 (c) divisor selection register n (brgcan) this is an 8-bit register used to control the serial transfer speed (divisor of csia input clock). this register can be set by an 8-bit memory manipulation instruction. however, when the tsfn bit of serial status register n (csisn) is 1, rewriting the brgcan register is prohibited. 7 0 brgcn1 0 0 1 1 brgcn0 0 1 0 1 selection of csian serial clock (f scka division ratio) brgcan 6 0 5 0 4 0 3 0 2 0 1 brgcn1 0 brgcn0 after reset: 03h r/w address: fffffd43h, ffffd53h 6 (f scka /6) 8 (f scka /8) 16 (f scka /16) 32 (f scka /32) remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 517 v850es/kf1, v850es/kg1, v850es/kj1 csiae0 0 note 1 1 master0 0 1 p53 note 3 p54 note 2 p55 pm55 pf55 note 4 pfc55 0 pm54 note 2 pmc54 1 note 2 pmc55 1 pfc54 0 note 2 pf5 note 4 note 2 pm53 note 3 pfc53 0 note 3 pmc53 1 note 3 serial i/o shift register a0 operation operation stopped operation enabled serial clock counter operation control clear count operation sia0/p53 pin function p53/rtp03/ kr3 sia0 note 2 soa0/p54 pin function p54/rtp04/ kr4 soa0 note 3 scka0/p55 pin function p55/rtp05/ kr5 scka0 (input) scka0 (output) v850es/kg1, v850es/kj1 csiae1 0 note 1 1 master1 0 1 p910 note 3 p911 note 2 p912 pm912 pf912 note 4 pfc912 1 pm911 note 2 pmc911 1 note 2 pmc912 1 pfc911 1 note 2 pf911 note 4 note 2 pm910 note 3 pfc910 1 note 3 pmc910 1 note 3 serial i/o shift register a1 operation operation stopped operation enabled serial clock counter operation control clear count operation sia1/p910 pin function p910/a10 sia1 note 2 soa1/p911 pin function p911/a11 soa1 note 3 scka1/p912 pin function p912/a12 scka1 (input) scka1 (output) notes 1. this pin can be used for a port function or an alternate function other than the serial communication pin. 2. this pin can be used for a port function or an alternate function other than the serial communication pin only during transmiss ion (rxen bit = 0, txen bit = 1). however, the p910 to p912 pins cannot be used as the a10 to a11 pins. 3. this pin can be used for a port function or an alternate function other than the serial communication pin only during reception (rxen bit = 1, txen bit = 0). however, the p910 to p912 pins cannot be used as the a10 to a11 pins. 4. when this pin is used as an alternate function as an n-ch open-drain, set as follows. p5n: p5n bit = 1 pf5n bit = 1 pmc5n bit = 1 p9n: p9n bit = 1 pfc9n bit = 1 pf9n bit = 1 pmc9n bit = 1 remark : don't care csiaen: bit 7 of serial operation mode specification register n (csiman) mastern: bit 4 of csiman register pmxx: pmxx bit of port mode register pmcxx: pmcxx bit of port mode control register pfcxx: pfcxx bit of port function control register pxx: port output latch chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 518 (3) 1-byte transmission/reception communication operation (a) 1-byte transmission/reception when the csiaen bit and aten bit of serial operation mode specification register n (csiman) = 1, 0, respectively, if transfer data is written to serial i/o shift register an (sioan), the data is output via the soa0 pin in synchronization with the sckan pin falling edge, and then input via the sian pin in synchronization with serial clock falling edge, and stored in the sioan register in synchronization with the rising edge 1 clock later. data transmission and data reception can be performed simultaneously. if only reception is to be performed, transfer can only be started by writing a dummy value to the sioan register. when transfer of 1 byte is complete, an interrupt request signal (intcsian) is generated. in 1-byte transmission/reception, the setting of the atmn bit of csiman is invalid. be sure to read data after confirming that the tsfn bit of serial status register n (csisn) = 0. figure 17-2. 3-wire serial i/o mode timing sian sckan 12345678 di7 di6 di5 di4 di3 di2 di1 di0 soan do7 do6 do5 do4 do3 do2 do1 do0 csiafn transfer starts at falling edge of sckan pin end of transfer sioan write caution the soan pin becomes low level by an sioan write. chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 519 (b) data format in the data format, data is changed in synchronization with the sckan pin falling edge as shown below. the data length is fixed to 8 bits and the data transfer direction can be switched by the specification of the dirn bit of serial operation mode specification register n (csiman). figure 17-3. format of transmit/receive data (a) msb-first (dirn bit = 0) scka0 sia0 do7 do6 do5 do4 do3 do2 do1 do0 soa0 di7 di6 di5 di4 di3 di2 di1 di0 (b) lsb-first (dirn bit = 1) scka0 sia0 do0 do1 do2 do3 do4 do5 do6 do7 soa0 di0 di1 di2 di3 di4 di5 di6 di7 chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 520 (c) switching msb/lsb as start bit figure 17-4 shows the configuration of serial i/o shift register n (sioan) and the internal bus. as shown in the figure, msb/lsb can be read/written in reverse form. switching msb/lsb as the start bit can be specified using the dirn bit of serial operation mode specification register n (csiman). start bit switching is realized by switching the bit order for data written to sioan. the sioan shift order remains unchanged. thus, switching between msb-first and lsb-first must be performed before writing data to the shift register. figure 17-4. transfer bit order switching circuit 7 6 internal bus 1 0 lsb-first msb-first read/write gate sian shift register n (sioan) read/write gate soan sckan dq soan latch (d) transfer start serial transfer is started by setting transfer data to serial i/o shift register n (sioan) when the following two conditions are satisfied. ? serial interface csian operation control bit (csiaen) = 1 ? internal serial clock is stopped or sckan pin is high level after 8-bit serial transfer. caution if csiaen is set to 1 after data is written to sioan, transfer does not start. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request signal (intcsian) is generated. remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 521 17.4.3 3-wire serial i/o mode with automatic transmit/receive function up to 32 bytes of data can be transmitted/received without using software in the mode in which the aten bit of serial operation mode specification register n (csiman) is set to 1. after transfer is started, only data of the set number of bytes stored in ram in advance can be transmitted, and only data of the set number of bytes can be received and stored in ram. (1) register setting serial interface csian is controlled by the following six registers. serial operation mode specification register n (csiman) serial status register n (csisn) serial trigger register n (csitn) divisor selection register n (brgcan) automatic data transfer address point specification register n (adtpn) automatic data transfer interval specification register n (adtin) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 522 (a) serial operation mode specification register n (csiman) this is an 8-bit register used to control the serial transfer operation. this register can be set by an 8-bit or 1-bit memory manipulation instruction. reset input sets this register to 00h. <7> csiaen disable csian operation (soan: low level, sckan: high level) enable csian operation csiaen 0 1 csian operation enable/disable control csiman 6 aten 5 atmn 4 mastern 3 txen 2 rxen 1 dirn 0 0 1-byte transfer mode automatic transfer mode aten 0 1 automatic transfer operation enable/disable control single transfer mode (stops at address specified with adtpn register) repeat transfer mode (following transfer completion, the adtcn register is cleared to 00h and transmission starts again.) atmn 0 1 specification of automatic transfer mode slave mode (synchronized with sckan input clock) master mode (synchronized with internal clock) mastern 0 1 specification of csian master/slave mode disable transmission (soan: low level) enable transmission txen 0 1 transmission enable/disable control disable reception enable reception rxen 0 1 reception enable/disable control msb first lsb first dirn 0 1 specification of transfer data direction after reset: 00h r/w address: fffffd40h, ffffd50h when csiaen = 0, the csian unit is reset asynchronously. when csiaen = 0, the csian unit is reset, so to operate csian, first set csiaen = 1. if the csiaen bit is changed from 1 to 0, all the registers of the csian unit are initialized. to set csiaen to 1 again, first re-set the registers of the csian unit. if the csiaen bit is changed from 1 to 0, the buffer ram value is not held. also, when the csiaen bit is 0, the buffer ram cannot be accessed. when the txen bit is 0, read from the transfer buffer ram is not possible. when the rxen bit is 0, write to the transfer buffer ram is not possible. remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 523 (b) serial status register n (csisn) this is an 8-bit register used to select the input clock and to control the transfer operation of csian. this register can be set by an 8-bit or 1-bit memory manipulation instruction. reset input sets this register to 00h. however, rewriting the csisn register is prohibited when the tsfn bit is 1. 7 cksan1 f xx f xx /2 f xx /4 f xx /8 20 mhz setting prohibited 100 ns 200 ns 400 ns 16 mhz setting prohibited 125 ns 250 ns 500 ns 10 mhz 100 ns 200 ns 400 ns 800 ns cksan1 0 0 1 1 cksan0 0 1 0 1 serial clock (f scka ) selection note csisn 6 cksan0 5 0 4 0 3 0 2 0 1 0 0 tsfn csiaen bit of csiman register = 0 at reset input at completion of specified transfer when transfer has been suspended by setting atstpn bit of csitn register to 1 from transfer start to completion of specified transfer rewriting csisn is prohibited when the csiaen bit of the csiman register is 1. tsfn 0 1 transfer status after reset: 00h r/w address: fffffd41h, ffffd51h note set f scka so as to satisfy the following conditions. v dd = 4.0 to 5.5 v: f scka 10 mhz v dd = 2.7 to 4.0: f scka 5 mhz cautions 1. the tsfn bit is read-only. 2. when the tsfn bit = 1, rewriting the csiman, csisn, brgcan, adtpn, adtin, sioan registers is prohibited. however, the transfer buffer ram can be rewritten. 3. when writing to bits 1 to 5, always write 0. remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 524 (c) serial trigger register n (csitn) this is an 8-bit register used to control execution/stop of automatic data transfer. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. however, manipulate only when the aten bit of serial operation mode specification register n (csiman) is 1 (manipulation prohibited when aten bit = 0). 7 0 csitn 6 0 5 0 4 0 3 0 2 0 <1> atstpn <0> atstan normal mode stop automatic data transfer atstpn 0 1 automatic data transfer suspension even when atstpn = 1 is set, transfer does not stop until 1 byte has been transferred. 1 is held until immediately before the intcsian interrupt signal is generated. after transfer has been interrupted, the data address at which transfer stopped is stored in the adtcn register. moreover, transfer cannot be resumed from the point where it has been stopped. after reset: 00h r/w address: fffffd42h, ffffd52h normal mode start automatic data transfer atstan 0 1 automatic data transfer start even when atstan = 1, automatic data transfer does not start until 1 byte has been transferred. 1 is held until immediately before the intcsian interrupt signal is generated. remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 525 (d) divisor selection register n (brgcan) this is an 8-bit register used to control the serial transfer speed (divisor of csia input clock). this register can be set by an 8-bit memory manipulation instruction. however, when the tsfn bit of serial status register n (csisn) is 1, rewriting the brgcan register is prohibited. 7 0 brgcn1 0 0 1 1 brgcn0 0 1 0 1 selection of csian serial clock (f scka division ratio) brgcan 6 0 5 0 4 0 3 0 2 0 1 brgcn1 0 brgcn0 after reset: 03h r/w address: fffffd43h, ffffd53h 6 (f scka /6) 8 (f scka /8) 16 (f scka /16) 32 (f scka /32) remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) (e) automatic data transfer address point specification register n (adtpn) this is an 8-bit register used to specify the buffer ram address that ends transfer during automatic data transfer (aten bit of serial operation mode specification register n (csiman) = 1). this register can be set by an 8-bit memory manipulation instruction. however, when the tsfn bit of serial status register n (csisn) is 1, rewriting the adtpn register is prohibited. in the v850es/kf1, v850es/kg1, and v850es/kj1, 00h to 1fh can be specified because 32 bytes of buffer ram are incorporated. example when the adtpn register is set to 07h 8 bytes of 00h to 07h are transferred. in repeat transfer mode (atmn bit of csiman register = 1), transfer is performed repeatedly up to the address value set in adtpn register. example when 07h is transferred to the adtpn register (repeat transfer mode) transfer is repeated as 00h to 07h, 00h to 07h, ? . 7 0 adtpn 6 0 5 0 4 adtpn4 3 adtpn3 2 adtpn2 1 adtpn1 0 adtpn0 after reset: 00h r/w address: fffffd44h, ffffd54h caution be sure to set bits 5 to 7 to 0. remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 526 the relationship between buffer ram address values and the adtpn register setting values is shown below. table 17-6. relationship between buffer ram address values and adtp0 register setting values buffer ram address value adtp0 register setting value buffer ram address value adtp0 register setting value fe00h 00h fe10h 10h fe01h 01h fe11h 11h fe02h 02h fe12h 12h fe03h 03h fe13h 13h fe04h 04h fe14h 14h fe05h 05h fe15h 15h fe06h 06h fe16h 16h fe07h 07h fe17h 17h fe08h 08h fe18h 18h fe09h 09h fe19h 19h fe0ah 0ah fe1ah 1ah fe0bh 0bh fe1bh 1bh fe0ch 0ch fe1ch 1ch fe0dh 0dh fe1dh 1dh fe0eh 0eh fe1eh 1eh fe0fh 0fh fe1fh 1fh table 17-7. relationship between buffer ram address values and adtp1 register setting values buffer ram address value adtp1 register setting value buffer ram address value adtp1 register setting value fe20h 00h fe30h 10h fe21h 01h fe31h 11h fe22h 02h fe32h 12h fe23h 03h fe33h 13h fe24h 04h fe34h 14h fe25h 05h fe35h 15h fe26h 06h fe36h 16h fe27h 07h fe37h 17h fe28h 08h fe38h 18h fe29h 09h fe39h 19h fe2ah 0ah fe3ah 1ah fe2bh 0bh fe3bh 1bh fe2ch 0ch fe3ch 1ch fe2dh 0dh fe3dh 1dh fe2eh 0eh fe3eh 1eh fe2fh 0fh fe3fh 1fh chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 527 (f) automatic data transfer interval specification register n (adtin) this is an 8-bit register used to specify the interval period between 1-byte transfers during automatic data transfer (aten bit of serial operation mode specification register n (csiman) = 1). set this register when in master mode (mastern bit of csiman = 1) (setting is unnecessary in slave mode). setting in 1-byte transfer mode (aten bit of csiman = 0) is also valid. when the interval time specified by the adtin register after the end of 1-byte transfer has elapsed, an interrupt request signal (intcsian) is output. the number of clocks for the interval can be set to between 0 and 63 clocks. the specified interval time is the transfer clock (specified by divisor selection register n (brgcan)) multiplied by an integer value. example when adtin register = 03h sckan interval time of 3 clocks this register can be set by an 8-bit memory manipulation instruction. however, when the tsfn bit of serial status register n (csisn) is 1, rewriting the adtin register is prohibited. adtin after reset: 00h r/w address: fffffd45h, ffffd55h 7 0 6 0 5 adtin5 4 adtin4 3 adtin3 2 adtin2 1 adtin1 0 adtin0 remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 528 (2) automatic transmit/receive data setting (a) transmit data setting <1> write transmit data from the least significant address fa00h of buffer ram (up to fa1fh at maximum). the transmit data should be in the order from lower address to higher address. <2> set the automatic data transfer address point specification register n (adtpn) to the value obtained by subtracting 1 from the number of transmit data bytes. (b) automatic transmission/reception mode setting <1> set the csiaen bit and aten bit of serial operating mode specification register n (csiman) to 1. <2> set the rxen bit and txen bit of the csiman register to 1. <3> set a data transfer interval in automatic data transfer interval specification register n (adtin). <4> set the atstan bit of serial trigger register n (csitn) to 1. the following operations are automatically carried out when (a) and (b) are carried out. ? after the buffer ram data indicated by automatic data transfer address count register n (adtcn) is transferred to the sioan register, transmission is carried out (start of automatic transmission/reception). ? the received data is written to the buffer ram address indicated by the adtcn register. ? adtcn register is incremented and the next data transmission/reception is carried out. data transmission/reception continues until the adtcn register incremental output matches the set value of automatic data transfer address point specification register n (adtpn) (end of automatic transmission/reception). however, if the atmn bit of csiman is set to 1 (repeat mode), the adtcn register is cleared after a match between the adtpn and adtcn registers, and then repeated transmission/reception is started. ? when automatic transmission/reception is terminated, the tsfn bit is cleared to 0. remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) (3) automatic transmission/reception communication operation (a) automatic transmission/reception mode automatic transmission/reception can be performed using buffer ram. the data stored in the buffer ram is output from the soan pin via the sioan register in synchronization with the sckan pin falling edge by performing (a) and (b) in (3) automatic transmit/receive data setting . the data is then input from the sian pin via the sioan register in synchronization with the serial clock falling edge and the receive data is stored in the buffer ram in synchronization with the rising edge 1 clock later. data transfer ends if the tsfn bit of serial status register n (csisn) is set to 1 when any of the following conditions is met. chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 529 ? reset by setting the csiaen bit of the csiman register to 0 ? transfer of 1 byte is complete by setting the atstpn bit of the csitn register to 1 ? transfer of the range specified by the adtpn register is complete at this time, an interrupt request signal (intcsian) is generated except when the csiaen bit = 0. if a transfer is terminated in the middle, transfer starting from the remaining data is not possible. read automatic data transfer address count register n (adtcn) to confirm how much of the data has already been transferred, set the transfer data again, and then re-execute transfer. figure 17-5 shows the operation timing in automatic transmission/reception mode and figure 17-6 shows the operation flowchart. figure 17-7 shows the operation of internal buffer ram when 6 bytes of data are transmitted/received. figure 17-5. automatic transmission/reception mode operation timings sckan soan d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 csiafn tsfn sian d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval cautions 1. because, in the automatic transmission/reception mode, the automatic transmit/receive function writes/reads data to/from the internal buffer ram after 1-byte transmission/reception, an interval is inserted until the next transmission/reception. as the buffer ram write/read is performed at the same time as cpu processing, the interval is dependent upon the value of automatic data transfer interval specification register n (adtin) (see (4) automatic transmit/receive interval time). 2. when the tsfn bit is cleared, the soan pin becomes low level. remarks 1. csiafn: interrupt request flag tsfn: bit n of serial status register n (csisn) 2. n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 530 figure 17-6. automatic transmission/reception mode flowchart start write transmit data in internal buffer ram set adtpn to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmission/reception operation interval time in adtin set atstan to 1 write transmit data from internal buffer ram to sioan transmission/reception operation write receive data from sioan to internal buffer ram adtpn = adtcn no tsfn = 0 no end yes yes increment pointer value software execution hardware execution software execution adtpn: automatic data transfer address point specification register n adtin: automatic data transfer interval specify register n atstan: bit 0 of serial trigger register n (csitn) sioan: serial i/o shift register n adtcn: automatic data transfer address count register n tsfn: bit 0 of serial status register n (csisn) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 531 in 6-byte transmission/reception (atmn bit = 0, rxen bit = 1, txen bit = 1 in the csiman register) in automatic transmission/reception mode, internal buffer ram operates as follows. (i) before transmission/reception (see figure 17-7 (a).) when the atstan bit of serial trigger register n (csitn) is set to 1, transmit data 1 (t1) is transferred from the internal buffer ram to sioan. when transmission of the first byte is completed, receive data 1 (r1) is transferred from sioan to the buffer ram, and automatic data transfer address count register n (adtcn) is incremented. then transmit data 2 (t2) is transferred from the internal buffer ram to sioan. (ii) 4th byte transmission/reception point (see figure 17-7 (b).) transmission/reception of the third byte is completed, and transmit data 4 (t4) is transferred from the internal buffer ram to the sioan register. when transmission of the fourth byte is completed, the receive data 4 (r4) is transferred from the sioan register to the internal buffer ram, and the adtcn register is incremented. (iii) completion of transmission/reception (see figure 17-7 (c).) when transmission of the sixth byte is completed, receive data 6 (r6) is transferred from sioan register to the internal buffer ram, and the interrupt request flag (csiafn) is set (intcsian generation). figure 17-7. internal buffer ram operation in 6-byte transmission/reception (in automatic transmission/reception mode) (1/2) (a) before transmission/reception transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h receive data 1 (r1) sioan 0 csiafn 0 adtcn +1 5 adtpn remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 532 figure 17-7. internal buffer ram operation in 6-byte transmission/reception (in automatic transmission/reception mode) (2/2) (b) 4th byte transmission/reception receive data 6 (r6) receive data 5 (r5) receive data 4 (r4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h receive data 4 (r4) sioan 0 csiafn 3 adtcn +1 5 adtpn (c) completion of transmission/reception receive data 6 (r6) receive data 5 (r5) receive data 4 (r4) receive data 3 (r3) receive data 2 (r2) receive data 1 (r1) fa1fh fa05h fa00h sioan 1 csiafn 5 adtcn 5 adtpn remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 533 (b) automatic transmission mode in this mode, the specified number of 8-bit unit data are transmitted. serial transfer is started when the atstan bit of serial trigger register n (csitn) is set to 1 while the csiaen, aten, and txean bits of serial operating mode specification register n (csiman) are set to 1. when the final byte has been transmitted, an interrupt request flag (csiafn) is set. however, judge the termination of automatic transmission and reception, not by the intcsian signal but by the tsfn bit of serial status register n (csisn). figure 17-8 shows the automatic transmission mode operation timing, and figure 17-9 shows the operation flowchart. figure 17-10 shows the operation of the internal buffer ram when 6 bytes of data are transmitted or received. figure 17-8. automatic transmission mode operation timing sckan soan d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 csiafn tsfn interval cautions 1. because, in the automatic transmission mode, the automatic transmit/receive function reads data from the internal buffer ram after 1-byte transmission, an interval is inserted until the next transmission. as the buffer ram read is performed at the same time as cpu processing, the interval is dependent upon the value of automatic data transfer interval specification register n (adtin) (see (6) automatic transmit/receive interval time). 2. when the tsfn bit is cleared, the soan pin becomes low level. remarks 1. csiafn: interrupt request flag tsfn: bit 0 of serial status register n (csisn) 2. n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 534 figure 17-9. automatic transmission mode flowchart start write transmit data in internal buffer ram set adtpn to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmission/reception operation interval time in adtin set atstan to 1 write transmit data from internal buffer ram to sioan transmission operation adtpn = adtcn no tsfn = 0 no end yes yes increment pointer value software execution hardware execution software execution adtpn: automatic data transfer address point specification register n adtin: automatic data transfer interval specification register n atstan: bit 0 of serial trigger register n (csitn) sioan: serial i/o shift register n adtcn: automatic data transfer address count register n tsfn: bit 0 of serial status register n (csisn) remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 535 in 6-byte transmission (atmn = 0, rxen bit = 0, txen bit = 1, ate0 bit = 1) in automatic transmission mode, internal buffer ram operates as follows. (i) before transmission (see figure 17-10 (a).) when the atstan bit of serial trigger register n (csitn) is set to 1, transmit data 1 (t1) is transferred from the internal buffer ram to sioan. when transmission of the first byte is completed, automatic data transfer address count register n (adtcn) is incremented. then transmit data 2 (t2) is transferred from the internal buffer ram to the sioan register. (ii) 4th byte transmission point (see figure 17-10 (b).) transmission of the third byte is completed, and transmit data 4 (t4) is transferred from the internal buffer ram to the sioan register. when transmission of the fourth byte is completed, the adtcn register is incremented. (iii) completion of transmission (see figure 17-10 (c).) when transmission of the sixth byte is completed, the interrupt request flag (csiafn) is set (intcsian signal generation). figure 17-10. internal buffer ram operation in 6-byte transmission (in automatic transmission mode) (1/2) (a) before transmission transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioan 0 csiafn 0 adtcn +1 5 adtpn remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 536 figure 17-10. internal buffer ram operation in 6-byte transmission (in automatic transmission mode) (2/2) (b) 4th byte transmission point transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioan 0 csiafn 3 adtcn +1 5 adtpn (c) completion of transmission transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioan 1 csiafn 5 adtcn 5 adtpn remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 537 (c) repeat transmission mode in this mode, data stored in the internal buffer ram is transmitted repeatedly. serial transfer is started when the atstan bit of serial trigger register n (csitn) is set to 1 while the csiaen, aten, atmn, and txen bits of serial operating mode specification register n (csiman) are set to 1. unlike the basic transmission mode, after the final byte (data in address fa1fh) has been transmitted, the interrupt request signal (intcsian) is not generated, the automatic data transfer address count register n (adtcn) is reset to 0, and the internal buffer ram contents are transmitted again. the repeat transmission mode operation timing is shown in figure 17-11, and the operation flowchart in figure 17-12. figure 17-13 shows the operation of the internal buffer ram when 6 bytes of data are transmitted in the repeat transmission mode. figure 17-11. repeat transmission mode operation timing d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval interval d7 d6 d5 sckan soan caution because, in the repeat transmission mode, a read is performed on the buffer ram after the transmission of one byte, the interval is included in the period up to the next transmission. as the buffer ram read is performed at the same time as cpu processing, the interval is dependent upon automatic data transfer interval specification register n (adtin) (see (4) automatic transmit/receive interval time). remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 538 figure 17-12. repeat transmission mode flowchart start write transmit data in internal buffer ram set adtpn to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmission/reception operation interval time in adtin set atstan to 1 write transmit data from internal buffer ram to sioan transmission operation adtpn = adtcn no yes increment pointer value software execution hardware execution reset adtcn to 0 adtpn: automatic data transfer address point specification register n adtin: automatic data transfer interval specification register n atstan: bit 0 of serial trigger register n (csitn) sioan: serial i/o shift register n adtcn: automatic data transfer address count register n remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 539 in 6-byte transmission (atmn bit = 1, rxean bit = 0, txean bit = 1, aten bit = 1) in repeat transmission mode, internal buffer ram operates as follows. (i) before transmission (see figure 17-13 (a).) when the atstan bit of serial trigger register n (csitn) is set to 1, transmit data 1 (t1) is transferred from the internal buffer ram to the sioan register. when transmission of the first byte is completed, automatic data transfer address count register n (adtcn) is incremented. then transmit data 2 (t2) is transferred from the internal buffer ram to the sioan register. (ii) upon completion of transmission of 6 bytes (see figure 17-13 (b).) when transmission of the sixth byte is completed, the interrupt request signal (intcsian) is not generated. the adtcn register is reset to 0. (iii) 7th byte transmission point (see figure 17-13 (c).) transmit data 1 (t1) is transferred from the internal buffer ram to sioan register again. when transmission of the first byte is completed, the adtcn register is incremented. then transmit data 2 (t2) is transferred from the internal buffer ram to the sioan register. figure 17-13. internal buffer ram operation in 6-byte transmission (in repeat transmission mode) (1/2) (a) before transmission transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioan 0 csiafn 0 adtcn +1 5 adtpn remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 540 figure 17-13. internal buffer ram operation in 6-byte transmission (in repeat transmission mode) (2/2) (b) upon completion of transmission of 6 bytes transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioan 0 csiafn 5 adtcn 5 adtpn (c) 7th byte transmission point transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) fa1fh fa05h fa00h sioan 0 csiafn 0 adtcn +1 5 adtpn remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 541 (d) data format in the data format, data is changed in synchronization with the sckan pin falling edge as shown below. the data length is fixed to 8 bits and the data transfer direction can be switched by the specification of the dirn bit of serial operation mode specification register n (csiman). figure 17-14. format of csian transmit/receive data (a) msb-first (dirn bit = 0) sckan sian do7 do6 do5 do4 do3 do2 do1 do0 soan di7 di6 di5 di4 di3 di2 di1 di0 (b) lsb-first (dirn bit = 1) sckan sian do0 do1 do2 do3 do4 do5 do6 do7 soan di0 di1 di2 di3 di4 di5 di6 di7 remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 542 (e) automatic transmission/reception suspension and restart automatic transmission/reception can be temporarily suspended by setting the atstpn bit of serial trigger register n (csitn) to 1. during 8-bit data transfer, the transmission/reception is not suspended. it is suspended upon completion of 8-bit data transfer. when suspended, the tsfn bit of serial status register n (csisn) is set to 0 after transfer of the 8th bit, and all the port pins that function alternately as serial interface pins are set to the port mode. to restart automatic transmission/reception, set the atstan bit of the csitn register to 1. the remaining data can be transmitted in this way. cautions 1. if the halt instruction is executed during automatic transmission/reception, transfer is suspended and the halt mode is set if during 8-bit data transfer. when the halt mode is cleared, automatic transmission/reception is restarted from the suspended point. 2. when suspending automatic transmission/reception, do not change the operating mode to 3-wire serial i/o mode while the tsfn bit = 1. figure 17-15. automatic transmission/reception suspension and restart sckan soan d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sian d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 restart command atstan = 1 suspend atstpn = 1 (suspend command) atstpn: bit 1 of serial trigger register n (csitn) atstan: bit 0 of csitn remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) chapter 17 clocked serial interface a (csia) with automatic transmit/receive function user ? s manual u15862ej3v0ud 543 (4) automatic transmit/receive interval time when using the automatic transmit/receive function, the read/write operations from/to the internal buffer ram are performed after transmitting/receiving one byte. therefore, an interval is inserted before the next transmit/receive operation. since the read/write operations from/to the buffer ram are performed in parallel with the cpu processing when using the automatic transmit/receive function by the internal clock, the interval depends on the value which is set in the automatic data transfer interval specification register n (adtin). figure 17-16. automatic data transmit/receive interval time sckan soan d7d6d5d4d3d2d1d0 d7d6d5d4d3d2d1d0 csiafn sian d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval acsiif: interrupt request flag remark n = 0 (v850es/kf1) n = 0, 1 (v850es/kg1, v850es/kj1) 544 user?s manual u15862ej3v0ud chapter 18 i 2 c bus to use the i 2 c bus function, set the p38/sda0, p39/scl0, p80/sda1, and p81/scl1 pins to n-ch open drain output. the number of i 2 c bus channels incorporated differs as follows depending on the product. product name v850es/kf1 v850es/kg1 v850es/kj1 number of channels 1 channel (i 2 c0) 2 channels (i 2 c0, i 2 c1) the products with an on-chip i 2 c bus are shown below. v850/kf1: pd703208y, 703209y, 703210y, 70f3210y v850/kg1: pd703212y, 703213y, 703214y, 70f3214y v850/kj1: pd703216y, 703217y, 70f3217y 18.1 selecting uart2 or i 2 c1 mode uart2 and i 2 c1 of the v850es/kj1 share pins, and therefore these interfaces cannot be used at the same time. select uart2 or i 2 c1 in advance by using the port 8 mode control register (pmc8) and port 8 function control register (pfc8) (refer to 4.3.8 port 8 ). caution uart2 or i 2 c1 transmission/reception operations are not guaranteed if the mode is changed during transmission or reception. be sure to disable the operation of the unit that is not used. figure 18-1. selecting mode of uart2 or i 2 c1 7 0 pmc8 6 0 5 0 4 0 3 0 2 0 1 pmc81 0 pmc80 7 0 pfc8 6 0 5 0 4 0 3 0 2 0 1 pfc81 0 pfc80 after reset: 00h r/w address: fffff450h after reset: 00h r/w address: fffff470h pfc8n pmc8n operation mode 0 0 port i/o mode 0 1 uart2 mode 1 0 port i/o mode 11i 2 c1 mode remark n = 0, 1 chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 545 18.2 features the i 2 c0 and i 2 c1 have the following two modes. operation stop mode i 2 c (inter ic) bus mode (multimaster supported) (1) operation stop mode this mode is used when serial transfers are not performed. it can therefore be used to reduce power consumption. (2) i 2 c bus mode (multimaster support) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock (scln) line and a serial data bus (sdan) line. this mode complies with the i 2 c bus format and the master device can output ? start condition ? , ? data ? , and ? stop condition ? data to the slave device, via the serial data bus. the slave device automatically detects these received data by hardware. this function can simplify the part of application program that controls the i 2 c bus. since the scln and sdan pins are n-ch open drain outputs, the i 2 cn requires pull-up resistors for the serial clock line and the serial data bus line. remark n = 0 (v850es/kf1, v850es/kg1) n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 546 user ? s manual u15862ej3v0ud figure 18-2. block diagram of i 2 cn internal bus iic status register n (iicsn) iic control register n (iiccn) slave address register n (svan) noise eliminator noise eliminator match signal iic shift register n (iicn) so latch iicen d q set clear cln1, cln0 sdan scln n-ch open- drain output n-ch open- drain output data hold time correction circuit ack output circuit wakeup controller ack detector stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller prescaler intiicn lreln wreln spien wtimn acken sttn sptn mstsn aldn excn coin trcn ackdn stdn spdn start condition detector internal bus cldn dadn smcn dfcn cln1 cln0 clxn stcfn iicbsyn iic clock selection register n (iiccln) iic function expansion register n (iicxn) iic flag register n (iicfn) stcenn iicrsvn start condition generator bus status detector f xx remark n = 0 (v850es/kf1, v850es/kg1) n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 547 a serial bus configuration example is shown below. figure 18-3. serial bus configuration example using i 2 c bus sda scl sda +v dd +v dd scl sda scl slave cpu3 address 3 sda scl slave ic address 4 sda scl slave ic address n master cpu1 slave cpu1 address 1 serial data bus serial clock master cpu2 slave cpu2 address 2 chapter 18 i 2 c bus 548 user ? s manual u15862ej3v0ud 18.3 configuration i 2 cn includes the following hardware. table 18-1. configuration of i 2 cn item configuration registers iic shift registers 0 and 1 (iic0, iic1) slave address registers 0 and 1 (sva0, sva1) control registers iic control registers 0 and 1 (iicc0, iicc1) iic status registers 0 and 1 (iics0, iics1) iic flag registers 0, 1 (iiccf0, iiccf1) iic clock selection registers 0 and 1 (iiccl0, iiccl1) iic function expansion registers 0 and 1 (iicx0, iicx1) remark n = 0 (v850es/kf1, v850es/kg1) n = 0, 1 (v850es/kj1) (1) iic shift registers 0 and 1 (iic0, iic1) iicn is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8-bit serial data. iicn can be used for both transmission and reception. write and read operations to iicn are used to control the actual transmit and receive operations. iicn is set by an 8-bit memory manipulation instruction. reset input clears iic0 and iic1 to 00h. (2) slave address registers 0 and 1 (sva0, sva1) svan sets local addresses when in slave mode. svan is set by an 8-bit memory manipulation instruction. reset input clears sva0 and sva1 to 00h. (3) so latch the so latch is used to retain the sdan pin ? s output level. (4) wakeup controller this circuit generates an interrupt request when the address received by this register matches the address value set to slave address register n (svan) or when an extension code is received. (5) clock selector this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was sent or received. chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 549 (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiicn). an i 2 c interrupt is generated following either of two triggers. ? eighth or ninth clock of the serial clock (set by wtimn bit note ) ? interrupt request generated when a stop condition is detected (set by spien bit note ) note wtimn bit: bit 3 of iic control register n (iiccn) spien bit: bit 4 of iic control register n (iiccn) (8) serial clock controller in master mode, this circuit generates the clock output via the scln pin from a sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack output circuit, stop condition detector, start condition detector, and ack detector these circuits are used to output and detect various control signals. (11) data hold time correction circuit this circuit generates the hold time for data corresponding to the falling edge of the serial clock. (12) start condition generator this circuit generates a start condition when the sttn bit is set. however, in the communication reservation disabled status (iicrsvn = 1), when the bus is not released (iicbsyn = 1), start condition requests are ignored and the stcfn flag is set. (13) bus status detector this circuit detects whether or not the bus is released by detecting start conditions and stop conditions. however, as the bus status cannot be detected immediately following operation, the initial status is set by the stcenn bit. chapter 18 i 2 c bus 550 user ? s manual u15862ej3v0ud 18.4 control registers i 2 c0 and i 2 c1 are controlled by the following registers. iic control registers 0, 1 (iicc0, iicc1) iic status registers 0, 1 (iics0, iics1) iic flag registers 0, 1 (iicf0, iicf1) iic clock selection registers 0, 1 (iiccl0, iiccl1) iic function expansion registers 0, 1 (iicx0, iicx1) the following registers are also used. iic shift registers 0, 1 (iic0, iic1) slave address registers 0, 1 (sva0, sva1) (1) iic control registers 0, 1 (iicc0, iicc1) iiccn is used to enable/disable i 2 cn operations, set wait timing, and set other i 2 c operations. iiccn can be set by an 8-bit or 1-bit memory manipulation instruction (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). reset input clears iiccn to 00h. caution in i 2 c0, i 2 c1 bus mode, set the port 3 mode register (pm3) and port 8 mode register (pm8) as follows. in addition, set each output latch to 0. ? set p38 (sda0) to output mode (pm38 = 0) ? set p39 (scl0) to output mode (pm39 = 0) ? set p80 (sda1) to output mode (pm80 = 0) ? set p81 (scl1) to output mode (pm81 = 0) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 551 (1/4) after reset: 00h r/w address: fffffd82h, fffffd92h <7><6>543210 iiccn iicen lreln wreln spien wtimn acken sttn sptn (n = 0, 1) iicen i 2 cn operation enable/disable specification 0 stops operation. presets iic status register n (iicsn). stops internal operation. 1 enables operation. condition for clearing (iicen = 0) condition for setting (iicen = 1) ? cleared by instruction ? when reset is input ? set by instruction lreln exit from communications 0 normal operation 1 this exits from the current communications operation and sets standby mode. this setting is automatically cleared after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scln and sdan lines are set to high impedance. the following flags are cleared. ? stdn ? ackdn ? trcn ? coin ? excn ? mstsn ? sttn ? sptn the standby mode following exit from communications remains in effect until the following communications entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code reception occurs after the start condition. condition for clearing (lreln = 0) note condition for setting (lreln = 1) ? automatically cleared after execution ? when reset is input ? set by instruction note this flag ? s signal is invalid when iicen = 0. remark stdn: bit 1 of iic status register n (iicsn) ackdn: bit 2 of iic status register n (iicsn) trcn: bit 3 of iic status register n (iicsn) coin: bit 4 of iic status register n (iicsn) excn: bit 5 of iic status register n (iicsn) mstsn: bit 7 of iic status register n (iicsn) chapter 18 i 2 c bus 552 user ? s manual u15862ej3v0ud (2/4) wreln wait cancellation control 0 does not cancel wait 1 cancels wait. this setting is automatically cleared after wait is canceled. condition for clearing (wreln = 0) note condition for setting (wreln = 1) ? automatically cleared after execution ? when reset is input ? set by instruction spien enable/disable generation of interrupt request when stop condition is detected 0 disable 1 enable condition for clearing (spien = 0) note condition for setting (spien = 1) ? cleared by instruction ? when reset is input ? set by instruction wtimn control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock ? s falling edge. master mode: after output of eight clo cks, clock output is set to low level and wait is set. slave mode: after input of eight clo cks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock ? s falling edge. master mode: after output of nine clo cks, clock output is set to low level and wait is set. slave mode: after input of nine clo cks, the clock is set to low level and wait is set for master device. this bit ? s setting is invalid during an address transfer and is valid as the transfer is completed. when in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ack signal is issued. when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtimn = 0) note condition for setting (wtimn = 1) ? cleared by instruction ? when reset is input ? set by instruction note this flag ? s signal is invalid when iicen = 0. chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 553 (3/4) acken acknowledge control 0 disable acknowledge. 1 enable acknowledge. during the ninth clock period, the sdan line is set to low level. however, the ack is invalid during address transfers and is valid when excn = 1. condition for clearing (acken = 0) note condition for setting (acken = 1) ? cleared by instruction ? when reset is input ? set by instruction sttn start condition trigger 0 does not generate a start condition. 1 when bus is released (in stop mode): generates a start condition (for starting as master). the sdan line is changed from high level to low level and then the start condition is generated. next, after the rated amount of time has elapsed, scln is changed to low level. when bus is not used: ? when communication reservation function is enabled (iicrsvn = 0) functions as the start condition reservation flag. when set, automatically generates a start condition after the bus is released. ? when communication reservation function is disabled (iicrsvn = 1) the stcfn flag is set. no start condition is generated. in the wait state (when master device): generates a restart condition after releasing the wait. cautions concerning set timing for master reception: cannot be set during transfer. can be set only when acken has been set to 0 and slave has been notified of final reception. for master transmission: a start condition cannot be generated normally during the ackn period. set during the wait period. ? cannot be set at the same time as sptn condition for clearing (sttn = 0) condition for setting (sttn = 1) ? cleared by instruction ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? when lreln = 1 ? when iicen = 0 ? cleared when reset is input ? set by instruction note this flag ? s signal is invalid when iicen = 0. remarks 1. bit 1 (sttn) is 0 if it is read after data setting. 2. iicrsvn: bit 0 of iic flag register n (iicfn) stcfn: iicrsvn: bit 7 of iic flag register n (iicfn) chapter 18 i 2 c bus 554 user ? s manual u15862ej3v0ud (4/4) sptn stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (termination of master device ? s transfer). after the sdan line goes to low level, either set the scln line to high level or wait until it goes to high level. next, after the rated amount of time has elapsed, the sdan line is changed from low level to high level and a stop condition is generated. cautions concerning setting timing for master reception: cannot be set during transfer. can be set only when acken has been set to 0 and during the wait period after slave has been notified of final reception. for master transmission: a stop condition cannot be generated normally during the ackn period. set during the wait period. ? cannot be set at the same time as sttn. ? sptn can be set only when in master mode note ? when wtimn has been set to 0, if sptn is set during the wait period that follows output of eight clo cks, note that a stop condition will be generated during the high-level period of the ninth clock. when a ninth clock must be output, wtimn should be changed from 0 to 1 during the wait period following output of eight clocks, and sptn should be set during the wait period that follows output of the ninth clock. condition for clearing (sptn = 0) condition for setting (sptn = 1) ? cleared by instruction ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? when lreln = 1 ? when iicen = 0 ? cleared when reset is input ? set by instruction note set sptn only in master mode. however, sptn must be set and a stop condition generated before the first stop condition is detected following the switch to operation enable status. for details, see 18.5 cautions . caution when bit 3 (trcn) of iic status register n (iicsn) is set to 1, wreln is set during the ninth clock and wait is canceled, after which trcn is cleared and the sdan line is set to high impedance. remark bit 0 (sptn) is 0 if it is read after data setting. chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 555 (2) iic status registers 0, 1 (iics0, iics1) iicsn indicates the status of the i 2 cn bus. iicsn can be set by an 8-bit or 1-bit memory manipulation instruction. iicsn is a read-only register (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). reset input sets iicsn to 00h. (1/3) after reset: 00h r address: fffffd86h, fffffd96h 76543210 iicsn mstsn aldn excn coin trcn ackdn stdn spdn (n = 0, 1) mstsn master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (mstsn = 0) condition for setting (mstsn = 1) ? when a stop condition is detected ? when aldn = 1 ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? when reset is input ? when a start condition is generated aldn detection of arbitration loss 0 this status means either that there was no arbitration or that the arbitration result was a ? win ? . 1 this status indicates the arbitration result was a ? loss ? . mstsn is cleared. condition for clearing (aldn = 0) condition for setting (aldn = 1) ? automatically cleared after iicsn is read note ? when iicen changes from 1 to 0 ? when reset is input ? when the arbitration result is a ? loss ? . note this register is also cleared when a bit manipulation instruction is executed for bits other than iicsn. remark lreln: bit 6 of iic control register n (iiccn) iicen: bit 7 of iic control register n (iiccn) chapter 18 i 2 c bus 556 user ? s manual u15862ej3v0ud (2/3) excn detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (excn = 0) condition for setting (excn = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? when reset is input ? when the higher four bits of the received address data is either ? 0000 ? or ? 1111 ? (set at the rising edge of the eighth clock). coin detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coin = 0) condition for setting (coin = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? when reset is input ? when the received address matches the local address (svan) (set at the rising edge of the eighth clock). trcn detection of transmit/receive status 0 receive status (other than transmit status). the sdan line is set for high impedance. 1 transmit status. the value in the so latch is enabled for output to the sdan line (valid starting at the falling edge of the first byte ? s ninth clock). condition for clearing (trcn = 0) condition for setting (trcn = 1) ? when a stop condition is detected ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? cleared by wreln = 1 note ? when aldn changes from 0 to 1 ? when reset is input master ? when ? 1 ? is output to the first byte ? s lsb (transfer direction specification bit) slave ? when a start condition is detected when not used for communication master ? when a start condition is generated slave ? when ? 1 ? is input by the first byte ? s lsb (transfer direction specification bit) note trcn is cleared and sdan line become high impedance when bit 5 (wreln) of iic control register n (iiccn) is set and wait state is released at ninth clock with bit 3 (trcn) of iic status register n (iicsn) = 1. remark wreln: bit 5 of iic control register n (iiccn) lreln: bit 6 of iic control register n (iiccn) iicen: bit 7 of iic control register n (iiccn) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 557 (3/3) ackdn detection of ack 0 ack was not detected. 1 ack was detected. condition for clearing (ackdn = 0) condition for setting (ackdn = 1) ? when a stop condition is detected ? at the rising edge of the next byte ? s first clock ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? when reset is input ? after the sdan line is set to low level at the rising edge of the scln ? s ninth clock stdn detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect condition for clearing (stdn = 0) condition for setting (stdn = 1) ? when a stop condition is detected ? at the rising edge of the next byte ? s first clock following address transfer ? cleared by lreln = 1 ? when iicen changes from 1 to 0 ? when reset is input when a start condition is detected spdn detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master device ? s communication is terminated and the bus is released. condition for clearing (spdn = 0) condition for setting (spdn = 1) ? at the rising edge of the address transfer byte ? s first clock following setting of this bit and detection of a start condition ? when iicen changes from 1 to 0 ? when reset is input when a stop condition is detected remark lreln: bit 6 of iic control register n (iiccn) iicen: bit 7 of iic control register n (iiccn) chapter 18 i 2 c bus 558 user ? s manual u15862ej3v0ud (3) iic flag registers 0, 1 (iicf0, iicf1) iicfn is used for i 2 cn control and as flags. iicfn is set with an 8-bit or 1-bit memory manipulation instruction (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). reset input sets iicfn to 00h. (1/2) 7 stcfn condition for clearing (stcfn = 0) clearing by setting sttn = 1 reset input condition for setting (stcfn = 1) clearing of sttn when communication reservation is disabled (iicrsvn = 1). stcfn 0 1 generate start condition clear sttn flag sttn clear flag iicfn (n = 0, 1) 6 iicbsyn 5 0 4 0 3 0 2 0 1 stcenn 0 iicrsvn after reset: 00h r/w note address: fffffd8ah, fffffd9ah condition for clearing (iicbsyn = 0) detection of stop condition reset input setting conditions (iicbsyn = 1) detection of start condition setting of iicen when stcenn = 0 iicbsyn 0 1 bus release status bus communication status i 2 cn bus status flag note bits 6 and 7 are read-only bits. remark sttn: bit 1 of iic control register n (iiccn) iicen: bit 7 of iic control register n (iiccn) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 559 (2/2) condition for clearing (stcen = 0) detection of start condition reset input condition for setting (stcen = 1) setting by instruction stcenn 0 1 after operation is enabled (iicen = 1), generates a start condition upon detection of a stop condition. after operation is enabled (iicen = 1), generates a start condition without detecting a stop condition. initial start enable trigger cautions 1. write to the stcenn bit only when the operation is stopped (iicen = 0). 2. as the bus release status (iicbsy = 0) is recognized regardless of the actual bus status when stcenn = 1, when generating the first start condition (sttn = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. remark sttn: bit 1 of iic control register n (iiccn) iicen: bit 7 of iic control register n (iiccn) condition for clearing (iicrsvn = 0) clearing by instruction reset input condition for setting (iicrsvn = 1) setting by instruction iicrsvn 0 1 enable communication reservation disable communication reservation communication reservation function disable bit caution write to the iicrsvn bit only when the operation is stopped (iicen = 0). chapter 18 i 2 c bus 560 user ? s manual u15862ej3v0ud (4) iic clock selection registers 0, 1 (iiccl0, iiccl1) iiccln is used to set the transfer clock for the i 2 cn bus. iiccln can be set by an 8-bit or 1-bit memory manipulation instruction. bits smcn, cln1 and cln0 are set in combination with clxn bit of iic function expansion register n (iicxn) (see 18.4 (6) i 2 cn transfer clock setting method ) (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). reset input clears iiccln to 00h. after reset: 00h r/w note address: fffffd84h, fffffd94h 76543210 iiccln 0 0 cldn dadn smcn dfcn cln1 cln0 (n = 0, 1) cldn detection of scln line level (valid only when iicen = 1) 0 scln line was detected at low level. 1 scln line was detected at high level. condition for clearing (cldn = 0) condition for setting (cldn = 1) ? when the scln line is at low level ? when iicen = 0 ? when reset is input ? when the scln line is at high level dadn detection of sdan line level (valid only when iicen = 1) 0 sdan line was detected at low level. 1 sdan line was detected at high level. condition for clearing (dadn = 0) condition for setting (dadn = 1) ? when the sdan line is at low level ? when iicen = 0 ? when reset is input ? when the sdan line is at high level smcn operation mode switching 0 operates in standard mode. 1 operates in high-speed mode. dfcn digital filter operation control 0 digital filter off. 1 digital filter on. digital filter can be used only in high-speed mode. in high-speed mode, the transfer clock does not vary regardless of dfcn switching (on/off). note bits 4 and 5 are read only bits. remark iicen: bit 7 of iic control register n (iiccn) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 561 (5) iic function expansion registers 0, 1 (iicx0, iicx1) these registers set the function expansion of i 2 cn (valid only in high-speed mode). iicxn is set with a 1-bit or 8-bit memory manipulation instruction. set the clxn bit in combination with the smcn, cln1, and cln0 bits of iic clock selection register n (iiccln) (see 18.4 (6) i 2 cn transfer clock setting method ) (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). reset input clears these registers to 00h. after reset: 00h r/w address: fffffd85h, fffffd95h 76543210 iicxn0000000clxn (n = 0, 1) (6) i 2 cn transfer clock setting method the i 2 cn transfer clock frequency (f scl ) is calculated using the following expression (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). f scl = 1/(m t + t r + t f ) m = 12, 24, 48, 54, 86, 88, 172, 198 (see table 18-2 selection clock setting .) t: 1/f xx t r : scln rise time t f : scln fall time for example, the i 2 cn transfer clock frequency (f scl ) when f xx = 20 mhz, m = 198, t r = 200 ns, and t f = 50 ns is calculated using following expression. f scl = 1/(198 50 ns + 200 ns + 50 ns) ? 98.5 khz m x t + t r + t f m/2 x t t f t r m/2 x t scln scln inversion scln inversion scln inversion the selection clock is set using a combination of the smcn, cln1, and cln0 bits of iic clock selection register n (iiccln) and the clxn bit of iic function expansion register n (iicxn). chapter 18 i 2 c bus 562 user ? s manual u15862ej3v0ud table 18-2. selection clock setting iicxn iiccln bit 0 bit 3 bit 1 bit 0 clxn smcn cln1 cln0 selection clock transfer clock (f xx /m) settable internal system clock frequency (f xx ) range operation mode 0000f xx /2 f xx /88 4.0 mhz to 8.38 mhz 0001f xx /2 f xx /172 8.38 mhz to 16.76 mhz 0010f xx f xx /86 4.19 mhz to 8.38 mhz 0011f xx /3 f xx /198 16.0 mhz to 19.8 mhz normal mode (smcn = 0) 010xf xx /2 f xx /48 8 mhz to 16.76 mhz 0110f xx f xx /24 4 mhz to 8.38 mhz 0111f xx/ 3f xx /54 16 mhz to 20 mhz high-speed mode (smcn = 1) 1 0 x x setting prohibited 110xf xx /2 f xx /24 8.00 mhz to 8.38 mhz 1110f xx f xx /12 4.00 mhz to 4.19 mhz normal mode (smcn = 0) 1 1 1 1 setting prohibited remarks 1. n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) 2. x: don ? t care (7) iic shift registers 0, 1 (iic0, iic1) iicn is used for serial transmission/reception (shift operations) that is synchronized with the serial clock. it can be read from or written to in 8-bit units, but data should not be written to iicn during a data transfer (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). after reset: 00h r/w address: fffffd80h, fffffd90h 7654321<0> iicn (n = 0, 1) (8) slave address registers 0, 1 (sva0, sva1) svan holds the i 2 c bus ? s slave addresses. it can be read from or written to in 8-bit units, but bit 0 should be fixed as 0. after reset: 00h r/w address: fffffd83h, fffffd93h 76543210 svan 0 (n = 0, 1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 563 18.5 functions 18.5.1 pin configuration the serial clock pin (scln) and serial data bus pin (sdan) are configured as follows (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). scln .............. this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. sdan .............. this pin is used for serial data input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. since outputs from the serial clock line and the serial data bus line are n-ch open-drain outputs, an external pull- up resistor is required. figure 18-4. pin configuration diagram v dd scln sdan scln sdan v dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device chapter 18 i 2 c bus 564 user ? s manual u15862ej3v0ud 18.6 i 2 c bus definitions and control methods the following section describes the i 2 c bus ? s serial data communication format and the signals used by the i 2 c bus. the transfer timing for the ? start condition ? , ? data ? , and ? stop condition ? output via the i 2 c bus ? s serial data bus is shown below. figure 18-5. i 2 c bus?s serial data transfer timing 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 scln sdan start condition address r/w ack data data stop condition ack ack the master device outputs the start condition, slave address, and stop condition. the acknowledge signal (ack) can be output by either the master or slave device (normally, it is output by the device that receives 8-bit data). the serial clock (scln) is continuously output by the master device. however, in the slave device, the scln ? s low-level period can be extended and a wait can be inserted (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). 18.6.1 start condition a start condition is met when the scln pin is at high level and the sdan pin changes from high level to low level. the start conditions for the scln pin and sdan pin are signals that the master device outputs to the slave device when starting a serial transfer. the slave device includes hardware for detecting start conditions (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). figure 18-6. start conditions h scln sdan a start condition is output when bit 1 (sttn) of iic control register n (iiccn) is set to 1 after a stop condition has been detected (spdn: bit 0 = 1 in the iic status register n (iicsn)). when a start condition is detected, bit 1 of iicsn (stdn) is set to 1. chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 565 18.6.2 addresses the 7 bits of data that follow the start condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines. therefore, each slave device connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in slave address register n (svan). if the address data matches the svan values, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). figure 18-7. address address scln 1 sdan intiicn note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w note the interrupt request signal (intiicn) is generated if a local address or extension code is received during slave device operation. remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) the slave address and the eighth bit, which specifies the transfer direction as described in (3) transfer direction specification below, are together written to the iic shift register (iicn) and are then output. received addresses are written to iicn. the slave address is assigned to the higher 7 bits of iicn. chapter 18 i 2 c bus 566 user ? s manual u15862ej3v0ud 18.6.3 transfer direction specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. when this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. figure 18-8. transfer direction specification scln 1 sdan intiicn 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note note the interrupt request signal (intiicn) is generated if a local address or extension code is received during slave device operation. remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 567 18.6.4 acknowledge signal (ack) the acknowledge signal (ack) is used by the transmitting and receiving devices to confirm serial data reception. the receiving device returns one ack signal for each 8 bits of data it receives. the transmitting device normally receives an ack signal after transmitting 8 bits of data. however, when the master device is the receiving device, it does not output an ack signal after receiving the final data to be transmitted. the transmitting device detects whether or not an ack signal is returned after it transmits 8 bits of data. when an ack signal is returned, the reception is judged as normal and processing continues. if the slave device does not return an ack signal, the master device outputs either a stop condition or a restart condition and then stops the current transmission. failure to return an ack signal may be caused by the following two factors. (a) reception was not performed normally. (b) the final data was received. when the receiving device sets the sdan line to low level during the ninth clock, the ack signal becomes active (normal receive response). when bit 2 (acken) of iic control register n (iiccn) is set to 1, automatic ack signal generation is enabled (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). transmission of the eighth bit following the 7 address data bits causes bit 3 (trcn) of iic status register n (iicsn) to be set. when this trcn bit ? s value is 0, it indicates receive mode. therefore, acken should be set to 1 (n = 0, 1). when the slave device is receiving (when trcn = 0), if the slave device does not need to receive any more data after receiving several bytes, setting acken to 0 will prevent the master device from starting transmission of the subsequent data. similarly, when the master device is receiving (when trcn = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, setting acken to 0 will prevent the ack signal from being returned. this prevents the msb data from being output via the sdan line (i.e., stops transmission) during transmission from the slave device. figure 18-9. ack signal scln 1 sdan 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) when the local address is received, an ack signal is automatically output in synchronization with the falling edge of the scln ? s eighth clock regardless of the acken value. no ack signal is output if the received address is not a local address (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). the ack signal output method during data reception is based on the wait timing setting, as described below. when 8-clock wait is selected: ack signal is output at the falling edge of the scln ? s eighth clock if acken is set to 1 before wait cancellation. when 9-clock wait is selected: ack signal is automatically output at the falling edge of the scln ? s eighth clock if acken has already been set to 1. chapter 18 i 2 c bus 568 user ? s manual u15862ej3v0ud 18.6.5 stop condition when the scln pin is at high level, changing the sdan pin from low level to high level generates a stop condition (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). a stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed. the slave device includes hardware that detects stop conditions. figure 18-10. stop condition h scln sdan remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) a stop condition is generated when bit 0 (sptn) of iic control register n (iiccn) is set to 1. when the stop condition is detected, bit 0 (spdn) of iic status register n (iicsn) is set to 1 and intiicn is generated when bit 4 (spien) of iiccn is set to 1. chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 569 18.6.6 wait signal (wait) the wait signal (wait) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scln pin to low level notifies the communication partner of the wait status. when wait status has been canceled for both the master and slave devices, the next data transfer can begin (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). figure 18-11. wait signal (1/2) (a) when master device has a nine-clock wait and slave device has an eight-clock wait (master: transmission, slave: reception, and acken = 1) scln 6 sdan 78 9 123 scln iicn 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iicn scln acken master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock. iicn data write (cancel wait) slave wait after output of eighth clock. ffh is written to iicn or wreln is set to 1. transfer lines remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 570 user ? s manual u15862ej3v0ud figure 18-11. wait signal (2/2) (b) when master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and acken = 1) scln 6 sdan 789 123 scln iicn 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iicn scln acken master master and slave both wait after output of ninth clock. iicn data write (cancel wait) slave ffh is written to iicn or wreln is set to 1. output according to previously set acken value transfer lines remarks 1. acken: bit 2 of iic control register n (iiccn) wreln: bit 5 of iic control register n (iiccn) 2. n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) a wait may be automatically generated depending on the setting for bit 3 (wtimn) of iic control register n (iiccn). normally, when bit 5 (wreln) of iiccn is set to 1 or when ffh is written to iic shift register n (iicn), the wait status is canceled and the transmitting side writes data to iicn to cancel the wait status. the master device can also cancel the wait status via either of the following methods. by setting bit 1 (sttn) of iiccn to 1 by setting bit 0 (sptn) of iiccn to 1 chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 571 18.7 i 2 c interrupt requests (intiicn) the following shows the value of iic status register n (iicsn) at the intiicn interrupt request generation timing and at the intiicn interrupt timing (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). 18.7.1 master device operation (1) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when wtimn = 0 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 10xxx110b 2: iicsn = 10xxx000b 3: iicsn = 10xxx000b (wtimn = 0) 4: iicsn = 10xxxx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) <2> when wtimn = 1 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 10xxx110b 2: iicsn = 10xxx100b 3: iicsn = 10xxxx00b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 572 user ? s manual u15862ej3v0ud (2) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) <1> when wtimn = 0 sttn = 1 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 ? 7 1: iicsn = 10xxx110b 2: iicsn = 10xxx000b (wtimn = 1) 3: iicsn = 10xxxx00b (wtimn = 0) 4: iicsn = 10xxx110b (wtimn = 0) 5: iicsn = 10xxx000b (wtimn = 1) 6: iicsn = 10xxxx00b ? 7: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) <2> when wtimn = 1 sttn = 1 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 10xxx110b 2: iicsn = 10xxxx00b 3: iicsn = 10xxx110b 4: iicsn = 10xxxx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 573 (3) start ~ code ~ data ~ data ~ stop (extension code transmission) <1> when wtimn = 0 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 1010x110b 2: iicsn = 1010x000b 3: iicsn = 1010x000b (wtimn = 1) 4: iicsn = 1010xx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) <2> when wtimn = 1 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 1010x110b 2: iicsn = 1010x100b 3: iicsn = 1010xx00b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 574 user ? s manual u15862ej3v0ud 18.7.2 slave device operation (when receiving slave address data (match with svan)) (1) start ~ address ~ data ~ data ~ stop <1> when wtimn = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0001x110b 2: iicsn = 0001x000b 3: iicsn = 0001x000b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) <2> when wtimn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0001x110b 2: iicsn = 0001x100b 3: iicsn = 0001xx00b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 575 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn = 0 (after restart, match with svan) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0001x110b 2: iicsn = 0001x000b 3: iicsn = 0001x110b 4: iicsn = 0001x000b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) <2> when wtimn = 1 (after restart, match with svan) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0001x110b 2: iicsn = 0001xx00b 3: iicsn = 0001x110b 4: iicsn = 0001xx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 576 user ? s manual u15862ej3v0ud (3) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtimn = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0001x110b 2: iicsn = 0001x000b 3: iicsn = 0010x010b 4: iicsn = 0010x000b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) <2> when wtimn = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 ? 6 1: iicsn = 0001x110b 2: iicsn = 0001xx00b 3: iicsn = 0010x010b 4: iicsn = 0010x110b 5: iicsn = 0010xx00b ? 6: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 577 (4) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn = 0 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0001x110b 2: iicsn = 0001x000b 3: iicsn = 00000x10b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) <2> when wtimn = 1 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0001x110b 2: iicsn = 0001xx00b 3: iicsn = 00000x10b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 578 user ? s manual u15862ej3v0ud 18.7.3 slave device operation (when receiving extension code) (1) start ~ code ~ data ~ data ~ stop <1> when wtimn = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0010x010b 2: iicsn = 0010x000b 3: iicsn = 0010x000b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) <2> when wtimn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0010x010b 2: iicsn = 0010x110b 3: iicsn = 0010x100b 4: iicsn = 0010xx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 579 (2) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtimn = 0 (after restart, match with svan) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0010x010b 2: iicsn = 0010x000b 3: iicsn = 0001x110b 4: iicsn = 0001x000b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) <2> when wtimn = 1 (after restart, match with svan) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 ? 6 1: iicsn = 0010x010b 2: iicsn = 0010x110b 3: iicsn = 0010xx00b 4: iicsn = 0001x110b 5: iicsn = 0001xx00b ? 6: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 580 user ? s manual u15862ej3v0ud (3) start ~ code ~ data ~ start ~ code ~ data ~ stop <1> when wtimn = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0010x010b 2: iicsn = 0010x000b 3: iicsn = 0010x010b 4: iicsn = 0010x000b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) <2> when wtimn = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 ? 7 1: iicsn = 0010x010b 2: iicsn = 0010x110b 3: iicsn = 0010xx00b 4: iicsn = 0010x010b 5: iicsn = 0010x110b 6: iicsn = 0010xx00b ? 7: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 581 (4) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtimn = 0 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0010x010b 2: iicsn = 0010x000b 3: iicsn = 00000x10b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) <2> when wtimn = 1 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0010x010b 2: iicsn = 0010x110b 3: iicsn = 0010xx00b 4: iicsn = 00000x10b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 582 user ? s manual u15862ej3v0ud 18.7.4 operation without communication (1) start ~ code ~ data ~ data ~ stop st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp ? 1 ? 1: iicsn = 00000001b remark ? : generated only when spien = 1 n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) 18.7.5 arbitration loss operation (operation as slave after arbitration loss) (1) when arbitration loss occurs during transmission of slave address data <1> when wtimn = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0101x110b (example: when aldn is read during interrupt servicing) 2: iicsn = 0001x000b 3: iicsn = 0001x000b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) <2> when wtimn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0101x110b (example: when aldn is read during interrupt servicing) 2: iicsn = 0001x100b 3: iicsn = 0001xx00b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 583 (2) when arbitration loss occurs during transmission of extension code <1> when wtimn = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 0110x010b (example: when aldn is read during interrupt servicing) 2: iicsn = 0010x000b 3: iicsn = 0010x000b ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) <2> when wtimn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn = 0110x010b (example: when aldn is read during interrupt servicing) 2: iicsn = 0010x110b 3: iicsn = 0010x100b 4: iicsn = 0010xx00b ? 5: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 584 user ? s manual u15862ej3v0ud 18.7.6 operation when arbitration loss occurs (no communication after arbitration loss) (1) when arbitration loss occurs during transmission of slave address data st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 ? 2 1: iicsn = 01000110b (example: when aldn is read during interrupt servicing) ? 2: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) (2) when arbitration loss occurs during transmission of extension code st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 ? 2 1: iicsn = 0110x010b (example: when aldn is read during interrupt servicing) iiccn ? s lreln is set to 1 by software ? 2: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 585 (3) when arbitration loss occurs during data transfer <1> when wtimn = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 ? 3 1: iicsn = 10001110b 2: iicsn = 01000000b (example: when aldn is read during interrupt servicing) ? 3: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) <2> when wtimn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 ? 3 1: iicsn = 10001110b 2: iicsn = 01000100b (example: when aldn is read during interrupt servicing) ? 3: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 586 user ? s manual u15862ej3v0ud (4) when loss occurs due to restart condition during data transfer <1> not extension code (example: mismatches with svan) st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iicsn = 1000x110b 2: iicsn = 01000110b (example: when aldn is read during interrupt servicing) ? 3: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care dn = d6 to d0 n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) <2> extension code st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iicsn = 1000x110b 2: iicsn = 0110x010b (example: when aldn is read during interrupt servicing) iiccn ? s lreln is set to 1 by software ? 3: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care dn = d6 to d0 n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 587 (5) when loss occurs due to stop condition during data transfer st ad6 to ad0 rw ak d7 to dn sp 1 ? 2 1: iicsn = 1000x110b ? 2: iicsn = 01000001b remark : always generated ? : generated only when spien = 1 x: don ? t care dn = d6 to d0 n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) (6) when arbitration loss occurs due to low-level data when attempting to generate a restart condition when wtimn = 1 sttn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 1000x110b 2: iicsn = 1000xx00b 3: iicsn = 01000100b (example: when aldn is read during interrupt servicing) ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 588 user ? s manual u15862ej3v0ud (7) when arbitration loss occurs due to a stop condition when attempting to generate a restart condition when wtimn = 1 sttn = 1 st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iicsn = 1000x110b 2: iicsn = 1000xx00b ? 3: iicsn = 01000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) (8) when arbitration loss occurs due to low-level data when attempting to generate a stop condition when wtimn = 1 sptn = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn = 1000x110b 2: iicsn = 1000xx00b 3: iicsn = 01000000b (example: when aldn is read during interrupt servicing) ? 4: iicsn = 00000001b remark : always generated ? : generated only when spien = 1 x: don ? t care n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 589 18.8 interrupt request (intiicn) generation timing and wait control the setting of bit 3 (wtimn) in iic control register n (iiccn) determines the timing by which intiicn is generated and the corresponding wait control, as shown below. table 18-3. intiicn generation timing and wait control during slave device operation during master device operation wtimn address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 988 1 9 notes 1, 2 9 note 2 9 note 2 999 notes 1. the slave device ? s intiicn signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to slave address register n (svan). at this point, ack is output regardless of the value set to iiccn ? s bit 2 (acken). for a slave device that has received an extension code, intiicn occurs at the falling edge of the eighth clock. 2. if the received address does not match the contents of slave address register n (svan), neither intiicn nor a wait occurs. remarks 1. the numbers in the table indicate the number of the serial clock ? s clock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. 2. n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) (1) during address transmission/reception ? slave device operation: interrupt and wait timing are determined regardless of the wtimn bit. ? master device operation: interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtimn bit. (2) during data reception ? master/slave device operation: interrupt and wait timing are determined according to the wtimn bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing are determined according to the wtimn bit. (4) wait cancellation method the four wait cancellation methods are as follows. ? by setting bit 5 (wreln) of iic control register n (iiccn) to 1 ? by writing to iic shift register n (iicn) ? by start condition setting (bit 1 (sttn) of iic control register n (iiccn) = 1) ? by step condition setting (bit 0 (sptn) of iic control register n (iiccn) = 1) when an 8-clock wait has been selected (wtimn = 0), the output level of ack must be determined prior to wait cancellation. remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 590 user ? s manual u15862ej3v0ud (5) stop condition detection intiicn is generated when a stop condition is detected. remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) 18.9 address match detection method when in i 2 c bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. address match detection is performed automatically by hardware. an interrupt request (intiicn) occurs when a local address has been set to slave address register n (svan) and when the address set to svan matches the slave address sent by the master device, or when an extension code has been received (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). 18.10 error detection in i 2 c bus mode, the status of the serial data bus (sdan) during data transmission is captured by iic shift register n (iicn) of the transmitting device, so the iicn data prior to transmission can be compared with the transmitted iicn data to enable detection of transmission errors. a transmission error is judged as having occurred when the compared data values do not match (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). 18.11 extension code (1) when the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (excn) is set for extension code reception and an interrupt request (intiicn) is issued at the falling edge of the eighth clock. the local address stored in slave address register n (svan) is not affected. (2) if 11110xx0 is set to svan by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. note that intiicn occurs at the falling edge of the eighth clock. ? higher 4 bits of data match: excn = 1 note ? 7 bits of data match: coin = 1 note note excn: bit 5 of iic status register n (iicsn) coin: bit 4 of iic status register n (iicsn) (3) since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. for example, when operation as a slave is not desired after the extension code is received, set bit 6 (lreln) of iic control register n (iiccn) to 1 and the cpu will enter the next communication wait state. remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 591 table 18-4. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 x cbus address 0000 010 x address that is reserved for different bus format 1111 0xx x 10-bit slave address specification 18.12 arbitration when several master devices simultaneously output a start condition (when sttn is set to 1 before stdn is set to 1 note ), communication among the master devices is performed as the number of clocks is adjusted until the data differs. this kind of operation is called arbitration (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). when one of the master devices loses in arbitration, an arbitration loss flag (aldn) in iic status register n (iicsn) is set via the timing by which the arbitration loss occurred, and the scln and sdan lines are both set for high impedance, which releases the bus. the arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop condition is detected, etc.) and the aldn = 1 setting that has been made by software. for details of interrupt request timing, see 18.7 i 2 c interrupt requests (intiicn) . note stdn: bit 1 of iic status register n (iicsn) sttn: bit 1 of iic control register n (iiccn) figure 18-12. arbitration timing example master 1 master 2 transfer lines scln sdan scln sdan scln sdan master 1 loses arbitration hi-z hi-z remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 592 user ? s manual u15862ej3v0ud table 18-5. status during arbitration and interrupt request generation timing status during arbitration interrupt request generation timing during address transmission at falling edge of eighth or ninth clock following byte transfer note 1 read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack signal transfer period after data reception when restart condition is detected during data transfer when stop condition is detected during data transfer when stop condition is output (when spien = 1) note 2 when data is at low level while attempting to output a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to output a restart condition when stop condition is output (when spien = 1) note 2 when data is at low level while attempting to output a stop condition at falling edge of eighth or ninth clock following byte transfer note 1 when scln is at low level while attempting to output a restart condition notes 1. when wtimn (bit 3 of the iic control register n (iiccn)) = 1, an interrupt request occurs at the falling edge of the ninth clock. when wtimn = 0 and the extension code ? s slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. when there is a possibility that arbitration will occur, set spien = 1 for master device operation. remarks 1. spien: bit 5 of iic control register n (iiccn) 2. n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) 18.13 wakeup function the i 2 c bus slave function is a function that generates an interrupt request (intiicn) when a local address or extension code has been received. this function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match. when a start condition is detected, wakeup standby mode is set. this wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has output a start condition) to a slave device. however, when a stop condition is detected, bit 5 (spien) of iic control register n (iiccn) is set regardless of the wake up function, and this determines whether interrupt requests are enabled or disabled (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 593 18.14 communication reservation to start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. there are two modes under which the bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when bit 6 (lreln) of iic control register n (iiccn) was set to ? 1 ? ). if bit 1 (sttn) of iiccn is set while the bus is not used, a start condition is automatically generated and wait status is set after the bus is released (after a stop condition is detected). when the bus release is detected (when a stop condition is detected), writing to iic shift register n (iicn) causes the master ? s address transfer to start. at this point, iiccn ? s bit 4 (spien) should be set. when sttn has been set, the operation mode (as start condition or as communication reservation) is determined according to the bus status. if the bus has been released ............................................. a start condition is generated if the bus has not been released (standby mode) ............. communication reservation to detect which operation mode has been determined for sttn, set sttn, wait for the wait period, then check the mstsn (bit 7 of iic status register n (iicsn)). wait periods, which should be set via software, are listed in table 18-6. these wait periods can be set via the settings for bits 3, 1, and 0 (smcn, cln1, and cln0) in iic clock selection register n (iiccln). table 18-6. wait periods smcn cln1 cln0 wait period 0 0 0 26 clocks 0 0 1 46 clocks 0 1 0 92 clocks 0 1 1 37 clocks 100 101 16 clocks 1 1 0 32 clocks 1 1 1 13 clocks remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 594 user ? s manual u15862ej3v0ud the communication reservation timing is shown below. figure 18-13. communication reservation timing 2 1 3456 2 1 3456 789 scln sdan program processing hardware processing write to iicn set spdn and intiicn sttn =1 communication reservation set stdn output by master with bus access iicn: iic shift register n sttn: bit 1 of iic control register n (iiccn) stdn: bit 1 of iic status register n (iicsn) spdn: bit 0 of iic status register n (iicsn) remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) communication reservations are accepted via the following timing. after bit 1 (stdn) of iic status register n (iicsn) is set to 1, a communication reservation can be made by setting bit 1 (sttn) of iic control register n (iiccn) to 1 before a stop condition is detected (n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1)). figure 18-14. timing for accepting communication reservations scln sdan stdn spdn standby mode remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 595 the communication reservation flowchart is illustrated below. figure 18-15. communication reservation flowchart di set1 sttn define communication reservation wait cancel communication reservation no yes iicn h ei mstsn = 0? (communication reservation) note (generate start condition) ; sets sttn flag (communication reservation). ; gets wait period set by software (see table 18-6 ). ; confirmation of communication reservation ; clear user flag. ; iicn write operation ; defines that communication reservation is in effect (defines and sets user flag to any part of ram). note the communication reservation operation executes a write to iic shift register n (iicn) when a stop condition interrupt request occurs. remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 596 user ? s manual u15862ej3v0ud 18.15 cautions after a reset, when changing from a mode in which no stop condition has been detected (the bus has not been released) to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. when using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). use the following sequence for generating a stop condition. (a) set iic clock selection register n (iiccln). (b) set bit 7 (iicen) of iic control register n (iiccn). (c) set bit 0 of iiccn. remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 597 18.16 communication operations 18.16.1 master operations the following is a flowchart of the master operations. figure 18-16. master operation flowchart (1) iiccln h select transfer clock. iiccn h iicen = spien = wtimn = 1 sptn = 1 start iicn write transfer. start iicn write transfer. wreln = 1 start reception. generate stop condition. (no slave with matching address) generate restart condition or stop condition. start data processing data processing acken = 0 no yes no no no no no no yes yes yes yes yes intiicn = 1? wtimn = 0 acken = 1 intiicn = 1? transfer completed? intiicn = 1? ackdn = 1? trcn = 1? intiicn = 1? ackdn = 1? ; stop condition detection ; address transfer completion no (receive) yes (transmit) ; iiccn initial setting remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 598 user ? s manual u15862ej3v0ud figure 18-17. master operation flowchart (2) iiccln xxh iicfn xxh transfer clock selection iicfn register setting iiccn register initial setting iiccn xxh iicen = spien = wtimn = 1 sttn = 1 3 clocks input iicn write transfer start iicn write start transfer wtimn = 0 acken = 1 wreln = 1 reception start data processing data processing acken = 0 sptn = 1 stop condition generated start no no yes yes intiicn = 1? no no yes (address transfer end) yes intiicn = 1? no yes yes intiicn = 1? no yes intiicn = 1? no yes ackdn = 1? no reception completed? yes no (restart) transfer completed? ackdn = 1? yes (transmission) trcn = 1? iicbsyn = 1? no no (reception) yes stcfn = 1? remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 599 18.16.2 slave operation an example of slave operation is shown below. figure 18-18. slave operation flowchart iiccn h iicen = 1 wreln = 1 start reception. detect restart condition or stop condition. start acken = 0 data processing data processing lreln = 1 no yes no no no no no no no yes no yes yes yes yes yes yes wtimn = 0 acken = 1 intiicn = 1? yes communicate? transfer completed? intiicn = 1? wtimn = 1 start iicn write transfer. intiicn = 1? excn = 1? coin = 1? trcn = 1? ackdn = 1? remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 600 user ? s manual u15862ej3v0ud 18.17 timing of data communication when using i 2 c bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the master device transmits the trcn bit (bit 3 of iic status register n (iicsn)) that specifies the data transfer direction and then starts serial communication with the slave device. iic shift register n (iicn) ? s shift operation is synchronized with the falling edge of the serial clock (scln). the transmit data is transferred to the so latch and is output (msb first) via the sdan pin. data input via the sdan pin is captured by iicn at the rising edge of scln. the data communication timing is shown below. remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 601 figure 18-19. example of master to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iicn ackdn stdn spdn wtimn h h l l l l h h h l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iicn address iicn data iicn ffh transmit start condition receive (when excn = 1) note note note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 602 user ? s manual u15862ej3v0ud figure 18-19. example of master to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iicn ackdn stdn spdn wtimn h h l l l l l l h h h h l l l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iicn data iicn ffh note iicn ffh note iicn data transmit receive note note note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 603 figure 18-19. example of master to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iicn ackdn stdn spdn wtimn h h l l l l h h h l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iicn data iicn address iicn ffh note iicn ffh note stop condition start condition transmit note note (when spien = 1) receive (when spien = 1) note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 604 user ? s manual u15862ej3v0ud figure 18-20. example of slave to master communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iicn ackdn stdn spdn wtimn h h l l h h l acken mstsn sttn l l sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r d4 d3 d2 d5 d6 d7 iicn address iicn ffh note note iicn data start condition note to cancel master wait, write ffh to iicn or set wreln. remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus user ? s manual u15862ej3v0ud 605 figure 18-20. example of slave to master communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iicn ackdn stdn spdn wtimn h h h l l l l l l h h h l l l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iicn data iicn data iicn ffh note iicn ffh note note to cancel master wait, write ffh to iicn or set wreln. remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 18 i 2 c bus 606 user ? s manual u15862ej3v0ud figure 18-20. example of slave to master communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iicn ackdn stdn spdn wtimn h h l l l h h acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scln sdan processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iicn address iicn ffh note note iicn data stop condition start condition (when spien = 1) n ? ack (when spien = 1) note to cancel master wait, write ffh to iicn or set wreln. remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) user?s manual u15862ej3v0ud 607 chapter 19 interrupt/exception processing function 19.1 overview the v850es/kf1, v850es/kg1, and v850es/kj1 are provided with a dedicated interrupt controller (intc) for interrupt servicing and realize a high-powered interrupt function that can service interrupt requests from a total of 33 to 45 sources. an interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution. the v850es/kf1, v850es/kg1, and v850es/kj1 can process interrupt requests from the on-chip peripheral hardware and external sources. moreover, exception processing can be started by the trap instruction (software exception) or by generation of an exception event (fetching of an illegal op code) (exception trap). 19.1.1 features interrupt source v850es/kf1 v850es/kg1 v850es/kj1 external 1 channel (nmi pin) non-maskable interrupt internal 2 channels (wdt1, wdt2) external 7 channels (all edge detection interrupts) wdt1 1 channel 1 channel 1 channel tm0 4 channels 8 channels 12 channels tmh 2 channels 2 channels 2 channels tm5 2 channels 2 channels 2 channels wt 2 channels 2 channels 2 channels brg 1 channel 1 channel 1 channel uart 6 channels 6 channels 9 channels csi0 2 channels 2 channels 3 channels csia 1 channel 2 channels 2 channels iic 1 channel 1 channel 2 channels kr 1 channel 1 channel 1 channel ad 1 channel 1 channel 1 channel interrupt function maskable interrupt internal total 24 channels 29 channels 38 channels 16 channels (trap00h to trap0fh) software exception 16 channels (trap10h to trap1fh) exception function exception trap 2 channels (ilgop/dbg0) tables 19-1 to 19-3 list the interrupt/exception sources. chapter 19 interrupt/exception processing function user?s manual u15862ej3v0ud 608 table 19-1. interrupt source list (v850es/kf1) (1/2) type classification default priority name trigger interrupt source exception code handler address restored pc interrupt control register reset pin input pin reset interrupt ? reset internal reset input from wdt1, wdt2 wdt1, wdt2 0000h 00000000h undefined ? ? nmi nmi pin valid edge input pin 0010h 00000010h note 1 ? ?intwdt1 wdt1 overflow (when non- maskable interrupt selected) wdt1 0020h 00000020h note 1 ? non- maskable interrupt ? intwdt2 wdt2 overflow (when non- maskable interrupt selected) wdt2 0030h 00000030h nextpc ? ? trap0n note 2 trap instruction ? 004nh note 2 00000040h nextpc ? software exception exception ? trap1n note 2 trap instruction ? 005nh note 2 00000050h nextpc ? exception trap exception ? ilgop/ dbg0 illegal op code/dbtrap instruction ? 0060h 00000060h nextpc ? 0 intwdtm1 wdt1 overflow (when interval timer selected) wdt1 0080h 00000080h nextpc wdt1ic 1 intp0 intp0 pin valid edge input pin 0090h 00000090h nextpc pic0 2 intp1 intp1 pin valid edge input pin 00a0h 000000a0h nextpc pic1 3 intp2 intp2 pin valid edge input pin 00b0h 000000b0h nextpc pic2 4 intp3 intp3 pin valid edge input pin 00c0h 000000c0h nextpc pic3 5 intp4 intp4 pin valid edge input pin 00d0h 000000d0h nextpc pic4 6 intp5 intp5 pin valid edge input pin 00e0h 000000e0h nextpc pic5 7 intp6 intp6 pin valid edge input pin 00f0h 000000f0h nextpc pic6 8 inttm000 tm00 and cr000 match tm00 0100h 00000100h nextpc tm0ic00 9 inttm001 tm00 and cr001 match tm00 0110h 00000110h nextpc tm0ic01 10 inttm010 tm01 and cr010 match tm01 0120h 00000120h nextpc tm0ic10 11 inttm011 tm01 and cr011 match tm01 0130h 00000130h nextpc tm0ic11 12 inttm50 tm50 and cr50 match tm50 0140h 00000140h nextpc tm5ic0 13 inttm51 tm51 and cr51 match tm51 0150h 00000150h nextpc tm5ic1 14 intcsi00 csi00 transfer completion csi00 0160h 00000160h nextpc csi0ic0 15 intcsi01 csi01 transfer completion csi01 0170h 00000170h nextpc csi0ic1 16 intsre0 uart0 reception error occurrence uart0 0180h 00000180h nextpc sreic0 maskable interrupt 17 intsr0 uart0 reception completion uart0 0190h 00000190h nextpc sric0 notes 1. in the case of intwdt1 and intwdt2, restoration through the reti instruction is not possible, so perform system reset following completion of interrupt servicing. 2. n = 0 to fh chapter 19 interrupt/exception processing function user?s manual u15862ej3v0ud 609 table 19-1. interrupt source list (v850es/kf1) (2/2) type classification default priority name trigger interrupt source exception code handler address restored pc interrupt control register 18 intst0 uart0 transmission completion uart0 01a0h 000001ah nextpc stic0 19 intsre1 uart1 reception error occurrence uart1 01b0h 000001b0h nextpc sreic1 20 intsr1 uart1 reception completion uart1 01c0h 000001c0h nextpc sric1 21 intst1 uart1 transmission completion uart1 01d0h 000001d0h nextpc stic1 22 inttmh0 tmh0 and cmp00/cmp01 match tmh0 01e0h 000001e0h nextpc tmhic0 23 inttmh1 tmh1 and cmp10/cmp11 match tmh1 01f0h 000001f0h nextpc tmhic1 24 intcsia0 csia0 transfer completion csia0 0200h 00000200h nextpc csiaic0 25 intiic0 note i 2 c0 transfer completion i 2 c0 0210h 00000210h nextpc iicic0 26 intad a/d conversion completion a/d 0220h 00000220h nextpc adic 27 intkr key return interrupt kr 0230h 00000230h nextpc kric 28 intwti watch timer interval wt 0240h 00000240h nextpc wtiic 29 intwt watch timer reference time wt 0250h 00000250h nextpc wtic maskable interrupt 30 intbrg watch counter brg and prscm match brg 0260h 00000260h nextpc brgic note only for the pd703208y, 703209y, 703210y, and 70f3210y remarks 1. default priority: the priority order when two or more maskable interrupt requests with the same priority level are generated at the same time. the highest priority is 0. restored pc: the value of the program counter (pc) saved to eipc or fepc when interrupt/exception processing is started. the restored pc when a non-maskable or maskable interrupt is acknowledged while either of the following instructions is being executed does not become nextpc (when an interrupt is acknowledged during the execution of an instruction, the execution of that instruction is stopped and is resumed following completion of interrupt servicing). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? divide instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only when an interrupt occurs before stack pointer update) nextpc: the pc value at which processing is started following interrupt/exception processing. 2. the execution address of the illegal op code when an illegal op code exception occurs is calculated with (restored pc ? 4). chapter 19 interrupt/exception processing function user?s manual u15862ej3v0ud 610 table 19-2. interrupt source list (v850es/kg1) (1/2) type classification default priority name trigger interrupt source exception code handler address restored pc interrupt control register reset pin input pin reset interrupt ? reset internal reset input from wdt1, wdt2 wdt1, wdt2 0000h 00000000h undefined ? ? nmi nmi pin valid edge input pin 0010h 00000010h nextpc ? ?intwdt1 wdt1 overflow (when non- maskable interrupt selected) wdt1 0020h 00000020h note 1 ? non- maskable interrupt ? intwdt2 wdt2 overflow (when non- maskable interrupt selected) wdt2 0030h 00000020h note 1 ? ? trap0n note 2 trap instruction ? 004nh note 2 00000040h nextpc ? software exception exception ? trap1n note 2 trap instruction ? 005nh note 2 00000050h nextpc ? exception trap exception ? ilgop/ dbg0 illegal op code/dbtrap instruction ? 0060h 00000060h nextpc ? 0 intwdtm1 wdt1 overflow (when interval timer selected) wdt1 0080h 00000080h nextpc wdt1ic 1 intp0 intp0 pin valid edge input pin 0090h 00000090h nextpc pic0 2 intp1 intp1 pin valid edge input pin 00a0h 000000a0h nextpc pic1 3 intp2 intp2 pin valid edge input pin 00b0h 000000b0h nextpc pic2 4 intp3 intp3 pin valid edge input pin 00c0h 000000c0h nextpc pic3 5 intp4 intp4 pin valid edge input pin 00d0h 000000d0h nextpc pic4 6 intp5 intp5 pin valid edge input pin 00e0h 000000e0h nextpc pic5 7 intp6 intp6 pin valid edge input pin 00f0h 000000f0h nextpc pic6 8 inttm000 tm00 and cr000 match tm00 0100h 00000100h nextpc tm0ic00 9 inttm001 tm00 and cr001 match tm00 0110h 00000110h nextpc tm0ic01 10 inttm010 tm01 and cr010 match tm01 0120h 00000120h nextpc tm0ic10 11 inttm011 tm01 and cr011 match tm01 0130h 00000130h nextpc tm0ic11 12 inttm50 tm50 and cr50 match tm50 0140h 00000140h nextpc tm5ic0 13 inttm51 tm51 and cr51 match tm51 0150h 00000150h nextpc tm5ic1 14 intcsi00 csi00 transfer completion csi00 0160h 00000160h nextpc csi0ic0 15 intcsi01 csi01 transfer completion csi01 0170h 00000170h nextpc csi0ic1 16 intsre0 uart0 reception error occurrence uart0 0180h 00000180h nextpc sreic0 maskable interrupt 17 intsr0 uart0 reception completion uart0 0190h 00000190h nextpc sric0 notes 1. in the case of intwdt1 and intwdt2, restoration through the reti instruction is not possible, so perform system reset following completion of interrupt servicing. 2. n = 0 to fh chapter 19 interrupt/exception processing function user?s manual u15862ej3v0ud 611 table 19-2. interrupt source list (v850es/kg1) (2/2) type classification default priority name trigger interrupt source exception code handler address restored pc interrupt control register 18 intst0 uart0 transmission completion uart0 01a0h 000001ah nextpc stic0 19 intsre1 uart1 reception error occurrence uart1 01b0h 000001b0h nextpc sreic1 20 intsr1 uart1 reception completion uart1 01c0h 000001c0h nextpc sric1 21 intst1 uart1 transmission completion uart1 01d0h 000001d0h nextpc stic1 22 inttmh0 tmh0 and cmp00/cmp01 match tmh0 01e0h 000001e0h nextpc tmhic0 23 inttmh1 tmh1 and cmp10/cmp11 match tmh1 01f0h 000001f0h nextpc tmhic1 24 intcsia0 csia0 transfer completion csia0 0200h 00000200h nextpc csiaic0 25 intiic0 note 1 i 2 c0 transfer completion i 2 c0 0210h 00000210h nextpc iicic0 26 intad a/d conversion completion a/d 0220h 00000220h nextpc adic 27 intkr key return interrupt kr 0230h 00000230h nextpc kric 28 intwti watch timer interval wt 0240h 00000240h nextpc wtiic 29 intwt watch timer reference time wt 0250h 00000250h nextpc wtic 30 intbrg watch counter brg and prscm match brg 0260h 00000260h nextpc brgic 31 inttm020 tm02 and cr020 match tm02 0270h 00000270h nextpc tm0ic20 32 inttm021 tm02 and cr021 match tm02 0280h 00000280h nextpc tm0ic21 33 inttm030 tm03 and cr030 match tm03 0290h 00000290h nextpc tm0ic30 34 inttm031 tm03 and cr031 match tm03 02a0h 000002a0h nextpc tm0ic31 maskable interrupt 35 intcsia1 csia1 transfer completion csia1 02b0h 000002b0h nextpc csiaic1 note only for the pd703212y, 703213y, 703214y, and 70f3214y remarks 1. default priority: the priority order when two or more maskable interrupt requests with the same priority level are generated at the same time. the highest priority is 0. restored pc: the value of the program counter (pc) saved to eipc or fepc when interrupt/exception processing is started. the restored pc when a non-maskable or maskable interrupt is acknowledged while either of the following instructions is being executed does not become nextpc (when an interrupt is acknowledged during the execution of an instruction, the execution of that instruction is stopped and is resumed following completion of interrupt servicing). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? divide instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only when an interrupt occurs before stack pointer update) nextpc: the pc value at which processing is started following interrupt/exception processing. 2. the execution address of the illegal op code when an illegal op code exception occurs is calculated with (restored pc ? 4). chapter 19 interrupt/exception processing function user?s manual u15862ej3v0ud 612 table 19-3. interrupt source list (v850es/kj1) (1/2) type classification default priority name trigger interrupt source exception code handler address restored pc interrupt control register reset pin input pin reset interrupt ? reset internal reset input from wdt1, wdt2 wdt1 wdt2 0000h 00000000h undefined ? ? nmi nmi pin valid edge input pin 0010h 00000010h nextpc ? ?intwdt1 wdt1 overflow (when non- maskable interrupt selected) wdt1 0020h 00000020h note 1 ? non- maskable interrupt ? intwdt2 wdt2 overflow (when non- maskable interrupt selected) wdt2 0030h 00000020h note 1 ? ? trap0n note 2 trap instruction ? 004nh note 2 00000040h nextpc ? software exception exception ? trap1n note 2 trap instruction ? 005nh note 2 00000050h nextpc ? exception trap exception ? ilgop/ dbg0 illegal op code/dbtrap instruction ? 0060h 00000060h nextpc ? 0 intwdtm1 wdt1 overflow (when interval timer selected) wdt1 0080h 00000080h nextpc wdt1ic 1 intp0 intp0 pin valid edge input pin 0090h 00000090h nextpc pic0 2 intp1 intp1 pin valid edge input pin 00a0h 000000a0h nextpc pic1 3 intp2 intp2 pin valid edge input pin 00b0h 000000b0h nextpc pic2 4 intp3 intp3 pin valid edge input pin 00c0h 000000c0h nextpc pic3 5 intp4 intp4 pin valid edge input pin 00d0h 000000d0h nextpc pic4 6 intp5 intp5 pin valid edge input pin 00e0h 000000e0h nextpc pic5 7 intp6 intp6 pin valid edge input pin 00f0h 000000f0h nextpc pic6 8 inttm000 tm00 and cr000 match tm00 0100h 00000100h nextpc tm0ic00 9 inttm001 tm00 and cr001 match tm00 0110h 00000110h nextpc tm0ic01 10 inttm010 tm01 and cr010 match tm01 0120h 00000120h nextpc tm0ic10 11 inttm011 tm01 and cr011 match tm01 0130h 00000130h nextpc tm0ic11 12 inttm50 tm50 and cr50 match tm50 0140h 00000140h nextpc tm5ic0 13 inttm51 tm51 and cr51 match tm51 0150h 00000150h nextpc tm5ic1 14 intcsi00 csi00 transfer completion csi00 0160h 00000160h nextpc csi0ic0 15 intcsi01 csi01 transfer completion csi01 0170h 00000170h nextpc csi0ic1 16 intsre0 uart0 reception error occurrence uart0 0180h 00000180h nextpc sreic0 17 intsr0 uart0 reception completion uart0 0190h 00000190h nextpc sric0 maskable interrupt 18 intst0 uart0 transmission completion uart0 01a0h 000001ah nextpc stic0 notes 1. in the case of intwdt1 and intwdt2, restoration through the reti instruction is not possible, so perform system reset following completion of interrupt servicing. 2. n = 0 to fh chapter 19 interrupt/exception processing function user?s manual u15862ej3v0ud 613 table 19-3. interrupt source list (v850es/kj1) (2/2) type classification default priority name trigger interrupt source exception code handler address restored pc interrupt control register 19 intsre1 uart1 reception error occurrence uart1 01b0h 000001b0h nextpc sreic1 20 intsr1 uart1 reception completion uart1 01c0h 000001c0h nextpc sric1 21 intst1 uart1 transmission completion uart1 01d0h 000001d0h nextpc stic1 22 inttmh0 tmh0 and cmp00/cmp01 match tmh0 01e0h 000001e0h nextpc tmhic0 23 inttmh1 tmh1 and cmp10/cmp11 match tmh1 01f0h 000001f0h nextpc tmhic1 24 intcsia0 csia0 transfer completion csia0 0200h 00000200h nextpc csiaic0 25 intiic0 note i 2 c0 transfer completion i 2 c0 0210h 00000210h nextpc iicic0 26 intad a/d conversion completion a/d 0220h 00000220h nextpc adic 27 intkr key return interrupt kr 0230h 00000230h nextpc kric 28 intwti watch timer interval wt 0240h 00000240h nextpc wtiic 29 intwt watch timer reference time wt 0250h 00000250h nextpc wtic 30 intbrg watch counter brg and prscm match brg 0260h 00000260h nextpc brgic 31 inttm020 tm02 and cr020 match tm02 0270h 00000270h nextpc tm0ic20 32 inttm021 tm02 and cr021 match tm02 0280h 00000280h nextpc tm0ic21 33 inttm030 tm03 and cr030 match tm03 0290h 00000290h nextpc tm0ic30 34 inttm031 tm03 and cr031 match tm03 02a0h 000002a0h nextpc tm0ic31 35 intcsia1 csia1 transfer completion csia1 02b0h 000002b0h nextpc csiaic1 36 inttm040 tm04 and cr040 match tm04 02c0h 000002c0h nextpc tm0ic40 37 inttm041 tm04 and cr041 match tm04 02d0h 000002d0h nextpc tm0ic41 38 inttm050 tm05 and cr050 match tm05 02e0h 000002e0h nextpc tm0ic50 39 inttm051 tm05 and cr051 match tm05 02f0h 000002f0h nextpc tm0ic51 40 intcsi02 csi02 transfer completion csi02 0300h 00000300h nextpc csi0ic2 41 intsre2 uart2 reception error occurrence uart2 0310h 00000310h nextpc sreic2 42 intsr2 uart2 reception completion uart2 0320h 00000320h nextpc sric2 43 intst2 uart2 transmission completion uart2 0330h 00000330h nextpc stic2 maskable interrupt 44 intiic1 note i 2 c1 transfer completion i 2 c1 0340h 00000340h nextpc iicic1 note only for the pd703216y, 703217y, and 70f3217y remarks 1. default priority: the priority order when two or more maskable interrupt requests with the same priority level are generated at the same time. the highest priority is 0. restored pc: the value of the program counter (pc) saved to eipc or fepc when interrupt/exception processing is started. the restored pc when a non-maskable or maskable interrupt is acknowledged while either of the following instructions is being executed does not become nextpc (when an interrupt is acknowledged during the execution of an instruction, the execution of that instruction is stopped and is resumed following completion of interrupt servicing). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? divide instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only when an interrupt occurs before stack pointer update) nextpc: the pc value at which processing is started following interrupt/exception processing. 2. the execution address of the illegal op code when an illegal op code exception occurs is calculated with (restored pc ? 4). chapter 19 interrupt/exception processing function user?s manual u15862ej3v0ud 614 19.2 non-maskable interrupts non-maskable interrupt requests are acknowledged unconditionally, even when interrupts are disabled (di state). non-maskable interrupts (nmi) are not subject to priority control and take precedence over all other interrupt requests. the following three types of non-maskable interrupt requests are available in the v850es/kf1, v850es/kg1, and v850es/kj1. ? nmi pin input (nmi) ? non-maskable interrupt request due to overflow of watchdog timer 1 (intwdt1) ? non-maskable interrupt request due to overflow of watchdog timer 2 (intwdt2) there are four choices for the valid edge of an nmi pin, namely: rising edge, falling edge, both edges, and no edge detection. the non-maskable interrupt due to overflow of watchdog timer 1 (intwdt1) functions by setting the wdtn14 and wdtm13 bits of watchdog timer mode register 1 (wdtm1) to 10. the non-maskable interrupt due to overflow of watchdog timer 2 (intwdt2) functions by setting the wdtn21 and wdtm20 bits of watchdog timer mode register 1 (wdtm1) to 01. when two or more non-maskable interrupts occur simultaneously, they are processed in a sequence determined by the following priority order (the interrupt requests with low priority level are ignored). intwdt2 > intwdt1 > nmi if during nmi processing, an nmi, intwdt1, or intwdt2 request newly occurs, processing is performed as follows. (1) if an nmi request newly occurs during nmi processing the new nmi request is held pending regardless of the value of the np bit of the program status word (psw) of the cpu. the nmi request held pending is acknowledged upon completion of processing of the nmi currently being executed (following reti instruction execution). (2) if an intwdt1 request newly occurs during nmi processing if the np bit of psw remains set (to 1) during nmi processing, the new intwdt1 request is held pending. the intwdt1 request held pending is acknowledged upon completion of processing of the nmi currently being executed (following reti instruction execution). if the np bit of psw is cleared (to 0) during nmi processing, a newly generated intwdt1 request is executed (nmi processing is interrupted). (3) if an intwdt2 request newly occurs during nmi processing a newly generated intwdt2 request is executed regardless of the value of the np bit of psw (nmi processing is interrupted). caution when a non-maskable interrupt request is generated, the pc and psw values are saved to the nmi occurrence status save registers (fepc, fepsw), but only nmis can be restored via the reti instruction at this time. in the case of intwdt1 and intwdt2, restoration through the reti instruction is not possible, so perform system reset following completion of interrupt servicing. chapter 19 interrupt/exception processing function user?s manual u15862ej3v0ud 615 figure 19-1. acknowledging non-maskable interrupt requests (1/2) (a) if two or more nmi requests are simultaneously generated main routine system reset nmi, intwdt2 request (simultaneously generated) intwdt2 processing nmi and intwdt2 requests simultaneously generated main routine system reset nmi, intwdt1 request (simultaneously generated) intwdt1 processing nmi and intwdt1 requests simultaneously generated main routine system reset nmi, intwdt1, intwdt2 requests (simultaneously generated) intwdt2 processing nmi, intwdt1, and intwdt2 requests simultaneously generated main routine system reset intwdt1, intwdt2 request (simultaneously generated) intwdt2 processing intwdt1 and intwdt2 requests simultaneously generated chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 616 figure 19-1. acknowledging non-maskable interrupt requests (2/2) (b) if a new nmi request is generated during a non-maskable interrupt servicing non-maskable interrupt currently being serviced non-maskable interrupt request newly generated during non-maskable interrupt servicing nmi intwdt1 intwdt2 nmi generation of nmi request during nmi processing generation of intwdt request during nmi processing (np = 1 state prior to intwdt request is maintained) generation of intwdt request during nmi processing (set np = 0 before intwdt request) generation of intwdt request during nmi processing (set np = 0 after intwdt request) generation of intwdt2 request during nmi processing main routine nmi request nmi processing (held pending) nmi processing nmi request (hold pending) main routine system reset nmi request nmi request nmi processing intwdt processing intwdt request (hold pending) main routine system reset nmi request nmi request nmi processing intwdt processing intwdt request np = 0 np = 0 main routine system reset intwdt2 request nmi processing intwdt2 processing generation of intwdt2 request during intwdt1 processing main routine system reset intwdt1 request intwdt1 processing intwdt2 processing intwdt2 request main routine system reset nmi processing intwdt processing intwdt (hold pending) request intwdt (invalid) request generation of intwdt request during intwdt processing main routine system reset intwdt processing generation of nmi request during intwdt processing intwdt1 intwdt2 main routine system reset intwdt request intwdt request intwdt processing nmi request (invalid) nmi request (invalid) generation of intwdt2 request during intwdt2 processing generation of intwdt1 request during intwdt2 processing main routine system reset intwdt2 processing main routine system reset intwdt2 processing generation of nmi request during intwdt2 processing main routine system reset intwdt2 request intwdt2 request intwdt2 processing intwdt1 (invalid) request intwdt2 (invalid) request chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 617 19.2.1 operation upon generation of a non-maskable interrupt request, the cpu performs the following processing and transfers control to a handler routine. <1> saves the restored pc to fepc. <2> saves the current psw to fepsw. <3> writes the exception code 0010h to the higher halfword (fecc) of ecr. <4> sets the np and id bits of the psw and clears the ep bit. <5> loads the handler address of the non-maskable interrupt to the pc and transfers control. figure 19-2. non-maskable interrupt servicing nmi input non-maskable interrupt request interrupt servicing interrupt request held pending fepc fepsw ecr. fecc psw. np psw. ep psw. id pc restored pc psw exception code 1 0 1 handler address intc acknowledged cpu processing psw. np 1 0 chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 618 19.2.2 restore execution is restored from non-maskable interrupt servicing by the reti instruction. (1) in case of nmi restore from nmi processing is done with the reti instruction. when the reti instruction is executed, the cpu performs the following processing and transfers control to the address of the restored pc. (i) loads the values of the restored pc and psw from fepc and fepsw, respectively, because the ep bit and np bit of the psw are 0 and 1, respectively. (ii) transfers control back to the loaded address of the restored pc and psw. figure 19-3 shows the processing flow of the reti instruction. figure 19-3. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and psw.np bit are changed by the ldsr instruction during non- maskable interrupt servicing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow. (2) in case of intwdt1, intwdt2 restoring with the reti instruction is not performed. perform system reset following the completion of interrupt servicing. chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 619 19.2.3 np flag the np flag is a status flag that indicates that non-maskable interrupt servicing is in progress. this flag is set when a non-maskable interrupt request has been acknowledged, and masks all non-maskable requests to prevent multiple interrupts. 0 np ep id sat cy ov s z psw no non-maskable interrupt servicing non-maskable interrupt serving in progress np 0 1 nmi servicing status after reset : 00000020h 19.2.4 noise elimination for nmi pin nmi pin noise is eliminated by a on-chip noise eliminator that uses analog delay. therefore, a signal input to the nmi pin is not detected as an edge unless it maintains its input level for a certain period. the edge is detected only after a certain period has elapsed. the nmi pin is used for releasing the stop mode. in the stop mode, noise elimination using the system clock is not performed because the internal system clock is stopped. chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 620 19.2.5 edge detection function for nmi pin the nmi valid edge can be selected from the following four types: falling edge, rising edge, both edges, and no edge detection. rising edge specification register 0 (intr0) and falling edge specification register 0 (intf0) specify the valid edge of non-maskable interrupts (nmi). these two registers can be read/written in 8-bit or 1-bit units. after reset, the edge detection for the nmi pin is set to ? no edge detection ? . therefore, the nmi pin functions as a normal port and interrupt requests cannot be acknowledged unless a valid edge is specified by the intf0 and intr0 registers. when using p02 as an output port, set the nmi pin valid edge to ? no edge detection ? . (1) external interrupt rising edge specification register 0 (intr0) this is an 8-bit register that specifies the rising edge of the nmi pin. this register can be read/written in 8-bit or 1-bit units. caution when switching to the port function from the external interrupt function (alternate function), edge detection may be performed. therefore, set the port mode after setting intf0n = intr0n = 0. 0 intr0 intr06 intr05 intr04 intr03 intr02 0 0 after reset : 00h r/w address : fffffc20h remark for specification of the valid edge, refer to table 19-4 . (2) external interrupt falling edge specification register 0 (intf0) this is an 8-bit register that specifies the falling edge of the nmi pin. this register can be read/written in 8-bit or 1-bit units. caution when switching to the port function from the external interrupt function (alternate function), edge detection may be performed. therefore, set the port mode after setting intf0n = intr0n = 0. 0 intf0 intf06 intf05 intf04 intf03 intf02 0 0 after reset : 00h r/w address : fffffc00h remark for specification of the valid edge, refer to table 19-4 . chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 621 table 19-4. nmi valid edge specification intf02 intr02 nmi valid edge specification 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both edges chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 622 19.3 maskable interrupts maskable interrupt requests can be masked by interrupt control registers. the v850es/kf1, v850es/kg1, and v850es/kj1 have 33 to 45 maskable interrupt sources (refer to 19.1.1 features ). if two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight levels of interrupt priorities can be specified by using the interrupt control registers, allowing programmable priority control. when an interrupt request has been acknowledged, the interrupt disabled (di) status is set and the acknowledgement of other maskable interrupts is disabled. when the ei instruction is executed in an interrupt servicing routine, the interrupt enabled (ei) status is set, which enables acknowledgement of interrupts having a priority higher than that of the interrupt request currently in progress. note that only interrupts with a higher priority have this capability; interrupts with the same priority level cannot be nested. to use multiple interrupts, it is necessary to save eipc and eipsw to memory or a register before executing the ei instruction, and restore eipc and eipsw to the original values by executing the di instruction before the reti instruction. when the wdtm14 bit of watchdog timer mode register 1 (wdtm1) is set to 0, the watchdog timer overflow interrupt functions as a maskable interrupt (intwdtm1). 19.3.1 operation if a maskable interrupt request is generated, the cpu performs the following processing and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower halfword of ecr (eicc). <4> sets the id bit of the psw and clears the ep bit. <5> loads the corresponding handler address to the pc and transfers control. the maskable interrupt request masked by intc and the maskable interrupt request that occurs while another interrupt is being serviced (when psw.np = 1 or psw.id = 1) are held pending internally. when the interrupts are unmasked, or when psw.np = 0 and psw.id = 0 by using the reti and ldsr instructions, a new maskable interrupt servicing is started in accordance with the priority of the pending maskable interrupt request. figure 19-4 shows the servicing flow for maskable interrupts. chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 623 figure 19-4. maskable interrupt servicing maskable interrupt request interrupt servicing eipc eipsw ecr. eicc psw. ep psw. id pc intc acknowledged cpu processing interrupt mask released? priority higher than that of interrupt currently being serviced? interrupt request pending psw. np psw. id interrupt request pending no no no no 1 0 1 0 int input yes yes yes yes priority higher than that of other interrupt requests? highest default priority of interrupt requests with the same priority? restored pc psw exception code 0 1 handler address chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 624 19.3.2 restore execution is restored from maskable interrupt servicing by the reti instruction. operation of reti instruction when the reti instruction is executed, the cpu performs the following processing and transfers control to the address of the restored pc. (1) loads the values of the restored pc and psw from eipc and eipsw because the ep bit and np bit of the psw are both 0. (2) transfers control to the loaded address of the restored pc and psw. figure 19-5 shows the processing flow of the reti instruction. figure 19-5. reti instruction processing reti instruction original processing restored pc psw eipc eipsw psw. ep 1 0 1 0 pc psw fepc fepsw psw. np caution when the psw.ep bit and psw.np bit are changed by the ldsr instruction during maskable interrupt servicing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 0 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow. chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 625 19.3.3 priorities of maskable interrupts the v850es/kf1, v850es/kg1, and v850es/kj1 provide a multiple interrupt servicing in which an interrupt can be acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels specified by the interrupt priority level specification bit (xxprn). when two or more interrupts having the same priority level specified by xxprn are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request (default priority level) beforehand. for more information, refer to tables 19-1 , 19-2 , and 19-3 interrupt sources . programmable priority control divides interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request is acknowledged, the id flag of the psw is automatically set (1). therefore, when multiple interrupts are to be used, clear (0) the id flag beforehand (for example, by placing the ei instruction into the interrupt service program) to enable interrupts. chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 626 figure 19-6. example of interrupt nesting (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b interrupt request b (level 2) servicing of c interrupt request c (level 3) interrupt request d (level 2) servicing of d servicing of e ei interrupt request e (level 2) interrupt request f (level 3) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. caution the values of eipc and eipsw must be saved before executing multiple interrupts. remarks 1. a to u in the figure are the names of interrupt requests shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests. chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 627 figure 19-6. example of interrupt nesting (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt requests n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after processing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. notes 1. lower default priority 2. higher default priority chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 628 figure 19-7. example of servicing simultaneously generated interrupt requests main routine ei interrupt request a (level 2) interrupt request b (level 1) note 1 interrupt request c (level 1) note 2 servicing of interrupt request b servicing of interrupt request c servicing of interrupt request a interrupt requests b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first because it has the higher default priority. notes 1. higher default priority 2. lower default priority chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 629 19.3.4 interrupt control register (xxlcn) an interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. the interrupt control registers can be read/written in 8-bit or 1-bit units. caution be sure to read the xxifn bit of the xxicn register while interrupts are disabled (di). if the xxifn bit is read while interrupts are enabled (ei), an incorrect value may be read if there is a conflict between acknowledgement of the interrupt and reading of the bit. xxifn interrupt request not generated interrupt request generated xxifn 0 1 interrupt request flag note xxicn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 enables interrupt servicing disables interrupt servicing (pending) xxmkn 0 1 interrupt mask flag specifies level 0 (highest) specifies level 1 specifies level 2 specifies level 3 specifies level 4 specifies level 5 specifies level 6 specifies level 7 (lowest) xxprn2 0 0 0 0 1 1 1 1 interrupt priority specification bit xxprn1 0 0 1 1 0 0 1 1 xxprn0 0 1 0 1 0 1 0 1 after reset: 47h r/w address: fffff110h to fffff168h < > < > note automatically reset by hardware when interrupt request is acknowledged. remark xx: identifying name of each peripheral unit (csi0, tm5, tm0, p, wdt, brg, wt, wti, kr, ad, iic, csia, tmh, st, sr, sre) n: peripheral unit number (see tables 19-5 to 19-7 .) following tables list the addresses and bits of the interrupt control registers. chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 630 table 19-5. interrupt control registers (xxlcn) (v850es/kf1) bits address register <7><6>543210 fffff110h wdt1ic wdt1if wdt1mk 0 0 0 wdt1pr2 wdt1pr1 wdt1pr0 fffff112h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff114h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff116h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff118h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff11ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff11ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff11eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff120h tm0ic00 tm0if00 tm0mk00 0 0 0 tm0pr002 tm0pr001 tm0pr000 fffff122h tm0ic01 tm0if01 tm0mk01 0 0 0 tm0pr012 tm0pr011 tm0pr010 fffff124h tm0ic10 tm0if10 tm0mk10 0 0 0 tm0pr102 tm0pr101 tm0pr100 fffff126h tm0ic11 tm0if11 tm0mk11 0 0 0 tm0pr112 tm0pr111 tm0pr110 fffff128h tm5ic0 tm5if0 tm5mk0 0 0 0 tm5pr02 tm5pr01 tm5pr00 fffff12ah tm5ic1 tm5if1 tm5mk1 0 0 0 tm5pr12 tm5pr11 tm5pr10 fffff12ch csi0ic0 csi0if0 csi0mk0 0 0 0 csi0pr02 csi0pr01 csi0pr00 fffff12eh csi0ic1 csi0if1 csi0mk1 0 0 0 csi0pr12 csi0pr11 csi0pr10 fffff130h sreic0 sreif0 sremk0 0 0 0 srepr02 srepr01 srepr00 fffff132h sric0 srif0 srmk0 0 0 0 srpr02 srpr01 srpr00 fffff134h stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff136h sreic1 sreif1 sremk1 0 0 0 srepr12 srepr11 srepr10 fffff138h sric1 srif1 srmk1 0 0 0 srpr12 srpr11 srpr10 fffff13ah stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff13ch tmhic0 tmhif0 tmhmk0 0 0 0 tmhpr02 tmhpr01 tmhpr00 fffff13eh tmhic1 tmhif1 tmhmk1 0 0 0 tmhpr12 tmhpr11 tmhpr10 fffff140h csiaic0 csiaif0 csiamk0 0 0 0 csiapr02 csiapr01 csiapr00 fffff142h iicic0 note iicif0 iicmk0 0 0 0 iicpr02 iicpr01 iicpr00 fffff144h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff146h kric krif krmk 0 0 0 krpr2 krpr1 krpr0 fffff148h wtiic wtiif wtiimk 0 0 0 wtipr2 wtipr1 wtipr0 fffff14ah wtic wtif wtmk 0 0 0 wtpr2 wtpr1 wtpr0 fffff14ch brgic brgif brgmk 0 0 0 brgpr2 brgpr1 brgpr0 note only for the pd703208y, 703209y, 703210y, and 70f3210y chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 631 table 19-6. interrupt control registers (xxlcn) (v850es/kg1) bits address register <7><6>543210 fffff110h wdt1ic wdt1if wdt1mk 0 0 0 wdt1pr2 wdt1pr1 wdt1pr0 fffff112h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff114h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff116h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff118h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff11ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff11ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff11eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff120h tm0ic00 tm0if00 tm0mk00 0 0 0 tm0pr002 tm0pr001 tm0pr000 fffff122h tm0ic01 tm0if01 tm0mk01 0 0 0 tm0pr012 tm0pr011 tm0pr010 fffff124h tm0ic10 tm0if10 tm0mk10 0 0 0 tm0pr102 tm0pr101 tm0pr100 fffff126h tm0ic11 tm0if11 tm0mk11 0 0 0 tm0pr112 tm0pr111 tm0pr110 fffff128h tm5ic0 tm5if0 tm5mk0 0 0 0 tm5pr02 tm5pr01 tm5pr00 fffff12ah tm5ic1 tm5if1 tm5mk1 0 0 0 tm5pr12 tm5pr11 tm5pr10 fffff12ch csi0ic0 csi0if0 csi0mk0 0 0 0 csi0pr02 csi0pr01 csi0pr00 fffff12eh csi0ic1 csi0if1 csi0mk1 0 0 0 csi0pr12 csi0pr11 csi0pr10 fffff130h sreic0 sreif0 sremk0 0 0 0 srepr02 srepr01 srepr00 fffff132h sric0 srif0 srmk0 0 0 0 srpr02 srpr01 srpr00 fffff134h stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff136h sreic1 sreif1 sremk1 0 0 0 srepr12 srepr11 srepr10 fffff138h sric1 srif1 srmk1 0 0 0 srpr12 srpr11 srpr10 fffff13ah stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff13ch tmhic0 tmhif0 tmhmk0 0 0 0 tmhpr02 tmhpr01 tmhpr00 fffff13eh tmhic1 tmhif1 tmhmk1 0 0 0 tmhpr12 tmhpr11 tmhpr10 fffff140h csiaic0 csiaif0 csiamk0 0 0 0 csiapr02 csiapr01 csiapr00 fffff142h iicic0 note iicif0 iicmk0 0 0 0 iicpr02 iicpr01 iicpr00 fffff144h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff146h kric krif krmk 0 0 0 krpr2 krpr1 krpr0 fffff148h wtiic wtiif wtiimk 0 0 0 wtipr2 wtipr1 wtipr0 fffff14ah wtic wtf wtmk 0 0 0 wtpr2 wtpr1 wtpr0 fffff14ch brgic brgif brgmk 0 0 0 brgpr2 brgpr1 brgpr0 fffff14eh tm0ic20 tm0if20 tm0mk20 0 0 0 tm0pr202 tm0pr201 tm0pr200 fffff150h tm0ic21 tm0if21 tm0mk21 0 0 0 tm0pr212 tm0pr211 tm0pr210 fffff152h tm0ic30 tm0if30 tm0mk30 0 0 0 tm0pr302 tm0pr301 tm0pr300 fffff154h tm0ic31 tm0if31 tm0mk31 0 0 0 tm0pr312 tm0pr311 tm0pr310 fffff156h csiaic1 csiaif1 csiamk1 0 0 0 csiapr12 csiapr11 csiapr10 note only for the pd703212y, 703213y, 703214y, and 70f3214y chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 632 table 19-7. interrupt control registers (xxlcn) (v850es/kj1) (1/2) bits address register <7><6>543210 fffff110h wdt1ic wdt1if wdt1mk 0 0 0 wdt1pr2 wdt1pr1 wdt1pr0 fffff112h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff114h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff116h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff118h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff11ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff11ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff11eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff120h tm0ic00 tm0if00 tm0mk00 0 0 0 tm0pr002 tm0pr001 tm0pr000 fffff122h tm0ic01 tm0if01 tm0mk01 0 0 0 tm0pr012 tm0pr011 tm0pr010 fffff124h tm0ic10 tm0if10 tm0mk10 0 0 0 tm0pr102 tm0pr101 tm0pr100 fffff126h tm0ic11 tm0if11 tm0mk11 0 0 0 tm0pr112 tm0pr111 tm0pr110 fffff128h tm5ic0 tm5if0 tm5mk0 0 0 0 tm5pr02 tm5pr01 tm5pr00 fffff12ah tm5ic1 tm5if1 tm5mk1 0 0 0 tm5pr12 tm5pr11 tm5pr10 fffff12ch csi0ic0 csi0if0 csi0mk0 0 0 0 csi0pr02 csi0pr01 csi0pr00 fffff12eh csi0ic1 csi0if1 csi0mk1 0 0 0 csi0pr12 csi0pr11 csi0pr10 fffff130h sreic0 sreif0 sremk0 0 0 0 srepr02 srepr01 srepr00 fffff132h sric0 srif0 srmk0 0 0 0 srpr02 srpr01 srpr00 fffff134h stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff136h sreic1 sreif1 sremk1 0 0 0 srepr12 srepr11 srepr10 fffff138h sric1 srif1 srmk1 0 0 0 srpr12 srpr11 srpr10 fffff13ah stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff13ch tmhic0 tmhif0 tmhmk0 0 0 0 tmhpr02 tmhpr01 tmhpr00 fffff13eh tmhic1 tmhif1 tmhmk1 0 0 0 tmhpr12 tmhpr11 tmhpr10 fffff140h csiaic0 csiaif0 csiamk0 0 0 0 csiapr02 csiapr01 csiapr00 fffff142h iicic0 note iicif0 iicmk0 0 0 0 iicpr02 iicpr01 iicpr00 fffff144h adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff146h kric krif krmk 0 0 0 krpr2 krpr1 krpr0 fffff148h wtiic wtiif wtiimk 0 0 0 wtipr2 wtipr1 wtipr0 fffff14ah wtic wtif wtmk 0 0 0 wtpr2 wtpr1 wtpr0 fffff14ch brgic brgif brgmk 0 0 0 brgpr2 brgpr1 brgpr0 fffff14eh tm0ic20 tm0if20 tm0mk20 0 0 0 tm0pr202 tm0pr201 tm0pr200 fffff150h tm0ic21 tm0if21 tm0mk21 0 0 0 tm0pr212 tm0pr211 tm0pr210 fffff152h tm0ic30 tm0if30 tm0mk30 0 0 0 tm0pr302 tm0pr301 tm0pr300 fffff154h tm0ic31 tm0if31 tm0mk31 0 0 0 tm0pr312 tm0pr311 tm0pr310 fffff156h csiaic1 csiaif1 csiamk1 0 0 0 csiapr12 csiapr11 csiapr10 fffff158h tm0ic40 tm0if40 tm0mk40 0 0 0 tm0pr402 tm0pr401 tm0pr400 fffff15ah tm0ic41 tm0if41 tm0mk41 0 0 0 tm0pr412 tm0pr411 tm0pr410 fffff15ch tm0ic50 tm0if50 tm0mk50 0 0 0 tm0pr502 tm0pr501 tm0pr500 fffff15eh tm0ic51 tm0if51 tm0mk51 0 0 0 tm0pr512 tm0pr511 tm0pr510 fffff160h csi0ic2 csi0if2 csi0mk2 0 0 0 csi0pr22 csi0pr21 csi0pr20 note only for the pd703216y, 703217y, and 70f3217y chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 633 table 19-7. interrupt control registers (xxlcn) (v850es/kj1) (2/2) bits address register <7><6>543210 fffff162h sreic2 sreif2 sremk2 0 0 0 srepr22 srepr21 srepr20 fffff164h sric2 srif2 srmk2 0 0 0 srpr22 srpr21 srpr20 fffff166h stic2 stif2 stmk2 0 0 0 stpr22 stpr21 stpr20 fffff168h iicic1 note iicif1 iicmk1 0 0 0 iicpr12 iicpr11 iicpr10 note only for the pd703216y, 703217y, and 70f3217y chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 634 19.3.5 interrupt mask registers 0 to 2 (imr0 to imr2) these registers set the interrupt mask status for maskable interrupts. bits xxmkn of the imr0 to imr2 register and bits xxmkn of the xxlcn register are respectively linked. the imrm register can be read/written in 16-bit units (m = 0 to 2). when the higher 8 bits of the imrm register are treated as the imrmh register and the lower 8 bits of the imrm register as the imrml register, they can be read/written in 8-bit or 1-bit units (m = 0 to 2). caution in the device file, the xxmkn bit of the xxicn register is defined as a reserved word. therefore, if bit manipulation is performed using the name xxmkn, the xxicn register, not the imrm register, is rewritten (as a result, the imrm register is also rewritten). (i) v850es/kf1 csi0mk1 pmk6 imr0 (imr0h note ) (imr0l) csi0mk0 pmk5 tm5mk1 pmk4 tm5mk0 pmk3 tm0mk11 pmk2 tm0mk10 pmk1 tm0mk01 pmk0 tm0mk00 wdt1mk after reset: ffffh r/w address: fffff100h (imr0, imr0l), fffff101h (imr0h) after reset: ffffh r/w address: fffff102h (imr1, imr1l), fffff103h (imr1h) 1 tmhmk1 imr1 (imr1h note ) (imr1l) brgmk tmhmk0 wtmk stmk1 wtimk srmk1 krmk sremk1 admk stmk0 iicmk0 srmk0 csiamk0 sremk0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 xxmkn 0 1 enables interrupt servicing disables interrupt servicing interrupt mask flag setting note when reading from or writing to bits 8 to 15 of the imr0 and imr1 registers in 8-bit or 1- bit units, specify these bits as bits 0 to 7 of the imr0h and imr1h registers. caution bit 15 of the imr1 register is fixed to 1. the operation is not generated if the value is changed. remark xx: identifying name of each peripheral unit (csi0, tm5, tm0, p, wdt, brg, wt, wti, kr, ad, iic, csia, tmh, st, sr, sre) n: peripheral unit number (see tables 19-5 to 19-7 .) chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 635 (ii) v850es/kg1 csi0mk1 pmk6 imr0 (imr0h note ) (imr0l) csi0mk0 pmk5 tm5mk1 pmk4 tm5mk0 pmk3 tm0mk11 pmk2 tm0mk10 pmk1 tm0mk01 pmk0 tm0mk00 wdt1mk after reset: ffffh r/w address: fffff100h (imr0, imr0l), fffff101h (imr0h) after reset: ffffh r/w address: fffff102h (imr1, imr1l), fffff103h (imr1h) after reset: ffffh r/w address: fffff104h (imr2, imr2l), fffff105h (imr2h) tm0mk20 tmhmk1 imr1 (imr1h note ) (imr1l) brgmk tmhmk0 wtmk stmk1 wtimk srmk1 krmk sremk1 admk stmk0 iicmk0 srmk0 csiamk0 sremk0 1 1 xxmkn 0 1 enables interrupt servicing disables interrupt servicing imr2 (imr2h note ) (imr2l) 1 1 1 1 1 1 1 csiamk1 1 tm0mk31 1 tm0mk30 1 tm0mk21 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 interrupt mask flag setting 14 15 1 2 3 4 5 6 7 0 note when reading from or writing to bits 8 to 15 of the imr0 to imr2 registers in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the imr0h to imr2h registers. caution bits 15 to 4 of the imr2 register are fixed to 1. the operation is not guaranteed if their value is changed. remark xx: identifying name of each peripheral unit (csi0, tm5, tm0, p, wdt, brg, wt, wti, kr, ad, iic, csia, tmh, st, sr, sre) n: peripheral unit number (see tables 19-5 to 19-7 .) chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 636 (iii) v850es/kj1 csi0mk1 pmk6 imr0 (imr0h note ) (imr0l) csi0mk0 pmk5 tm5mk1 pmk4 tm5mk0 pmk3 tm0mk11 pmk2 tm0mk10 pmk1 tm0mk01 pmk0 tm0mk00 wdt1mk after reset: ffffh r/w address: fffff100h (imr0, imr0l), fffff101h (imr0h) after reset: ffffh r/w address: fffff102h (imr1, imr1l), fffff103h (imr1h) after reset: ffffh r/w address: fffff104h (imr2, imr2l), fffff105h (imr2h) tm0mk20 tmhmk1 imr1 (imr1h note ) (imr1l) brgmk tmhmk0 wtmk stmk1 wtimk srmk1 krmk sremk1 admk stmk0 iicmk0 srmk0 csiamk0 sremk0 1 tm0mk51 xxmkn 0 1 enables interrupt servicing disables interrupt servicing imr2 (imr2h note ) (imr2l) 1 tm0mk50 1 tm0mk41 iicmk1 tm0mk40 stmk2 csiamk1 srmk2 tm0mk31 sremk2 tm0mk30 csi0mk2 tm0mk21 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 interrupt mask flag setting 14 15 1 2 3 4 5 6 7 0 note when reading from or writing to bits 8 to 15 of the imr0 to imr2 registers in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the imr0h to imr2h registers. caution bits 15 to 13 of the imr2 register are fixed to 1. the operation is not guaranteed if their value is changed. remark xx: identifying name of each peripheral unit (csi0, tm5, tm0, p, wdt, brg, wt, wti, kr, ad, iic, csia, tmh, st, sr, sre) n: peripheral unit number (see tables 19-5 to 19-7 .) chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 637 19.3.6 in-service priority register (ispr) this register holds the priority level of the maskable interrupt currently being acknowledged. when the interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt is set (1) and remains set while the interrupt is being serviced. when the reti instruction is executed, the bit among those that are set (1) in the ispr register that corresponds to the interrupt request having the highest priority is automatically reset (0) by hardware. however, it is not reset (0) when execution is returned from non-maskable interrupt servicing or exception processing. this register can only be read, in 8-bit or 1-bit units. caution if an interrupt is acknowledged while the ispr register is being read in the interrupt enabled (ei) status, the value of the ispr register after the bits of the register have been set to 1 by acknowledging the interrupt may be read. to accurately read the value of the ispr register before an interrupt is acknowledged, read the register while interrupts are disabled (di status). ispr7 interrupt request with priority n is not acknowledged interrupt request with priority n is being acknowledged isprn 0 1 priority of interrupt currently being acknowledged ispr ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 after reset: 00h r address: fffff1fah < > < > < > < > < > < > < > < > remark n = 0 to 7 (priority level) chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 638 19.3.7 maskable interrupt status flag the interrupt disable flag (id) is allocated to the psw and controls the maskable interrupt ? s operating state, and stores control information regarding enabling/disabling reception of interrupt requests. 0 np ep id sat cy ov s z psw maskable interrupt acknowledgement enabled maskable interrupt acknowledgement disabled id 0 1 maskable interrupt servicing specification note after reset: 00000020h note interrupt disable flag (id) function id is set (1) by the di instruction and reset (0) by the ei instruction. its value is also modified by the reti instruction or ldsr instruction when referencing the psw. non-maskable interrupts and exceptions are acknowledged regardless of this flag. when a maskable interrupt is acknowledged, the id flag is automatically set (1) by hardware. an interrupt request generated during the acknowledgement disabled period (id = 1) can be acknowledged when the xxifn bit of xxicn is set (1), and the id flag is reset (0). chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 639 19.3.8 watchdog timer mode register 1 (wdtm1) this register is a special register that can be written to only in a special sequence. to generate a maskable interrupt (intwdt1), set the wdtm14 bit to 0. this register can be read/written in 8-bit or 1-bit units (for details, refer to chapter 12 watchdog timer functions ). run1 stop count operation clear counter and start count operation run1 0 1 watchdog timer operation mode selection note 1 wdtm1 0 0 wdtm14 wdtm13 0 0 0 after reset: 00h r/w address: fffff6c2h interval timer mode (generate maskable interrupt intwdtm1 when overflow occurs) watchdog timer mode 1 note 3 (generate non-maskable interrupt intwdt1 when overflow occurs) watchdog timer mode 2 (start wdtres2 reset operation when overflow occurs) wdtm14 0 0 1 1 wdtm13 0 1 0 1 watchdog timer operation mode selection note 2 < > notes 1. once the run1 bit has been set (1), it cannot be cleared (0) by software. therefore, once counting starts, it cannot be stopped except through reset input. 2. once the wdtm14 and wdtm13 bits have been set (1), they cannot be cleared (0) by software. reset input is the only way to clear these bits. 3. restoring using the reti instruction following a non-maskable interrupt servicing due to non-maskable interrupt request (intwdt1) is not possible. therefore, following completion of interrupt servicing, perform system reset. 19.3.9 elimination of noise from intp0 to intp6 (1) elimination of noise from intp0 to intp6 pins intp0 to intp6 pins incorporate a noise eliminator that uses analog delay to eliminate noise. therefore, only when a signal having a constant level is input for a specified time or longer, it is detected as a valid edge. edge detection occurs only after the specified length of time has elapsed. chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 640 19.3.10 intp0 to intp6 edge detection function the valid edges of the intp0 to intp6 pins can be selected from the following four types. ? rising edge ? falling edge ? both edges ? no edge detection (1) external interrupt rising edge specification register 0 (intr0) this is an 8-bit register that specifies detection of the rising edge of the intp0 to intp3 pins. this register can be read/written in 8-bit or 1-bit units. caution when switching to the port function from the external interrupt function (alternate function), edge detection may be performed. therefore, set the port mode after setting intf0n = intr0n = 0. 0 intr0 intr06 intr05 intr04 intr03 intr02 0 0 after reset: 00h r/w address: fffffc20h remark for specification of the valid edge, refer to table 19-8 . (2) external interrupt falling edge specification register 0 (intf0) this is an 8-bit register that specifies detection of the falling edge of the intp0 to intp3 pins. this register can be read/written in 8-bit or 1-bit units. caution when switching to the port function from the external interrupt function (alternate function), edge detection may be performed. therefore, set the port mode after setting intf0n = intr0n = 0. 0 intf0 intf06 intf05 intf04 intf03 intf02 0 0 after reset: 00h r/w address: fffffc00h remark for specification of the valid edge, refer to table 19-8 . chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 641 table 19-8. intp0 to intp3 pins valid edge specification intf0n intr0n valid edge specification (n = 3 to 6) 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 3 to 6: control of intp0 to intp3 pins (3) external interrupt rising edge specification register 9h (intr9h) this is an 8-bit register that specifies detection of the rising edge of the intp4 to intp6 pins. this register can be read/written in 8-bit or 1-bit units. caution when switching to the port function from the external interrupt function (alternate function), edge detection may be performed. therefore, set the port mode after setting intf9n = intr9n = 0. intr915 intr9h intr914 intr913 0 0 0 0 0 after reset: 00h r/w address: fffffc33h remark for specification of the valid edge, refer to table 19-9 . (4) external interrupt falling edge specification register 9h (intf9h) this is an 8-bit register that specifies detection of the falling edge of the intp4 to intp6 pins. this register can be read/written in 8-bit or 1-bit units. caution when switching to the port function from the external interrupt function (alternate function), edge detection may be performed. therefore, set the port mode after setting intf9n = intr9n = 0. intf915 intf9h intf914 intf913 0 0 0 0 0 after reset: 00h r/w address: fffffc13h remark for specification of the valid edge, refer to table 19-9 . chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 642 table 19-9. intp4 to intp6 pins valid edge specification intf9n intr9n valid edge specification (n = 13 to 15) 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both edges remark n = 13 to 15: control of intp4 to intp6 pins chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 643 19.4 software exceptions a software exception is generated when the cpu executes the trap instruction. software exceptions can always be acknowledged. 19.4.1 operation if a software exception occurs, the cpu performs the following processing and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the ep and id bits of the psw. <5> loads the handler address (00000040h or 00000050h) for the software exception routine to the pc and transfers control. figure 19-8 shows the software exception processing flow. figure 19-8. software exception processing trap instruction note eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note trap instruction format: trap vector (however, vector = 0 to 1fh) the handler address is determined by the operand (vector) of the trap instruction. if the vector is 0 to 0fh, the handler address is 00000040h, and if the vector is 10 to 1fh, the handler address is 00000050h. chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 644 19.4.2 restore execution is restored from software exception processing by the reti instruction. when the reti instruction is executed, the cpu performs the following processing and transfers control to the address of the restored pc. <1> loads the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. <2> transfers control to the address of the restored pc and psw. figure 19-9 shows the processing flow of the reti instruction. figure 19-9. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and psw.np bit are changed by the ldsr instruction during software exception processing, in order to restore the pc and psw correctly during restoring by the reti instruction, it is necessary to set psw.ep back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow. chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 645 19.4.3 exception status flag (ep) the ep flag, which is bit 6 of the psw, is a status flag that indicates that exception processing is in progress. it is set when an exception occurs. 0 np ep id sat cy ov s z psw exception processing not in progress exception processing in progress ep 0 1 exception processing status after reset: 00000020h chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 646 19.5 exception trap the exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. in the v850es/kf1, v850es/kg1, and v850es/kj1, an illegal op code trap (ilgop: illegal op code trap) is considered as an exception trap. 19.5.1 illegal op code an illegal op code is defined as an instruction with instruction op code (bits 10 to 5) = 111111b, sub-op code (bits 26 to 23) = 0111b to 1111b, and sub-op code (bit 16) = 0b. when such an instruction is executed, an exception trap is generated. 15 16 23 22 xxxxxx0 x x x x x x x x x x 1 1 1 1 1 1 x x x x x 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 x: don ? t care caution it is recommended not to use illegal op code because instructions may newly be assigned in the future. (1) operation upon generation of an exception trap, the cpu performs the following processing and transfers control to a handler routine. <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the np, ep, and id bits of the psw. <4> loads the handler address (00000060h) for the exception trap routine to the pc and transfers control. figure 19-10 shows the exception trap processing flow. chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 647 figure 19-10. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore execution is restored from exception trap processing by the dbret instruction. when the dbret instruction is executed, the cpu performs the following processing and transfers control to the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the loaded address of the restored pc and psw. figure 19-11 shows the processing flow for restore from exception trap processing. figure 19-11. processing flow for restore from exception trap dbret instruction pc psw dbpc dbpsw jump to restored pc address chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 648 19.5.2 debug trap a debug trap is an exception that occurs upon execution of the dbtrap instruction and that can be acknowledged at all times. when a debug trap occurs, the cpu performs the following processing. (1) operation <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the np, ep, and id bits of the psw. <4> sets the handler address (00000060h) for the debug trap routine to the pc and transfers control. figure 19-12 shows the debug trap processing flow. figure 19-12. debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 649 (2) restore execution is restored from debug trap processing by the dbret instruction. when the dbret instruction is executed, the cpu performs the following processing and transfers control to the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the loaded address of the restored pc and psw. figure 19-13 shows the processing flow for restore from debug trap processing. figure 19-13. processing flow for restore from debug trap dbret instruction pc psw dbpc dbpsw jump to restored pc address chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 650 19.6 multiple interrupt servicing control multiple interrupt servicing control is a function that stops an interrupt service routine currently in progress if a higher priority interrupt request is generated, and processes the acknowledgement operation of the higher priority interrupt. if an interrupt with a lower or equal priority is generated and a service routine is currently in progress, the later interrupt will be held pending. multiple interrupt servicing control is performed when interrupts are enabled (id = 0). even in an interrupt servicing routine, multiple interrupt control must be performed while interrupts are enabled (id = 0). if a maskable interrupt or software exception is generated in a maskable interrupt or software exception service program, eipc and eipsw must be saved. the following example illustrates the procedure. (1) to acknowledge maskable interrupt requests in service program service program for maskable interrupt or exception ? ? ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (enables interrupt acknowledgement) ? ? acknowledges maskable interrupt ? ? ? di instruction (disables interrupt acknowledgement) ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 651 (2) to generate exception in service program service program for maskable interrupt or exception ? ? ? eipc saved to memory or register ? eipsw saved to memory or register ? ? trap instruction acknowledges exceptions such as trap instruction. ? ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction priorities 0 to 7 (0 is the highest) can be set for each maskable interrupt request in multiple interrupt servicing control by software. to set a priority level, write values to the xxprn0 to xxprn2 bits of the interrupt request control register (xxicn) corresponding to each maskable interrupt request. after reset, interrupt requests are masked by the xxmkn bit, and the priority is set to level 7 by the xxprn0 to xxprn2 bits. priorities of maskable interrupts are as follows. (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt servicing that has been suspended as a result of multiple interrupt servicing control is resumed after the interrupt servicing of the higher priority has been completed and the reti instruction has been executed. a pending interrupt request is acknowledged after the current interrupt servicing has been completed and the reti instruction has been executed. caution in a non-maskable interrupt servicing routine (in the time until the reti instruction is executed), maskable interrupts are not acknowledged and held pending. chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 652 19.7 interrupt response time except in the following cases, the cpu interrupt response time is a minimum of 4 clocks. if inputting consecutive interrupt requests, at least 4 clocks must be placed between each interrupt. ? stop mode ? external bus access ? interrupt request non-sample instruction (refer to 19.8 periods in which interrupts are not acknowledged by cpu .) ? interrupt control register access figure 19-14. pipeline operation during interrupt request acknowledgment (outline) (1) minimum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgement operation instruction (first instruction of interrupt servicing routine) interrupt request if id ex mem wb ifx idx int1 int2 int3 int4 4 system clocks (2) maximum interrupt response time if id ex internal clock instruction 1 instruction 2 interrupt acknowledgement operation instruction (first instruction of interrupt servicing routine) interrupt request if id ex mem mem mem wb ifx idx int1 int2 int3 int3 int3 int4 6 system clocks int1 to int4: interrupt acknowledgement processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt response time (internal system clock) internal interrupt external interrupt condition min. 4 4 + analog delay max. 6 6 + analog delay the following cases are excluded. ? idle/stop mode ? external bus access ? consecutive interrupt request non-sample instruction ? access to interrupt control register ? access to peripheral i/o register chapter 19 interrupt/exception processing function user ? s manual u15862ej3v0ud 653 19.8 periods in which interrupts are not acknowledged by cpu interrupts are acknowledged by the cpu while an instruction is being executed. however, no interrupt is acknowledged between an interrupt request non-sample instruction and the next instruction. the following instructions are interrupt request non-sample instructions. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instructions (vs. psw) ? store instruction for the following registers ? command register (prcmd) ? interrupt-related registers: interrupt control register (xxlcn), interrupt mask registers 0 to 2 (imr0 to imr2), in-service priority register (ispr) user?s manual u15862ej3v0ud 654 chapter 20 key interrupt function 20.1 function a key interrupt (intkr) can be generated by inputting a falling edge to the eight key input pins (kr0 to kr7) by setting the key return mode register (krm). table 20-1. assignment of key return detection pins flag pin description krm0 controls kr0 signal in 1-bit units krm1 controls kr1 signal in 1-bit units krm2 controls kr2 signal in 1-bit units krm3 controls kr3 signal in 1-bit units krm4 controls kr4 signal in 1-bit units krm5 controls kr5 signal in 1-bit units krm6 controls kr6 signal in 1-bit units krm7 controls kr7 signal in 1-bit units figure 20-1. key return block diagram intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0 chapter 20 key interrupt function user ? s manual u15862ej3v0ud 655 20.2 key interrupt control register (1) key return mode register (krm) the krm register controls the krm0 to krm7 bits using the kr0 to kr7 signals. this register can be read/written in 8-bit or 1-bit units. reset input clears krm to 00h. krm7 does not detect key return signal detects key return signal krmn 0 1 key return mode control krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 after reset: 00h r/w address: fffff300h caution if the key return mode register (krm) is changed, an interrupt request flag may be set. to prevent this, change the krm register after disabling interrupts, and then enable interrupts after clearing the interrupt request flag. user?s manual u15862ej3v0ud 656 chapter 21 standby function 21.1 overview the power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. the available standby modes are listed in table 21-1. table 21-1. standby modes mode functional outline halt mode mode to stop only the operating clock of the cpu idle mode mode to stop all the internal operations of the chip except the oscillator note stop mode mode to stop all the internal operations of the chip except the subclock oscillator note subclock operation mode mode to use the subclock as the internal system clock sub-idle mode mode to stop all the internal operations of the chip, except the oscillator, in the subclock operation mode note the pll does not stop. stop the pll to reduce the current consumption before setting each standby mode. chapter 21 standby function user?s manual u15862ej3v0ud 657 figure 21-1. status transition (1/2) normal operation mode (operation with main clock) wait for stabilization of oscillation wait for stabilization of oscillation wait for stabilization of oscillation end of oscillation stabilization time count end of oscillation stabilization time count end of oscillation stabilization time count setting of halt mode interrupt request note 3 setting of stop mode idle mode halt mode stop mode reset input note 1 interrupt request note 2 setting of idle mode interrupt request note 4 reset input note 1 reset input note 1 notes 1. reset input by reset input or watchdog timer 2 overflow. 2. non-maskable interrupt request or unmasked maskable interrupt request. 3. non-maskable interrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp6 pin input), or unmasked internal interrupt request from peripheral functions operable in idle mode. 4. non-maskable interrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp6 pin input), or unmasked internal interrupt request from peripheral functions operable in stop mode. chapter 21 standby function user ? s manual u15862ej3v0ud 658 figure 21-1. status transition (2/2) normal operation mode (operation with main clock) subclock operation mode (operation with subclock) wait for stabilization of oscillation wait for stabilization of oscillation end of oscillation stabilization time count setting of subclock operation mode setting of normal operation mode end of oscillation stabilization time count sub-idle mode reset input note 1 interrupt request note 2 setting of idle mode reset input note 1 notes 1. reset input by reset input or watchdog timer 2 overflow. 2. non-maskable interrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp6 pin input), or unmasked internal interrupt request from peripheral functions operable in sub- idle mode. chapter 21 standby function user ? s manual u15862ej3v0ud 659 21.2 halt mode 21.2.1 setting and operation status the halt mode is set when a dedicated instruction (halt) is executed in the normal operation mode. in the halt mode, the clock oscillator continues operating. only clock supply to the cpu is stopped; clock supply to the other on-chip peripheral functions continues. as a result, program execution is stopped, and the internal ram retains the contents before the halt mode was set. the on-chip peripheral functions that are independent of instruction processing by the cpu continue operating. table 21-3 shows the operation status in the halt mode. the average power consumption of the system can be reduced by using the halt mode in combination with the normal operation mode for intermittent operation. caution insert five or more nop instructions after the halt instruction. 21.2.2 releasing halt mode the halt mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request, and reset pin input. after the halt mode has been released, the normal operation mode is restored. (1) releasing halt mode by non-maskable interrupt request or unmasked maskable interrupt request the halt mode is released by a non-maskable interrupt request or an unmasked maskable interrupt request, regardless of the priority of the interrupt request. if the halt mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the halt mode is released, and that interrupt request is not acknowledged. the interrupt request itself is retained. (b) if an interrupt request with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request), the halt mode is released and that interrupt request is acknowledged. table 21-2. operation after releasing halt mode by interrupt request release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request execution branches to the handler address maskable interrupt request execution branches to the handler address or the next instruction is executed the next instruction is executed (2) releasing halt mode by reset pin input the same operation as the normal reset operation is performed. chapter 21 standby function user ? s manual u15862ej3v0ud 660 table 21-3. operation status in halt mode setting of halt mode when cpu is operating with main clock item when subclock is not used when subclock is used cpu stops operation rom correction stops operation main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled interrupt controller operable 16-bit timers (tm00 to tm05) operable 8-bit timers (tm50, tm51) operable timer h (tmh0, tmh1) operable watch timer operable when main clock output is selected as count clock operable watchdog timer 1 operable watchdog timer 2 operable when main clock is selected as count clock operable csi00 to csi02 operable csia0 to csia1 operable i 2 c0 note , i 2 c1 note operable serial interface uart0 to uart2 operable key interrupt function operable a/d converter operable d/a converter operable real-time output operable port function retains status before halt mode was set. external bus interface refer to chapter 5 bus control function . internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the halt mode was set. note only products with i 2 c chapter 21 standby function user ? s manual u15862ej3v0ud 661 21.3 idle mode 21.3.1 setting and operation status the idle mode is set by clearing the psm bit of the power save mode register (psmr) to 0 and setting the stp bit of the power save control register (psc) to 1 in the normal operation mode. in the idle mode, the clock oscillator continues operation but clock supply to the cpu and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle mode was set are retained. the cpu and other on-chip peripheral functions stop operating. however, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. table 21-5 shows the operation status in the idle mode. the idle mode can reduce the current consumption more than the halt mode because it stops the operation of the on-chip peripheral functions. the main clock oscillator does not stop, so the normal operation mode can be restored without waiting for the oscillation stabilization time after the idle mode has been released, in the same manner as when the halt mode is released. caution insert five or more nop instructions after the instruction that stores data in the psc register to set the idle mode. 21.3.2 releasing idle mode the idle mode is released by a non-maskable interrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp6 pin input), unmasked internal interrupt request from the peripheral functions operable in the idle mode, or reset input. after the idle mode has been released, the normal operation mode is restored. (1) releasing idle mode by non-maskable interrupt request or unmasked maskable interrupt request the idle mode is released by a non-maskable interrupt request or an unmasked maskable interrupt request, regardless of the priority of the interrupt request. if the idle mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is processed as follows. (a) if an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the idle mode is released, and that interrupt request is not acknowledged. the interrupt request itself is retained. (b) if an interrupt request with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request), the idle mode is released and that interrupt request is acknowledged. table 21-4. operation after releasing idle mode by interrupt request release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request execution branches to the handler address maskable interrupt request execution branches to the handler address or the next instruction is executed the next instruction is executed chapter 21 standby function user ? s manual u15862ej3v0ud 662 (2) releasing idle mode by reset pin input the same operation as the normal reset operation is performed. table 21-5. operation status in idle mode setting of idle mode when cpu is operating with main clock item when subclock is not used when subclock is used cpu stops operation rom correction stops operation main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled interrupt controller stops operation 16-bit timers (tm00 to tm05) stops operation 8-bit timers (tm50, tm51) operable when ti5m is selected as count clock timer h (tmh0) stops operation timer h (tmh1) stops operation operable when f xt is selected as count clock watch timer operable when main clock output is selected as count clock operable watchdog timer 1 stops operation watchdog timer 2 stops operation operable when f xt is selected as count clock csi00 to csi02 operable when sck0n input clock is selected as operation clock csia0, csia1 stops operation i 2 c0 note , i 2 c1 note stops operation uart0 operable when asck0 is selected as count clock serial interface uart0, uart2 stops operation key interrupt function operable a/d converter stops operation d/a converter stops operation real-time output stops operation port function retains status before idle mode was set. external bus interface refer to chapter 5 bus control function . internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the idle mode was set. note only products with i 2 c remark m = 0 or 1 n = 0 to 2 chapter 21 standby function user ? s manual u15862ej3v0ud 663 21.4 stop mode 21.4.1 setting and operation status the stop mode is set when the psm bit of the power save mode register (psmr) is set to 1 and the stp bit of the power save control register (psc) is set to 1 in the normal operation mode. in the stop mode, the subclock oscillator continues operating but the main clock oscillator stops. clock supply to the cpu and the on-chip peripheral functions is stopped. as a result, program execution is stopped, and the contents of the internal ram before the stop mode was set are retained. the on-chip peripheral functions that operate with the clock oscillated by the subclock oscillator or an external clock continue operating. table 21-7 shows the operation status in the stop mode. because the stop stops operation of the main clock oscillator, it reduces the current consumption to a level lower than the idle mode. if the subclock oscillator and external clock are not used, the power consumption can be minimized with only leakage current flowing. caution insert five or more nop instructions after the instruction that stores data in the psc register to set the stop mode. 21.4.2 releasing stop mode the stop mode is released by a non-maskable interrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp6 pin input), unmasked internal interrupt request from the peripheral functions operable in the stop mode, or reset pin input. after the stop mode has been released, the normal operation mode is restored after the oscillation stabilization time has been secured. (1) releasing stop mode by non-maskable interrupt request or unmasked maskable interrupt request the stop mode is released by a non-maskable interrupt request or an unmasked maskable interrupt request, regardless of the priority of the interrupt request. if the software stop mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the stop mode is released, and that interrupt request is not acknowledged. the interrupt request itself is retained. (b) if an interrupt request with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request), the stop mode is released and that interrupt request is acknowledged. table 21-6. operation after releasing stop mode by interrupt request release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request execution branches to the handler address maskable interrupt request execution branches to the handler address or the next instruction is executed the next instruction is executed chapter 21 standby function user ? s manual u15862ej3v0ud 664 (2) releasing stop mode by reset pin input the same operation as the normal reset operation is performed. table 21-7. operation status in stop mode setting of stop when cpu is operating with main clock item mode when subclock is not used when subclock is used cpu stops operation rom correction stops operation main clock oscillator oscillation stops subclock oscillator ? oscillation enabled interrupt controller stops operation 16-bit timers (tm00 to tm05) stops operation 8-bit timers (tm50, tm51) operable when ti5m is selected as count clock timer h (tmh0) stops operation timer h (tmh1) stops operation operable when f xt is selected as count clock watch timer stops operation operable when f xt is selected as count clock watchdog timer 1 stops operation watchdog timer 2 stops operation operable when f xt is selected as count clock csi00 to csi02 operable when sck0n input clock is selected as operation clock csia0, csia1 stops operation i 2 c0 note , i 2 c1 note stops operation uart0 operable when asck0 is selected as count clock serial interface uart1, uart2 stops operation key interrupt function operable a/d converter stops operation d/a converter stops operation real-time output stops operation port function retains status before stop mode was set. external bus interface refer to chapter 5 bus control function . internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the stop mode was set. note only products with i 2 c remark m = 0 or 1 n = 0 to 2 chapter 21 standby function user ? s manual u15862ej3v0ud 665 21.5 securing oscillation stabilization time when the stop mode is released, only the oscillation stabilization time set by the oscillation stabilization time selection register (osts) elapses. if the software stop mode has been released by reset pin input, however, the reset value of the osts register, 2 15 /f x (8.192 ms at f x = 4 khz) elapses. the timer for counting the oscillation stabilization time is shared with watchdog timer 1, so the oscillation stabilization time equal to the overflow time of the watchdog timer elapses. figure 21-2 shows the operation performed when the stop mode is released by an interrupt request. figure 21-2. oscillation stabilization time oscillated waveform main clock oscillator stops oscillation stabilization time count main clock stop mode status interrupt request caution for details of the osts register, refer to 21.1.3 (1) oscillation stabilization time selection register (osts). chapter 21 standby function user ? s manual u15862ej3v0ud 666 21.6 subclock operation mode 21.6.1 setting and operation status the subclock operation mode is set when the ck3 bit of the processor clock control register (pcc) is set to 1 in the normal operation mode. when the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. when the mck bit of the pcc register is set to 1, the operation of the main clock oscillator is stopped. as a result, the system operates only with the subclock. however, watchdog timer 1 stops counting when subclock operation is started (cls bit of pcc register = 1). (watchdog timer 1 retains the value before the subclock operation mode was set.) table 21-8 shows the operation status in subclock operation mode. in the subclock operation mode, the current consumption can be reduced to a level lower than in the normal operation mode because the subclock is used as the internal system clock. in addition, the current consumption can be further reduced to the level of the stop mode by stopping the operation of the main system clock oscillator. caution when manipulating the ck3 bit of the pcc register, do not change the set values of the ck2 to ck0 bits (using a bit manipulation instruction to manipulate the bit is recommended). for details, refer to 6.3 (1) processor clock control register (pcc). 21.6.2 releasing subclock operation mode the subclock operation mode is released by reset pin input when the ck3 bit of the pcc register is cleared to 0. if the main clock is stopped (mck bit of pcc register = 1), set the mck bit of the pcc register to 1, secure the oscillation stabilization time of the main clock by software, and clear the ck3 bit of the pcc register to 0. the normal operation mode is restored when the subclock operation mode is released. caution when manipulating the ck3 bit of the pcc register, do not change the set values of the ck2 to ck0 bits (using a bit manipulation instruction to manipulate the bit is recommended). for details, refer to 6.3 (1) processor clock control register (pcc). chapter 21 standby function user ? s manual u15862ej3v0ud 667 table 21-8. operation status in subclock operation mode operation status setting of subclock operation mode item when main clock is oscillating when main clock is stopped cpu operable rom correction operable subclock oscillator oscillation enabled interrupt controller operable 16-bit timers (tm00 to tm05) operable stops operation 8-bit timers (tm50, tm51) operable operable when ti5m is selected as count clock timer h (tmh0) operable stops operation timer h (tmh1) operable operable when f xt is selected as count clock watch timer operable operable when f xt is selected as count clock watchdog timer 1 operable stops operation watchdog timer 2 operable operable when f xt is selected as count clock csi00 to csi02 operable operable when sck0n input clock is selected as operation clock csia0, csia1 operable stops operation i 2 c0 note , i 2 c1 note operable stops operation uart0 operable operable when asck0 is selected as count clock serial interface uart1, uart2 operable stops operation key interrupt function operable a/d converter operable stops operation d/a converter operable stops operation real-time output operable stops operation port function settable external bus interface operable internal data settable note only products with i 2 c remark m = 0 or 1 n = 0 to 2 chapter 21 standby function user ? s manual u15862ej3v0ud 668 21.7 sub-idle mode 21.7.1 setting and operation status the sub-idle mode is set when the psm bit of the power save mode register (psmr) is cleared to 0 and the stp bit of the power save control register (psc) is set to 1 in the subclock operation mode. in this mode, the clock oscillator continues operation but clock supply to the cpu and the other on-chip peripheral functions is stopped. as a result, program execution is stopped and the contents of the internal ram before the sub-idle mode was set are retained. the cpu and the other on-chip peripheral functions are stopped. however, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. table 21-10 shows the operation status in the sub-idle mode. because the sub-idle mode stops operation of the cpu and other on-chip peripheral functions, it can reduce the current consumption more than the subclock operation mode. if the sub-idle mode is set after the main clock has been stopped, the current consumption can be reduced to a level as low as that in the stop mode. 21.7.2 releasing sub-idle mode the sub-idle mode is released by a non-maskable interrupt request (nmi pin input), unmasked external interrupt request (intp0 to intp6 pin input), unmasked internal interrupt request from the peripheral functions operable in the sub-idle mode, or reset pin input. when the sub-idle mode is released by an interrupt request, the subclock operation mode is set. if it is released by reset pin input, the normal operation mode is restored. (1) releasing sub-idle mode by non-maskable interrupt request or unmasked maskable interrupt request the sub-idle mode is released by a non-maskable interrupt request or an unmasked maskable interrupt request, regardless of the priority of the interrupt request. if the sub-idle mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) if an interrupt request with a priority lower than that of the interrupt request currently being serviced is issued, only the sub-idle mode is released, and that interrupt request is not acknowledged. the interrupt request itself is retained. (b) if an interrupt request with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request), the sub-idle mode is released and that interrupt request is acknowledged. table 21-9. operation after releasing sub-idle mode by interrupt request release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request execution branches to the handler address maskable interrupt request execution branches to the handler address or the next instruction is executed the next instruction is executed (2) releasing sub-idle mode by reset pin input the same operation as the normal reset operation is performed. chapter 21 standby function user ? s manual u15862ej3v0ud 669 table 21-10. operation status in sub-idle mode setting of sub-idle mode operation status item when main clock is oscillating when main clock is stopped cpu stops operation rom correction stops operation subclock oscillator oscillation enabled interrupt controller stops operation 16-bit timers (tm00 to tm05) stops operation 8-bit timers (tm50, tm51) operable when ti5m is selected as count clock timer h (tmh0) stops operation timer h (tmh1) operable when f xt is selected as count clock watch timer stops operation operable when f xt is selected as count clock watchdog timer 1 operable stops operation watchdog timer 2 operable when f xt is selected as count clock csi00 to csi02 stops operation operable when sck0n input clock is selected as operation clock csia0, csia1 stops operation i 2 c0 note , i 2 c1 note stops operation uart0 operable when asck0 is selected as count clock serial interface uart1, uart2 stops operation key interrupt function operable a/d converter stops operation d/a converter stops operation real-time output stops operation port function retains status before sub-idle mode was set. external bus interface refer to chapter 5 bus control function . internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the sub-idle mode was set. note only products with i 2 c remark m = 0 or 1 n = 0 to 2 chapter 21 standby function user ? s manual u15862ej3v0ud 670 21.8 control registers (1) power save control register (psc) this is an 8-bit register that controls the standby function. the stp bit of this register is used to specify the stop mode. the psc register is a special register (refer to 3.4.7 special registers ). data can be written to this register only in a specific sequence so that its contents are not rewritten by mistake due to a program hang-up. this register can be read or written in 8-bit or 1-bit units. nmi2m psc 0 nmi0m intm 0 0 stp 0 intwdt2 request enabled intwdt2 request disabled nmi2m 0 1 controls non-maskable interrupt request (intwdt2) from watchdog timer 2 note 1 nmi request enabled nmi request disabled nmi0m 0 1 controls non-maskable interrupt request from nmi pin note 1 intxxx request enabled intxxx request disabled intm 0 1 controls all non-maskable interrupt requests (intxx note 2 ) note 1 normal mode standby mode note 3 stp 0 1 sets standby mode after reset: 00h r/w address: fffff1feh < > < > < > < > notes 1. setting these bits is valid only in the stop mode. 2. for details, refer to tables 19-1 to 19-3 interrupt sources . 3. set the stop or idle mode using the psm bit of the psmr register. caution if the nmi2m, nmi0m, and intm bits, and the stp bit are set to 1 at the same time, the setting of nmi2m, nmi0m, and intm bits becomes invalid. if there is an unmasked interrupt request being held pending when the stop mode is set, set the bit corresponding to the interrupt (nmi2m, nmi0m, or intm) to 1, and then set the stp bit to 1. user?s manual u15862ej3v0ud 671 chapter 22 reset function 22.1 overview the following reset functions are available. ? reset function by reset pin input ? reset function by overflow of watchdog timer 1 (wdtres1) ? reset function by overflow of watchdog timer 2 (wdtres2) if the reset pin goes high, the reset status is released, and the cpu starts executing the program. initialize the contents of each register in the program as necessary. the reset pin has a noise eliminator that operates by analog delay to prevent malfunction caused by noise. 22.2 configuration figure 22-1. reset block diagram reset count clock count clock analog delay circuit reset controller watchdog timer 1 watchdog timer 2 wdtres1 issued due to overflow reset signal to cpu reset signal to cg reset signal to other peripheral macros wdtres2 issued due to overflow chapter 22 reset function user ? s manual u15862ej3v0ud 672 22.3 operation the system is reset, initializing each hardware unit, when a low level is input to the reset pin or if watchdog timer 1 or watchdog timer 2 overflows (wdtres1 or wdtres2). while a low level is being input to the reset pin, the main clock oscillator stops. therefore, the overall power consumption of the system can be reduced. if the reset pin goes high or if wdtres1 or wdtres2 is received, the reset status is released. if the reset status is released by reset pin input or wdtres2, the oscillation stabilization time elapses (reset value of osts register: 2 15 /fxx) and then the cpu starts program execution. if the reset status is released by wdtres1, the oscillation stabilization time is not inserted because the main system clock oscillator does not stop. chapter 22 reset function user ? s manual u15862ej3v0ud 673 table 22-1. hardware status on reset pin input or occurrence of wdtres2 item during reset after reset main clock oscillator (f x ) oscillation stops (f x = 0 level). oscillation starts subclock oscillator (f xt ) oscillation can continue without effect from reset note . peripheral clock (f xx to f xx /1024), internal system clock (f clk ), cpu clock (f cpu ) operation stops operation starts. however, operation stops during oscillation stabilization time count. watchdog timer 1 clock (f xw ) operation stops operation starts internal ram undefined if power-on reset occurs or writing data to ram and reset conflict (data loss); otherwise, retains values immediately before reset input. i/o lines (ports) high impedance on-chip peripheral i/o registers initialized to specified status other on-chip peripheral functions operation stops operation can be started note the on-chip feedback resistor is ? connected ? by default (refer to 6.3 (1) processor clock control register (pcc) ). table 22-2. hardware status on occurrence of wdtres1 item during reset after reset main clock oscillator (f x ) oscillation continues note subclock oscillator (f xt ) oscillation can continue without effect from reset note . peripheral clock (f xx to f xx /1024), internal system clock (f clk ), cpu clock (f cpu ) operation stops operation starts watchdog timer 1 clock (f xw ) operation continues internal ram undefined if writing data to ram and reset conflict (data loss); otherwise, retains values immediately before reset input. i/o lines (ports) high impedance on-chip peripheral i/o registers initialized to specified status other on-chip peripheral functions operation stops operation can be started note the on-chip feedback resistor is "connected" by default (refer to 6.3 (1) processor clock control register (pcc) ). chapter 22 reset function user ? s manual u15862ej3v0ud 674 figure 22-2. hardware status on reset input figure 22-3. operation on power application oscillation stabilization time count initialized to f xx /8 operation overflow of timer for oscillation stabilization internal system reset signal analog delay reset f x v dd f clk oscillation stabilization time count initialized to f xx /8 operation overflow of timer for oscillation stabilization internal system reset signal analog delay (eliminated as noise) analog delay analog delay (eliminated as noise) reset f x f clk analog delay user?s manual u15862ej3v0ud 675 chapter 23 regulator 23.1 overview the v850es/kf1, v850es/kg1, and v850es/kj1 include a regulator to reduce the power consumption and noise. this regulator supplies a stepped-down v dd power supply voltage to the oscillator block and internal logic circuits (except the a/d converter, d/a converter, and output buffer). the regulator output voltage is set to 3.6 v (typ.). figure 23-1. regulator 23.2 operation the regulator stops operating in the following modes (but only when regc = v dd ). ? during reset input ? in stop mode ? in sub-idle mode be sure to connect a capacitor (10 f) to the regc pin to stabilize the regulator output. a diagram of the regulator pin connections is shown below. ev dd i/o buffer (normal port) 2.7 to 5.5 v bidirectional level shifter bv dd i/o buffer (external access port) 2.7 to 5.5 v regulator a/d converter 2.7 to 5.5 v d/a converter 2.7 to 5.5 v bv dd av ref0 av ref1 v pp v dd ev dd regc flash memory main/sub oscillator internal digital circuits 3.6 v (typ.) chapter 23 regulator user ? s manual u15862ej3v0ud 676 figure 23-2. regc pin connection (a) when regc = v dd reg input voltage = 2.7 to 5.5 v voltage supply to oscillator/internal logic = 2.7 to 5.5 v v dd regc (b) when connecting regc pin to v ss via a capacitor reg input voltage = 4.0 to 5.5 v voltage supply to oscillator/internal logic = 3.6 v v dd regc 10 f (recommended) user?s manual u15862ej3v0ud 677 chapter 24 rom correction function 24.1 overview the rom correction function is used to replace part of the program in the mask rom with the program of an external ram or the internal ram. by using this function, instruction bugs found in the mask rom can be corrected at up to four places. figure 24-1. block diagram of rom correction remark n = 0 to 3 instruction address bus block replacing bug with dbtrap instruction data bus rom dbtrap instruction generation block correction address register n (coradn) correction control register (corenn bit) comparator chapter 24 rom correction function user ? s manual u15862ej3v0ud 678 24.2 control registers 24.2.1 correction address registers 0 to 3 (corad0 to corad3) these registers are used to set the first address (correction address) of the instruction to be corrected in the rom. the program can be corrected at up to four places because four correction address register n (coradn) are provided (n = 0 to 3). the coradn register can only be read or written in 32-bit units. if the higher 16 bits of the coradn register are used as the coradnh register, and the lower 16 bits as the coradnl register, these registers can be read or written in 16-bit units. because the rom capacity differs depending on the product, set correction addresses in the following ranges. pd703208, 703208y, 7030212, 703212y (64 kb): 0000000h to 000fffeh pd703209, 703209y, 703213, 703213y, 703216, 703216y (96 kb): 0000000h to 0017ffeh pd703210, 703210y, 703214, 703214y, 703217, 703217y (128 kb): 0000000h to 001fffeh fix bits 0 and 18 to 31 to 0. correction address fixed to 0 0 coradn (n = 0-3) after reset: 00000000h r/w address: corad0: fffff840h corad2: fffff848h corad1: fffff844h corad3: fffff84ch 17 16 chapter 24 rom correction function user ? s manual u15862ej3v0ud 679 24.2.2 correction control register (corcn) this register disables or enables the correction operation of correction address register n (coradn) (n = 0 to 3). each channel can be enabled or disabled by this register. this register is set by using an 8-bit or 1-bit memory manipulation instruction. 0 disabled enabled corenn 0 1 enables/disables correction operation corcn 0 0 0 coren3 coren2 coren1 coren0 after reset: 00h r/w address: fffff880h remark n = 0 to 3 table 24-1. correspondence between corcn register bits and coradn registers corcn register bit corresponding coradn register coren3 corad3 coren2 corad2 coren1 corad1 coren0 corad0 24.3 rom correction operation and program flow <1> if the address to be corrected and the fetch address of the internal rom match, the fetch code is replaced by the dbtrap instruction. <2> when the dbtrap instruction is executed, execution branches to address 00000060h. <3> software processing after branching causes the result of rom correction to be judged (the fetch address and rom correction operation are confirmed) and execution to branch to the correction software. <4> after the correction software has been executed, the return address is set, and return processing is started by the dbret instruction. cautions 1. the software that performs <3> and <4> must be executed in the internal rom/ram. 2. develop the program so that the rom correction function is not used until data has been completely written to the corcn register that controls rom correction. 3. when setting an address to be corrected to the coradn register, clear the higher bits to 0 in accordance with the capacity of the internal rom. 4. the rom correction function cannot be used to correct the data of the internal rom. it can only be used to correct instruction codes. if rom correction is used to correct data, that data is replaced with the dbtrap instruction code. chapter 24 rom correction function user ? s manual u15862ej3v0ud 680 figure 24-2. rom correction operation and program flow reset & start fetch address = coradn coradn = dbpc-2? corenn = 1 dbtrap instruction executed? initialize microcontroller set coradn register change fetch code to dbtrap instruction jump to rom correction judgment address jump to address of replacement program execute fetch code jump to address 60h execute correction code error processing execute dbret instruction write return address to dbpc. write value of psw to dbpsw as necessary. set corcn register yes yes yes yes no no no no : processing by user program : rom correction judgment read data for setting rom correction from external memory remark n = 0 to 3 user?s manual u15862ej3v0ud 681 chapter 25 flash memory the following products are the on-chip flash memory versions of the v850es/kf1, v850es/kg1, and v850es/kj1. (1) v850es/kf1 pd70f3210, 70f3210y: products with 128 kb flash memory (2) v850es/kg1 pd70f3214, 70f3214y: products with 128 kb flash memory (3) v850es/kj1 pd70f3217, 70f3217y: products with 128 kb flash memory when an instruction is fetched from this flash memory, 4 bytes can be accessed with 1 clock, in the same manner as the mask rom versions. data can be written to the flash memory with the flash memory mounted on the target system (on-board). connect a dedicated flash programmer to the target system to write the flash memory. the following are the assumed environments and applications of flash memory. { changing software after soldering the v850es/kf1, v850es/kg1, or v850es/kj1 onto the target system { producing many variations of a product in small quantities by changing the software { adjusting data when mass production is started caution there are differences in noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing and application set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct sufficient evaluation for the commercial samples (not engineering samples) of the mask rom version. 25.1 features ? 4 byte/1 clock access (during instruction fetch access) ? erasing all areas at once or in area units ? communication with dedicated flash programmer via serial interface ? erase/write voltage: v pp = 10.3 v ? on-board programming chapter 25 flash memory user?s manual u15862ej3v0ud 682 25.2 writing with flash programmer data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) on-board programming the contents of the flash memory can be rewritten after the v850es/kf1, v850es/kg1, or v850es/kj1 has been mounted on the target system. the connectors that connect the dedicated flash programmer must be mounted on the target system. (2) off-board programming data can be written to the flash memory with a dedicated program adapter (fa series) before the v850es/kf1, v850es/kg1, or v850es/kj1 is mounted on the target system. remark the fa series is a product of naito densei machida mfg. co., ltd. table 25-1. wiring between pd70f3210 and 70f3210y (v850es/kf1), and pg-fp3 pin configuration of flash programmer (pg-fp3) with csi00-hs with csi00 with uart0 signal name i/o pin function pin name pin no. pin name pin no. pin name pin no. si/rxd input receive signal p41/so00 20 p41/so00 20 p30/txd0 22 so/txd output transmit signal p40/si00 19 p40/si00 19 p31/rxd0 23 sck output transfer clock p42/sck00 21 p42/sck00 21 not needed not needed x1 12 x1 12 x1 12 clk output clock to v850es/kf1 x2 note 13 x2 note 13 x2 note 13 /reset output reset signal reset 14 reset 14 reset 14 vpp output write voltage v pp 8v pp 8v pp 8 hs input handshake signal for csi0 + hs communication pcs1/cs1 48 not needed not needed not needed not needed v dd 9v dd 9v dd 9 ev dd 31 ev dd 31 ev dd 31 vdd i/o v dd voltage generation/voltage monitor av ref0 1av ref0 1av ref0 1 v ss 11 v ss 11 v ss 11 av ss 2av ss 2av ss 2 gnd ? ground ev ss 30 ev ss 30 ev ss 30 note when using the clock out of the flash programmer, connect clk of the programmer to x1, and connect its inverse signal to x2. cautions 1. be sure to connect the regc pin in either of the following ways. ? ? ? ? connect to gnd via a 10 f capacitor ? ? ? ? directly connect to v dd 2. when connecting the regc pin to gnd via a 10 f capacitor, the clock cannot be supplied from the clk pin of the flash programmer. supply the clock by creating an oscillator on the board. chapter 25 flash memory user?s manual u15862ej3v0ud 683 figure 25-1. wiring example of v850es/kf1 flash writing adapter (fa-80gc-8bt, fa-80gk-9eu) pd70f3210, pd70f3210y vdd gnd gnd vdd gnd vdd v dd g nd 31 connect to vdd. connect to gnd. 1 9 8 2 11 12 13 14 48 19 20 30 21 so sck si x1 /reset v pp reserve/hs x2 10 note note be sure to connect the regc pin in either of the following ways. ? connect to gnd via a 10 f capacitor. ? directly connect to v dd . when connecting the regc pin to gnd via a 10 f capacitor, the clock cannot be supplied from the clk pin of the flash programmer. supply the clock by preparing an oscillator on the board. remarks 1. handle the pins not described above in accordance with the specified handling of unused pins (refer to 2.4 pin i/o circuits and recommended connection of unused pins). when connecting to v dd via a resistor, use of a resistor of 1 k ? to 10 k ? is recommended. 2. this adapter is for 80-pin plastic qfp and 80-pin plastic tqfp (fine pitch) packages. 3. this diagram shows the wiring when using a handshake-supporting csi. chapter 25 flash memory user ? s manual u15862ej3v0ud 684 table 25-2. wiring between pd70f3214 and 70f3214y (v850es/kg1), and pg-fp3 pin configuration of flash programmer (pg-fp3) with csi00-hs with csi00 with uart0 signal name i/o pin function pin name pin no. pin name pin no. pin name pin no. si/r x d input receive signal p41/so00 23 p41/so00 23 p30/txd0 25 so/t x d output transmit signal p40/si00 22 p40/si00 22 p31/rxd0 26 sck output transfer clock p42/sck00 24 p42/sck00 24 not needed not needed x1 12 x1 12 x1 12 clk output clock to v850es/kg1 x2 note 13 x2 note 13 x2 note 13 /reset output reset signal reset 14 reset 14 reset 14 vpp output write voltage v pp 8v pp 8v pp 8 hs input handshake signal for csi0 + hs communication pcs1/cs1 60 not needed not needed not needed not needed v dd 9v dd 9v dd 9 bv dd 70 bv dd 70 bv dd 70 ev dd 34 ev dd 34 ev dd 34 av ref0 1av ref0 1av ref0 1 vdd i/o v dd voltage generation/voltage monitor av ref1 5av ref1 5av ref1 5 v ss 11 v ss 11 v ss 11 av ss 2av ss 2av ss 2 bv ss 69 bv ss 69 bv ss 69 gnd ? ground ev ss 33 ev ss 33 ev ss 33 note when using the clock out of the flash programmer, connect clk of the programmer to x1, and connect its inverse signal to x2. cautions 1. be sure to connect the regc pin in either of the following ways. ? ? ? ? connect to gnd via a 10 f capacitor ? ? ? ? directly connect to v dd 2. when connecting the regc pin to gnd via a 10 f capacitor, the clock cannot be supplied from the clk pin of the flash programmer. supply the clock by creating an oscillator on the board. chapter 25 flash memory user ? s manual u15862ej3v0ud 685 figure 25-2. wiring example of v850es/kg1 flash writing adapter (fa-100gc-8eu) pd70f3214, pd70f3214y vdd gnd g n d v d d gnd vdd vd d g n d 70 69 60 connect to vdd. connect to gnd. 34 1 5 910 8 24 23 22 2 11 12 13 14 33 so sck si x1 /reset v pp reserve/hs x2 note note be sure to connect the regc pin in either of the following ways. ? connect to gnd via a 10 f capacitor. ? directly connect to v dd . when connecting the regc pin to gnd via a 10 f capacitor, the clock cannot be supplied from the clk pin of the flash programmer. supply the clock by preparing an oscillator on the board. remarks 1. handle the pins not described above in accordance with the specified handling of unused pins (refer to 2.4 pin i/o circuits and recommended connection of unused pins). when connecting to v dd via a resistor, use of a resistor of 1 k ? to 10 k ? is recommended. 2. this adapter is for a 100-pin plastic lqfp (fine pitch) package. 3. this diagram shows the wiring when using a handshake-supporting csi. chapter 25 flash memory user ? s manual u15862ej3v0ud 686 table 25-3. wiring between pd70f3217 and 70f3217y (v850es/kj1), and pg-fp3 pin configuration of flash programmer (pg-fp3) with cis00-hs with csi00 with uart0 signal name i/o pin function pin name pin no. pin name pin no. pin name pin no. si/r x d input receive signal p41/so00 23 p41/so00 23 p30/txd0 25 so/t x d output transmit signal p40/si00 22 p40/si00 22 p31/rxd0 26 sck output transfer clock p42/sck00 24 p42/sck00 24 not needed not needed x1 12 x1 12 x1 12 clk output clock to v850es/kj1 x2 note 13 x2 note 13 x2 note 13 /reset output reset signal reset 14 reset 14 reset 14 vpp output write voltage v pp 8v pp 8v pp 8 hs input handshake signal for csi0 + hs communication pcs1/cs1 82 not needed not needed not needed not needed v dd 9v dd 9v dd 9 bv dd 104 bv dd 70 bv dd 70 ev dd 34 ev dd 34 ev dd 34 av ref0 1av ref0 1av ref0 1 vdd i/o v dd voltage generation/voltage monitor av ref1 5av ref1 5av ref1 5 v ss 11 v ss 11 v ss 11 av ss 2av ss 2av ss 2 bv ss 103 bv ss 69 bv ss 69 gnd ? ground ev ss 33 ev ss 33 ev ss 33 note when using the clock out of the flash programmer, connect clk of the programmer to x1, and connect its inverse signal to x2. cautions 1. be sure to connect the regc pin in either of the following ways. ? ? ? ? connect to gnd via a 10 f capacitor ? ? ? ? directly connect to v dd 2. when connecting the regc pin to gnd via a 10 f capacitor, the clock cannot be supplied from the clk pin of the flash programmer. supply the clock by creating an oscillator on the board. chapter 25 flash memory user ? s manual u15862ej3v0ud 687 figure 25-3. wiring example of v850es/kj1 flash writing adapter (fa-144gj-uen) pd70f3217, pd70f3217y so sck si x1 /reset v pp reserve/hs x2 vdd gnd gnd vdd gnd vdd vd d g n d connect to vdd. connect to gnd. 23 24 22 11 12 13 14 33 2 104 103 82 34 1 5 89 10 note note be sure to connect the regc pin in either of the following ways. ? connect to gnd via a 10 f capacitor. ? directly connect to v dd . when connecting the regc pin to gnd via a 10 f capacitor, the clock cannot be supplied from the clk pin of the flash programmer. supply the clock by preparing an oscillator on the board. remarks 1. handle the pins not described above in accordance with the specified handling of unused pins (refer to 2.4 pin i/o circuits and recommended connection of unused pins). when connecting to v dd via a resistor, use of a resistor of 1 k ? to 10 k ? is recommended. 2. this adapter is for a 144-pin plastic lqfp (fine pitch) package. 3. this diagram shows the wiring when using a handshake-supporting csi. chapter 25 flash memory user ? s manual u15862ej3v0ud 688 25.3 programming environment the environment required for writing a program to the flash memory of the v850es/kf1, v850es/kg1, and v850es/kj1 is illustrated below. figure 25-4. environment for writing program to flash memory host machine rs-232-c dedicated flash programmer v850es/kf1, v850es/kg1, v850es/kj1 v pp v dd v ss reset uart0/csi00 pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve a host machine that controls the dedicated flash programmer is necessary. to interface between the flash programmer and the v850es/kf1, v850es/kg1, and v850es/kj1, uart0 or csi00 is used for manipulation such as writing and erasing. to write the flash memory off-board, a dedicated program adapter (fa series) is necessary. 25.4 communication mode communication between the dedicated flash programmer and the v850es/kf1, v850es/kg1, and v850es/kj1 is established by serial communication via uart0 or csi00 of the v850es/kf1, v850es/kg1, and v850es/kj1. (1) uart0 transfer rate: 4800 to 76800 bps (lsb first) figure 25-5. communication with dedicated flash programmer (uart0) dedicated flash programmer v850es/kf1, v850es/kg1, v850es/kj1 v pp v dd v ss reset txd0 x1 v pp v dd gnd reset rxd rxd0 txd clk x2 clk pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xx x yy y x x x x x x x x x x x x x x x xx xx yyyy statve chapter 25 flash memory user ? s manual u15862ej3v0ud 689 (2) csi00 transfer rate: 200 khz to 1 mhz (msb first) figure 25-6. communication with dedicated flash programmer (csi00) dedicated flash programmer v850es/kf1, v850es/kg1, v850es/kj1 v pp v dd v ss reset so00 si00 sck00 v pp v dd gnd reset si so x1 clk x2 clk sck pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve (3) csi communication mode supporting handshake transfer rate: 200 khz to 1 mhz (msb first) figure 25-7. communication with flash programmer (csi00+hs) dedicated flash programmer v850es/kf1, v850es/kg1, v850es/kj1 v pp v dd v ss reset so00 si00 sck00 pcs1 v pp v dd gnd reset si so sck x1 clk x2 clk hs (v pp 2) pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve chapter 25 flash memory user ? s manual u15862ej3v0ud 690 if the pg-fp3 is used as the flash programmer, the pg-pf3 generates the following signal for the v850es/kf1, v850es/kg1, and v850es/kj1. for details, refer to the pg-fp3 user's manual (u13502e) . table 25-4. signals generated by dedicated flash programmer (pg-fp3) pg-fp3 v850es/kf1, v850es/kg1, v850es/kj1 connection signal name i/o pin function pin name note 1 csi00 uart0 v pp output write voltage v pp v dd i/o v dd voltage generation/voltage monitor v dd gnd ? ground v ss clk output clock output to v850es/kf1, v850es/kg1, or v850es/kj1 x1, x2 note 2 { { reset output reset signal reset si/rxd input receive signal so00/txd0 so/txd output transmit signal si00/rxd0 sck output transfer clock sck00 hs (v pp 2) input handshake signal of csi00+hs communication pcs1 notes 1. when the flash memory programming mode is set, the pins not used for flash memory programming are in the same status as immediately after reset, i.e., port mode (input) and high impedance. if the external device connected to each port does not recognize the state immediately after reset, connect the pin to v dd or v ss via a resistor. 2. for off-board writing only: connect the clock output of the flash programmer to x1 and its inverse signal to x2. remark : be sure to connect the pin. { : the pin does not have to be connected if the signal is generated on the target board. : the pin does not have to be connected. : in handshake mode chapter 25 flash memory user ? s manual u15862ej3v0ud 691 25.5 pin processing to write the flash memory on-board, connectors that connect the flash programmer must be provided on the target system. first provide a function that selects the normal operation mode or flash memory programming mode on the board. when the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset. therefore, because all the ports go into an output high-impedance state, if the external device does not recognize the output high-impedance state, the pins must be processed as described below. 25.5.1 v pp pin in the normal operation mode, 0 v is input to the v pp pin. in the flash memory programming mode, a write voltage of 10.3 v is supplied to the v pp pin. an example of connection of the v pp pin is illustrated below. figure 25-8. example of connection of v pp pin v850es/kf1, v850es/kg1, v850es/kj1 v pp flash programmer connection pin pull-down resistor (r vpp ) chapter 25 flash memory user ? s manual u15862ej3v0ud 692 25.5.2 serial interface pins the pins used by each serial interface are listed below. table 25-5. pins used by each serial interface serial interface pins used csi00 so00, si00, sck00 csi00 + hs so00, si00, sck00, pcs1 uart0 txd0, rxd0 to connect the dedicated flash programmer to the pins of a serial interface that is connected to another device on the board, care must be exercised so that signals do not collide or that the other device does not malfunction. (1) signal collision if the flash programmer (output) is connected to a pin (input) of a serial interface connected to another device (output), signal collision takes place. to avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state. figure 25-9. signal collision (input pin of serial interface) input pin signal collision flash programmer connection pin other device output pin in the flash memory programming mode, the signal output by the device collides with the signal sent from the flash programmer. therefore, isolate the signal of the other device. v850es/kf1, v850es/kg1, v850es/kj1 chapter 25 flash memory user ? s manual u15862ej3v0ud 693 (2) malfunction of other device if the dedicated flash programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal may be output to the other device, causing the device to malfunction. to avoid this malfunction, either isolate the connection with the other device, or ignore the input signal to the other device. figure 25-10. malfunction of other device pin flash programmer connection pin other device input pin if the signal output by the v850es/kf1, v850es/kg1, and v850es/kj1 in the flash memory programming mode affects the other device, isolate the signal of the other device. pin flash programmer connection pin other device input pin if the signal output by the flash programmer in the flash memory programming mode affects the other device, isolate the signal of the other device. v850es/kf1, v850es/kg1, v850es/kj1 v850es/kf1, v850es/kg1, v850es/kj1 chapter 25 flash memory user ? s manual u15862ej3v0ud 694 25.5.3 reset pin if the reset signal of the flash programmer is connected to the reset pin that is connected to the reset signal generator on the board, signal collision takes place. to prevent this collision, isolate the connection with the reset signal generator. if the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed. do not input any signal other than the reset signal of the flash programmer. figure 25-11. signal collision (reset pin) reset flash programmer connection signal reset signal generator signal collision output pin in the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the flash programmer. therefore, isolate the signal of the reset signal generator. v850es/kf1, v850es/kg1, v850es/kj1 25.5.4 port pins when the flash memory programming mode is set, all the port pins, except those used for communication with the flash programmer, go into an output high-impedance state. if this causes a problem in the external device connected to a port due to prohibition of the output high-impedance state (etc.), connect the port to v dd or v ss via a resistor. 25.5.5 other signal pins connect the x1, x2, xt1, xt2, and regc pins in the same status as in the normal operation mode. to input the operating clock from the programmer, however, connect the clock out of the programmer to x1, and its inverse signal to x2. 25.5.6 power supply supply power as follows. v dd = ev dd supply the same power as in the normal operation mode to the other power supply pins (av ref0 , av ref1 , av ss , bv dd , and bv ss ). caution vdd of the flash programmer has a power monitor function. be sure to connect v dd and v ss to vdd and gnd of the flash programmer. chapter 25 flash memory user ? s manual u15862ej3v0ud 695 25.6 programming method 25.6.1 controlling flash memory the following figure illustrates the procedure to manipulate the flash memory. figure 25-12. flash memory manipulation procedure start selecting communication mode manipulate flash memory end? yes reset pulse supply no end flash memory programming mode is set chapter 25 flash memory user ? s manual u15862ej3v0ud 696 25.6.2 flash memory programming mode to rewrite the contents of the flash memory by using the dedicated flash programmer, set the v850es/kf1, v850es/kg1, and v850es/kj1 in the flash memory programming mode. to set the mode, set the v pp pin and clear the reset signal. change the mode by using a jumper when writing the flash memory on-board. figure 25-13. flash memory programming mode 1 10.3 v 0 v reset v pp v dd flash memory programming mode 2n v pp operation mode 0 v normal operation mode 10.3 v flash memory programming mode 25.6.3 selecting communication mode in the v850es/kf1, v850es/kg1, and v850es/kj1 a communication mode is selected by inputting pulses (up to 16 pulses) to the v pp pin after the flash memory programming mode is entered. these v pp pulses are generated by the flash programmer. the following table shows the relationship between the number of pulses and communication modes. table 25-6. communication modes v pp pulse communication mode remark 0 csi00 v850es/kf1, v850es/kg1, and v850es/kj1 operate as slave with msb first. 3 csi00 + hs v850es/kf1, v850es/kg1, and v850es/kj1 operate as slave with msb first. 8 uart0 communication rate: 9600 bps (after reset), lsb first other rfu setting prohibited caution when uart0 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after the v pp pulse has been received. chapter 25 flash memory user ? s manual u15862ej3v0ud 697 25.6.4 communication commands the v850es/kf1, v850es/kg1, and v850es/kj1 communicate with the flash programmer by using commands. the commands sent from the flash programmer to the v850es/kf1, v850es/kg1, and v850es/kj1 are called commands, and the commands sent from the v850es/kf1, v850es/kg1, and v850es/kj1 to the flash programmer are called response commands. figure 25-14. communication commands flash programmer command response command v850es/kf1, v850es/kg1, v850es/kj1 pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve the flash memory control commands of the v850es/kf1, v850es/kg1, and v850es/kj1 are listed in the table below. all these commands are issued from the programmer and the v850es/kf1, v850es/kg1, and v850es/kj1 perform processing corresponding to the respective commands. table 25-7. flash memory control commands classification command name function verify batch verify command compares the contents of the entire memory with the input data. erase batch erase command erases the contents of the entire memory. blank check batch blank check command checks the erasure status of the entire memory. high-speed write command writes data by specifying the write address and number of bytes to be written, and executes a verify check. data write successive write command writes data from the address following that of the high-speed write command executed immediately before, and executes a verify check. status read command obtains the operation status oscillation frequency setting command sets the oscillation frequency erase time setting command sets the erase time for batch erase write time setting command sets the write time for writing data baud rate setting command sets the baud rate when uart is used silicon signature command reads the silicon signature information system setting, control reset command escapes from each status the v850es/kf1, v850es/kg1, and v850es/kj1 return a response command for the command issued by the dedicated flash programmer. the response commands sent from the v850es/kf1, v850es/kg1, and v850es/kj1 are listed below. chapter 25 flash memory user ? s manual u15862ej3v0ud 698 table 25-8. response commands command name function ack (acknowledge) acknowledges command/data. nak (not acknowledge) acknowledges illegal command/data. 25.6.5 resources used the resources used in the flash memory programming mode are the areas other than addresses 03ffe800h to 03ffefffh (2 kb) of the internal ram, and all the registers. the other areas of the internal ram retain their data unless the power is turned off. the registers that are initialized by reset are initialized to the default value. user?s manual u15862ej3v0ud 699 chapter 26 electrical specifications absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd v dd = ev dd = av ref0 ? 0.3 to + 6.5 v v pp flash memory version, note 1 ? 0.3 to + 10.5 v bv dd bv dd v dd ? 0.3 to v dd + 0.3 note 2 v ev dd v dd = ev dd = av ref0 ? 0.3 to + 6.5 v av ref0 v dd = ev dd = av ref0 ? 0.3 to + 6.5 v av ref1 av ref1 v dd (d/a output mode) av ref1 = av ref0 = v dd (port mode) ? 0.3 to v dd + 0.3 note 2 v v ss v ss = ev ss = bv ss = av ss ? 0.3 to + 0.3 v av ss v ss = ev ss = bv ss = av ss ? 0.3 to + 0.3 v bv ss v ss = ev ss = bv ss = av ss ? 0.3 to + 0.3 v supply voltage ev ss v ss = ev ss = bv ss = av ss ? 0.3 to + 0.3 v v i1 p00 to p06, p30 to p35, p38, p39, p40 to p42, p50 to p55, p60 to p613, p80, p81, p90 to p915 ? 0.3 to ev dd + 0.3 note 2 v v i2 pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdl0 to pdl15, pdh0 to pdh7 ? 0.3 to bv dd + 0.3 note 2 v v i3 p10, p11 ? 0.3 to av ref1 + 0.3 note 2 v v i4 p36, p37, p614, p615 ? 0.3 to + 13 note 3 v v i5 x1, x2, xt1, xt2 ? 0.3 to v dd + 1.0 note 2 v input voltage v i6 v pp ? 0.3 to + 10.5 v analog input voltage v ian p70 to p715 ? 0.3 to av ref0 + 0.3 note 2 v notes 1. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? ? ? ? when supply voltage rises v pp must exceed v dd 15 s or more after v dd has reached the lower-limit value (2.7 v) of the operating voltage range (see a in the figure below). ? ? ? ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (2.7 v) of the operating voltage range of v dd (see b in the figure below). 2.7 v v dd 0 v 0 v v pp 2.7 v a b 2. be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. 3. when pull-up is not specified by a mask option. the same as v i1 when pull-up is specified. chapter 26 electrical specifications user ? s manual u15862ej3v0ud 700 absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit p00 to p06, p10, p11, p30 to p35, p40 to p42, p50 to p55, p60 to p613, p80, p81, p90 to p915, pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdl0 to pdl15, pdh0 to pdh7 20 ma p36 to p39, p614, p615 per pin 30 ma p00 to p06, p30 to p39, p40 to p42 35 p50 to p55, p60 to p615, p80, p81, p90 to p915 total of all pins: 70 ma 35 ma pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7 35 ma output current, low i ol note pdl0 to pdl15, pdh0 to pdh7 total of all pins: 70 ma 35 ma per pin ? 10 p00 to p06, p30 to p35, p40 to p42 ? 30 ma p50 to p55, p60 to p613, p80, p81, p90 to p915 total of all pins: ? 60 ma ? 30 ma pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7 total of all pins: ? 60 ma ? 30 ma pdl0 to pdl15, pdh0 to pdh7 total of all pins: ? 70 ma ? 30 output current, high i oh note p10, p11 per pin ? 10 ma operating ambient temperature t a ? 40 to + 85 c mask rom version ? 65 to + 150 c storage temperature t stg flash memory version ? 40 to + 125 c note in the v850es/kf1, the specifications of the total of all pins for i ol and i oh are as follows since bv dd system pins do not exist. p00 to p06, p30 to p35, p38, p39, p40 to p42 35 ma i ol total of pins: 70 ma p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0 to pcm3, pcs0, pcs1, pct0, pct1, pct4, pct6, pdl0 to pdl15 35 ma p00 to p06, p30 to p35, p40 to p42 ? 30 ma i oh total of pins: ? 60 ma p50 to p55, p90, p91, p96 to p99, p913 to p915, pcm0 to pcm3, pcs0, pcs1, pct0, pct1, pct4, pct6, pdl0 to pdl15 ? 30 ma chapter 26 electrical specifications user ? s manual u15862ej3v0ud 701 cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-collector pins, however, can be directly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. 3. the following pins are not provided in the v850es/kf1. p10, p11, p36, p37, p60 to p615, p78 to p715, p80, p81, p92 to p95, p910 to p912, pcd0 to pcd3, pcm4, pcm5, pcs2 to pcs7, pct2, pct3, pct5, pct7, pdh0 to pdh7, av ref1 , bv dd , bv ss in the v850es/kf1, the specification of v i2 is the same as that of the v i1 since the bv dd pin does not exist. the following pins are not provided in the v850es/kg1. p60 to p615, p78 to p715, p80, p81, pcd0 to pcd3, pcm4, pcm5, pcs2 to pcs7, pct2, pct3, pct5, pct7, pdh6, pdh7 capacitance (t a = 25 c, v dd = ev dd = av ref0 = bv dd = av ref1 = v ss = ev ss = bv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i p70 to p715 15 pf note 15 pf i/o capacitance c io f x = 1 mhz unmeasured pins returned to 0 v p36 to p39, p614, p615 20 pf note p00 to p06, p10, p11, p30 to p35, p40 to p42, p50 to p55, p60 to p613, p80, p81, p90 to p915, pcd0 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdl0 to pdl15, pdh0 to pdh7 caution the following pins are not provided in the v850es/kf1. p10, p11, p36, p37, p60 to p615, p78 to p715, p80, p81, p92 to p95, p910 to p912, pcd0 to pcd3, pcm4, pcm5, pcs2 to pcs7, pct2, pct3, pct5, pct7, pdh0 to pdh7, av ref1 , bv dd , bv ss the following pins are not provided in the v850es/kg1. p60 to p615, p78 to p715, p80, p81, pcd0 to pcd3, pcm4, pcm5, pcs2 to pcs7, pct2, pct3, pct5, pct7, pdh6, pdh7 chapter 26 electrical specifications user ? s manual u15862ej3v0ud 702 operating conditions (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit regc = v dd = 5 v 10% in pll mode (osc = 2 to 5 mhz) 820mhz regc = capacity, v dd = 4.0 to 5.5 v in pll mode (osc = 2 to 4 mhz) 816mhz regc = v dd = 2.7 to 5.5 v 2 10 mhz internal system clock frequency f clk regc = v dd = 2.7 to 5.5 v, operating with subclock 32.768 khz internal system clock frequency vs. supply voltage pll characteristics (t a = ? ? ? ? 40 to + + + + 85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit input frequency f x 25mhz output frequency f xx 820mhz lock time t pll after v dd reaches min.:2.7 v 200 s 1.0 0.1 when regc = capacity 2.0 10.0 100 3.0 4.0 supply voltage v dd [v] internal system clock frequency f clk [mhz] 5.0 6.0 20.0 16.0 chapter 26 electrical specifications user ? s manual u15862ej3v0ud 703 main clock oscillator characteristics (t a = ? ? ? ? 40 to + + + + 85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 210mhz after reset is released 2 15 /f x s ceramic resonator oscillation stabilization time note 2 after stop mode is released note 3 s oscillation frequency (f x ) note 1 210mhz after reset is released 2 15 /f x s crystal resonator oscillation stabilization time note 2 after stop mode is released note 3 s external clock x1, x2 input frequency (f x ) regc = v dd duty = 50% 5% 210mhz notes 1. indicates only oscillator characteristics. 2. time required to stabilize the crystal resonator after reset or stop mode is released. 3. the value differs depending on the osts register settings. cautions 1. when using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main clock is stopped and the device is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. x2 x1 external clock x2 x1 x2 x1 chapter 26 electrical specifications user ? s manual u15862ej3v0ud 704 (i) murata manufacturing co., ltd.: ceramic resonator (t a = ? ? ? ? 40 to +85 c) recommended circuit constant recommended voltage range manufacturer product name type oscillation frequency f xx (mhz) c1 (pf) c2 (pf) rd (k ? ) min. (v) max. (v) cstcc2m00g56-r0 smd 2.000 47 47 0 2.7 5.5 cstcc3m00g56-r0 smd 3.000 47 47 0 2.7 5.5 cstcr4m00g55-r0 smd 39 39 0 2.7 5.5 cstls4m00g56-b0 4.000 47 47 0 2.7 5.5 cstcr5m00g55-r0 smd 39 39 0 2.7 5.5 cstls5m00g56-b0 5.000 47 47 0 2.7 5.5 cstce10m0g52-r0 smd 10 10 0 2.7 5.5 cstls10m0g53-b0 10.000 15 15 0 2.7 5.5 cstcc2m00g56a-r0 smd 2.000 47 47 0 2.7 5.5 cstcc3m00g56a-r0 smd 3.000 47 47 0 2.7 5.5 cstcr4m00g55a-r0 smd 4.000 39 39 0 2.7 5.5 cstcr5m00g55a-r0 smd 5.000 39 39 0 2.7 5.5 murata mfg. co., ltd. cstce10m0g52a-r0 smd 10.000 10 10 0 2.7 5.5 caution this oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and oscillation frequency indicate only oscillator characteristics. use the v850es/kf1, v850es/kg1, and v850es/kj1 so that the internal operating conditions are within the specifications of the dc and ac characteristics. chapter 26 electrical specifications user ? s manual u15862ej3v0ud 705 subclock oscillator characteristics (t a = ? ? ? ? 40 to + + + + 85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz crystal resonator oscillation stabilization time note 2 10 s external clock xt1 input frequency (f xt ) note 1 duty = 50% 5% regc = v dd 32 35 khz notes 1. indicates only oscillator characteristics. 2. time required from when v dd reaches oscillation voltage range (min.: 2.7 v) to when the crystal resonator stabilizes. cautions 1. when using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subclock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main clock oscillator. particular care is therefore required with the wiring method when the subclock is used. xt2 xt1 external clock xt2 xt1 chapter 26 electrical specifications user ? s manual u15862ej3v0ud 706 dc characteristics (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v) (1/5) parameter symbol conditions max. unit per pin for p00 to p06, p30 to p35, p40 to p42, p50 to p55, p60 to p613, p80, p81, p90 to p915 ? 5.0 ma ev dd = 4.0 to 5.5 v ? 30 ma total of p00 to p06, p30 to p35, p40 to p42 ev dd = 2.7 to 5.5 v ? 15 ma ev dd = 4.0 to 5.5 v ? 30 ma i oh1 total of p50 to p55, p60 to p613, p80, p81, p90 to p915 ev dd = 2.7 to 5.5 v ? 15 ma per pin for pcd0 to pcd3, pcm0 to pcm3, pcs0 to pcs7, pct0 to pct7, pdh0 to pdh7, pdl0 to pdl15 ? 5.0 ma ev dd = 4.0 to 5.5 v ? 30 ma total of pcd0 to pcd3, pcm0 to pcm3, pcs0 to pcs7, pct0 to pct7 ev dd = 2.7 to 5.5 v ? 15 ma ev dd = 4.0 to 5.5 v ? 30 ma output current, high i oh2 total of pdl0 to pdl15, pdh0 to pdh7 ev dd = 2.7 to 5.5 v ? 15 ma per pin for p00 to p06, p30 to p35, p40 to p42, p50 to p55, p60 to p613, p80, p81, p90 to p915 10 ma ev dd = 4.0 to 5.5 v 15 ma per pin for p36 to p39 ev dd = 2.7 to 5.5 v 8 ma ev dd = 4.0 to 5.5 v 10 ma per pin for p614, p615 ev dd = 2.7 to 5.5 v 5 ma total of p00 to p06, p30 to p37, p40 to p42 30 ma i ol1 total of p38, p39, p50 to p55, p60 to p615, p80, p81, p90 to p915 30 ma per pin for pcd0 to pcd3, pcm0 to pcm3, pcs0 to pcs7, pct0 to pct7, pdh0 to pdh7, pdl0 to pdl15 10 ma total of pcd0 to pcd3, pcm0 to pcm3, pcs0 to pcs7, pct0 to pct7 30 ma output current, low i ol2 total of pdl0 to pdl15, pdh0 to pdh7 30 ma caution the following pins are not provided in the v850es/kf1. p10, p11, p36, p37, p60 to p615, p78 to p715, p80, p81, p92 to p95, p910 to p912, pcd0 to pcd3, pcm4, pcm5, pcs2 to pcs7, pct2, pct3, pct5, pct7, pdh0 to pdh7, av ref1 , bv dd , bv ss the following pins are not provided in the v850es/kg1. p60 to p615, p78 to p715, p80, p81, pcd0 to pcd3, pcm4, pcm5, pcs2 to pcs7, pct2, pct3, pct5, pct7, pdh6, pdh7 chapter 26 electrical specifications user ? s manual u15862ej3v0ud 707 dc characteristics (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v) (2/5) parameter symbol conditions min. typ. max. unit v ih1 note 1 0.7ev dd ev dd v v ih2 note 2 0.8ev dd ev dd v v ih3 note 3 0.7bv dd bv dd v v ih4 p70 to p715 0.7av ref0 av ref0 v v ih5 p10, p11 note 4 0.7av ref1 av ref1 v v ih6 p36, p37, p614, p615 0.7ev dd 12 note 5 v input voltage, high v ih7 x1, x2, xt1, xt2 ev dd ? 0.5 ev dd v v il1 note 1 ev ss 0.3ev dd v v il2 note 2 ev ss 0.2ev dd v v il3 note 3 bv ss 0.3bv dd v v il4 p70 to p715 av ss 0.3av ref0 v v il5 p10, p11 note 4 av ss 0.3av ref1 v v il6 p36, p37, p614, p615 ev ss 0.3ev dd v input voltage, low v il7 x1, x2, xt1, xt2 ev ss 0.4 v notes 1. p00, p01, p30, p41, p60 to p65, p67, p611, p98, p911 and their alternate-function pins. 2. reset, p02 to p06, p31 to p35, p38, p39, p40, p42, p50 to p55, p66, p68 to p610, p612, p613, p80, p81, p90 to p97, p99, p910, p912 to p915 and their alternate-function pins. 3. pcd0 to pcd3, pcm0 to pcm3, pcs0 to pcs7, pct0 to pct7, pdl0 to pdl15, pdh0 to pdh7 and their alternate-function pins. 4. when used as port pins, set av ref1 = av ref0 = v dd. 5. when pull-up is not specified by a mask option. ev dd when pull-up is specified. caution the following pins are not provided in the v850es/kf1. p10, p11, p36, p37, p60 to p615, p78 to p715, p80, p81, p92 to p95, p910 to p912, pcd0 to pcd3, pcm4, pcm5, pcs2 to pcs7, pct2, pct3, pct5, pct7, pdh0 to pdh7, av ref1 , bv dd , bv ss the following pins are not provided in the v850es/kg1. p60 to p615, p78 to p715, p80, p81, pcd0 to pcd3, pcm4, pcm5, pcs2 to pcs7, pct2, pct3, pct5, pct7, pdh6, pdh7 chapter 26 electrical specifications user ? s manual u15862ej3v0ud 708 dc characteristics (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v) (3/5) parameter symbol conditions min. typ. max. unit note 1 i oh = ? 2.0 ma, ev dd = 4.0 to 5.5 v ev dd ? 1.0 ev dd v v oh1 note 2 i oh = ? 0.1 ma, ev dd = 2.7 to 5.5 v ev dd ? 0.5 ev dd v note 3 i oh = ? 2.0 ma, ev dd = 4.0 to 5.5 v bv dd ? 1.0 bv dd v v oh2 note 4 i oh = ? 0.1 ma, ev dd = 2.7 to 5.5 v bv dd ? 0.5 bv dd v i oh = ? 0.2 ma a ref1 ? 1.0 av ref1 v output voltage, high v oh3 p10, p11 note 5 i oh = ? 0.1 ma a ref1 ? 0.5 av ref1 v v ol1 note 6 i ol = 2.0 ma note 7 00.8v v ol2 note 8 i ol = 2.0 ma note 7 00.8v v ol3 p10, p11 note 5 i ol = 2 ma 0 0.8 v i ol = 15 ma, ev dd = 4.0 to 5.5 v 02.0v i ol = 8 ma, ev dd = 3.0 to 5.5 v 01.0v v ol4 p36 to p39 i ol = 5 ma, ev dd = 2.7 to 5.5 v 01.0v i ol = 10 ma, ev dd = 4.0 to 5.5 v 02.0v output voltage, low v ol5 p614, p615 i ol = 5 ma, ev dd = 2.7 to 5.5 v 01.0v notes 1. total of p00 to p06, p30 to p35, p40 to p42 and their alternate-function pins: i oh = ? 30 ma, total of p50 to p55, p60 to p613, p80, p81, p90 to p915 and their alternate-function pins: i oh = ? 30 ma. 2. total of p00 to p06, p30 to p35, p40 to p42 and their alternate-function pins: i oh = ? 15 ma, total of p50 to p55, p60 to p613, p80, p81, p90 to p915 and their alternate-function pins: i oh = ? 15 ma. 3. total of pcd0 to pcd3, pcm0 to pcm3, pcs0 to pcs7, pct0 to pct7: i oh = ? 30 ma, total of pdh0 to pdh7, pdl0 to pdl15 and their alternate-function pins: i oh = ? 30 ma. 4. total of pcd0 to pcd3, pcm0 to pcm3, pcs0 to pcs7, pct0 to pct7: i oh = ? 15 ma, total of pdh0 to pdh7, pdl0 to pdl15 and their alternate-function pins: i oh = ? 15 ma. 5. when used as port pins, set av ref1 = av ref0 = v dd . 6. total of p00 to p06, p30 to p37, p40 to p42 and their alternate-function pins: i ol = 30 ma, total of p38 to p39, p50 to p55, p60 to p615, p80, p81, p90 to p915 and their alternate-function pins: i ol = 30 ma. 7. refer to i ol1 for i ol of p36 to p39, p614, and p615. 8. total of pcd0 to pcd3, pcm0 to pcm3, pcs0 to pcs7, pct0 to pct7 and their alternate-function pins:i ol = 30 ma, total of pdh0 to pdh7, pdl0 to pdl15 and their alternate-function pins: i ol = 30 ma. caution the following pins are not provided in the v850es/kf1. p10, p11, p36, p37, p60 to p615, p78 to p715, p80, p81, p92 to p95, p910 to p912, pcd0 to pcd3, pcm4, pcm5, pcs2 to pcs7, pct2, pct3, pct5, pct7, pdh0 to pdh7, av ref1 , bv dd , bv ss the following pins are not provided in the v850es/kg1. p60 to p615, p78 to p715, p80, p81, pcd0 to pcd3, pcm4, pcm5, pcs2 to pcs7, pct2, pct3, pct5, pct7, pdh6, pdh7 chapter 26 electrical specifications user ? s manual u15862ej3v0ud 709 dc characteristics (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v) (4/5) parameter symbol conditions min. typ. max. unit input leakage current, high i lih v in = v dd 3.0 a input leakage current, low i lil v in = 0 v ? 3.0 a output leakage current, high i loh v o = v dd 3.0 a output leakage current, low i lol v o = 0 v ? 3.0 a f xx = 20 mhz (osc = 5 mhz) (in pll mode) regc = v dd = 5 v 10% 43 60 ma f xx = 16 mhz (osc = 4 mhz) (in pll mode) regc = capacity v dd = 5 v 10% 27 40 ma i dd1 normal operation f xx = 10 mhz (osc = 10 mhz) regc = v dd = 3 v 10% 14 29 ma f xx = 20 mhz (osc = 5 mhz) (in pll mode) regc = v dd = 5 v 10% 18 28 ma f xx = 16 mhz (osc = 4 mhz) (in pll mode) regc = capacity v dd = 5 v 10% 11 20 ma i dd2 halt mode f xx = 10 mhz (osc = 10 mhz) regc = v dd = 3 v 10% 611ma osc = 5 mhz (when pll mode off) regc = v dd = 5 v 10% 1200 2000 a osc = 4 mhz (when pll mode off) regc = capacity v dd = 5 v 10% 900 1600 a i dd3 idle mode osc = 10 mhz (when pll mode off) regc = v dd = 3 v 10% 900 1600 a i dd4 subclock operating mode f xt = 32.768 khz 190 320 a i dd5 subclock idle mode f xt = 32.768 khz 15 60 a supply current note (flash memory version) i dd6 stop mode 0.1 30 a pull-up resistor r l v in = 0 v 10 30 100 k ? note total current of v dd , ev dd , and bv dd (all ports stopped). av ref0 is not included. chapter 26 electrical specifications user ? s manual u15862ej3v0ud 710 dc characteristics (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v) (5/5) parameter symbol conditions min. typ. max. unit f xx = 20 mhz (osc = 5 mhz) (in pll mode) regc = v dd = 5 v 10% 30 45 ma f xx = 16 mhz (osc = 4 mhz) (in pll mode) regc = capacity v dd = 5 v 10% 18 30 ma i dd1 normal operation f xx = 10 mhz (osc = 10 mhz) regc = v dd = 3 v 10% 918ma f xx = 20 mhz (osc = 5 mhz) (in pll mode) regc = v dd = 5 v 10% 17 25 ma f xx = 16 mhz (osc = 4 mhz) (in pll mode) regc = capacity v dd = 5 v 10% 10 18 ma i dd2 halt mode f xx = 10 mhz (osc = 10 mhz) regc = v dd = 3 v 10% 510ma osc = 5 mhz (when pll mode off) regc = v dd = 5 v 10% 900 1400 a osc = 4 mhz (when pll mode off) regc = capacity v dd = 5 v 10% 600 1000 a i dd3 idle mode osc = 10 mhz (when pll mode off) regc = v dd = 3 v 10% 600 1000 a i dd4 subclock operating mode f xt = 32.768 khz 70 160 a i dd5 subclock idlemode f xt = 32.768 khz 15 60 a supply current note (mask rom version) i dd6 stop mode 0.1 30 a pull-up resistance r l v in = 0 v 10 30 100 k ? note total current of v dd , ev dd , and bv dd (all ports stopped). av ref0 is not included. chapter 26 electrical specifications user ? s manual u15862ej3v0ud 711 data retention characteristics stop mode (t a = ? ? ? ? 40 to + + + + 85 c) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode 2.0 5.5 v stop release signal input time t drel 0 s caution shifting to stop mode and restoring from stop mode must be performed within the rated operating range. t drel stop release signal input stop mode setting v dddr v dd reset (input) stop mode release interrupt (nmi, etc.) (released by falling edge) stop mode release interrupt (nmi, etc.) (released by rising edge) operating voltage lower limit chapter 26 electrical specifications user ? s manual u15862ej3v0ud 712 ac characteristics ac test input measurement points (v dd , av dd , ev dd, b vdd ) ac test output measurement points load conditions v oh v ol v oh v ol measurement points dut (device under measurement) c l = 50 pf caution if the load capacitance exceeds 50 pf due to the circuit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means. v dd 0 v v ih v il v ih v il measurement points chapter 26 electrical specifications user ? s manual u15862ej3v0ud 713 clkout output timing (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit output cycle t cyk <1> 50 ns 30.6 s v dd = 4.0 to 5.5 v t cyk /2 ? 17 ns high-level width t wkh <2> v dd = 2.7 to 5.5 v t cyk /2 ? 26 ns v dd = 4.0 to 5.5 v t cyk /2 ? 17 ns low-level width t wkl <3> v dd = 2.7 to 5.5 v t cyk /2 ? 26 ns v dd = 4.0 to 5.5 v 17 ns rise time t kr <4> v dd = 2.7 to 5.5 v 26 ns v dd = 4.0 to 5.5 v 17 ns fall time t kf <5> v dd = 2.7 to 5.5 v 26 ns clock timing clkout (output) <1> <2> <3> <4> <5> chapter 26 electrical specifications user ? s manual u15862ej3v0ud 714 bus timing (1) in multiplex bus mode (a) clkout asynchronous: in multiplex bus mode (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, 4.0 v bv dd v dd , 4.0 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit address setup time (to astb )t sast <11> 0.5t ? 23 ns address hold time (from astb )t hsta <12> 0.5t ? 15 ns delay time from rd to address float t frda <13> 16 ns data input setup time from address t said <14> (2 + n)t ? 40 ns data input setup time from rd t srid <15> (1 + n)t ? 25 ns delay time from astb to rd, wrm t dstrdwr <16> 0.5t ? 20 ns data input hold time (from rd )t hrdid <17> 0 ns address output time from rd t drda <18> (1 + i)t ? 16 ns delay time from rd, wrm to astb t drdwrst <19> 0.5t ? 10 ns delay time from rd to astb t drdst <20> (1.5 + i)t ? 10 ns rd, wrm low-level width t wrdwrl <21> (1 + n)t ? 10 ns astb high-level width t wsth <22> t ? 25 ns data output time from wrm t dwrod <23> 20 ns data output setup time (to wrm )t sodwr <24> (1 + n)t ? 25 ns data output hold time (from wrm )t hwrod <25> t ? 15 ns t sawt1 <26> n 1 1.5t ? 45 ns wait setup time (to address) t sawt2 <27> (1.5 + n)t ? 45 ns t hawt1 <28> n 1 (0.5 + n)t ns wait hold time (from address) t hawt2 <29> (1.5 + n)t ns t sstwt1 <30> n 1t ? 32 ns wait setup time (to astb ) t sstwt2 <31> (1 + n)t ? 32 ns t hstwt1 <32> n 1nt ns wait hold time (from astb ) t hstwt2 <33> (1 + n)t ns hldrq high-level width t whqh <34> t + 10 ns hldak low-level width t whal <35> t ? 15 ns delay time from hldak to bus output t dhac <36> ? 40 ns delay time from hldrq to hldak t dhqha1 <37> (2n + 7.5)t + 40 ns delay time from hldrq to hldak t dhqha2 <38> 0.5t 1.5t + 40 ns remarks 1. t = 1/f cpu (f cpu : cpu operating clock frequency) 2. n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 3. m = 0, 1 4. i: number of idle states inserted after a read cycle (0 or 1). 5. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 26 electrical specifications user ? s manual u15862ej3v0ud 715 (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit address setup time (to astb )t sast <11> 0.5t ? 42 ns address hold time (from astb )t hsta <12> 0.5t ? 30 ns delay time from rd to address float t frda <13> 32 ns data input setup time from address t said <14> (2 + n)t ? 72 ns data input setup time from rd t srid <15> (1 + n)t ? 40 ns delay time from astb to rd, wrm t dstrdwr <16> 0.5t ? 35 ns data input hold time (from rd )t hrdid <17> 0 ns address output time from rd t drda <18> (1 + i)t ? 32 ns delay time from rd, wrm to astb t drdwrst <19> 0.5t ? 20 ns delay time from rd to astb t drdst <20> (1.5 + i)t ? 20 ns rd, wrm low-level width t wrdwrl <21> (1 + n)t ? 20 ns astb high-level width t wsth <22> t ? 50 ns data output time from wrm t dwrod <23> 35 ns data output setup time (to wrm )t sodwr <24> (1 + n)t ? 40 ns data output hold time (from wrm )t hwrod <25> t ? 30 ns t sawt1 <26> n 1 1.5t ? 80 ns wait setup time (to address) t sawt2 <27> (1.5 + n)t ? 80 ns t hawt1 <28> n 1 (0.5 + n)t ns wait hold time (from address) t hawt2 <29> (1.5 + n)t ns t sstwt1 <30> n 1t ? 60 ns wait setup time (to astb ) t sstwt2 <31> (1 + n)t ? 60 ns t hstwt1 <32> n 1nt ns wait hold time (from astb ) t hstwt2 <33> (1 + n)t ns hldrq high-level width t whqh <34> t + 10 ns hldak low-level width t whal <35> t ? 15 ns delay time from hldak to bus output t dhac <36> ? 80 ns delay time from hldrq to hldak t dhqha1 <37> (2n + 7.5)t + 70 ns delay time from hldrq to hldak t dhqha2 <38> 0.5t 1.5t + 70 ns caution set the following in accordance with the usage conditions of the cpu operation clock frequency (n = 0 to 3). ? 70 ns < 1/ f cpu < 84 ns set an address setup wait (aswn bit = 1). ? 62.5 ns < 1/ f cpu < 70 ns set an address setup wait (aswn bit = 1) and address hold wait (ahwn bit = 1). remarks 1. t = 1/f cpu (f cpu : cpu operating clock frequency) 2. n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 3. m = 0, 1 4. i: number of idle states inserted after a read cycle (0 or 1). 5. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 26 electrical specifications user ? s manual u15862ej3v0ud 716 (b) clkout synchronous: in multiplex bus mode (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, 4.0 v bv dd v dd , 4.0 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit delay time from clkout to address t dka <39> 0 19 ns delay time from clkout to address float t fka <40> 0 14 ns delay time from clkout to astb t dkst <41> 0 23 ns delay time from clkout to rd, wrm t dkrdwr <42> ? 22 0 ns data input setup time (to clkout )t sidk <43> 15 ns data input hold time (from clkout )t hkid <44> 0 ns data output delay time from clkout t dkod <45> 19 ns wait setup time (to clkout )t swtk <46> 15 ns wait hold time (from clkout )t hkwt <47> 0 ns hldrq setup time (to clkout )t shqk <48> 15 ns hldrq hold time (from clkout )t hkhq <49> 0 ns delay time from clkout to bus float t dkf <50> 20 ns delay time from clkout to hldak t dkha <51> 20 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit delay time from clkout to address t dka <39> 0 19 ns delay time from clkout to address float t fka <40> 0 18 ns delay time from clkout to astb t dkst <41> 0 55 ns delay time from clkout to rd, wrm t dkrdwr <42> ? 22 0 ns data input setup time (to clkout )t sidk <43> 30 ns data input hold time (from clkout )t hkid <44> 0 ns data output delay time from clkout t dkod <45> 19 ns wait setup time (to clkout )t swtk <46> 25 ns wait hold time (from clkout )t hkwt <47> 0 ns hldrq setup time (to clkout )t shqk <48> 25 ns hldrq hold time (from clkout )t hkhq <49> 0 ns delay time from clkout to bus float t dkf <50> 40 ns delay time from clkout to hldak t dkha <51> 40 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 26 electrical specifications user ? s manual u15862ej3v0ud 717 read cycle (clkout synchronous/asynchronous, 1 wait): in multiplex bus mode clkout (output) a16 to a23 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) t1 t2 tw t3 data address hi-z <39> <41> <11> <12> <42> <22> <40> <14> <41> <17> <19> <42> <15> <16> <30> <46> <32> <31> <33> <26> <28> <27> <29> <46> <47> <47> <21> <13> <18> <20> <43> <44> remark wr0 and wr1 are high level. chapter 26 electrical specifications user ? s manual u15862ej3v0ud 718 write cycle (clkout synchronous/asynchronous, 1 wait): in multiplex bus mode clkout (output) a16 to a23 (output) ad0 to ad15 (i/o) astb (output) wr0 (output), wr1 (output) wait (input) t1 t2 tw t3 data address <39> <41> <42> <42> <47> <47> <46> <46> <30> <32> <31> <33> <26> <28> <27> <29> <11> <12> <22> <19> <25> <24> <21> <16> <23> <41> <45> remarks rd is high level. chapter 26 electrical specifications user ? s manual u15862ej3v0ud 719 bus hold: in multiplex bus mode clkout (output) hldrq (input) hldak (output) a16 to a23 (output) ad0 to ad15 (i/o) astb (output) rd (output), wr0 (output), wr1 (output) th th th ti hi-z hi-z hi-z data hi-z <48> <48> <51> <51> <49> <34> <38> <35> <36> <37> <50> chapter 26 electrical specifications user ? s manual u15862ej3v0ud 720 (2) in separate bus mode (a) read cycle (clkout asynchronous): in separate bus mode (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, 4.0 v bv dd v dd , 4.0 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit address setup time (to rd )t sard <52> 0.5t ? 50 ns address hold time (from rd )t hard <53> ? 13 ns rd low-level width t wrdl <54> (1.5 + n )t ? 15 ns data setup time (to rd )t sisd <55> 30 ns data hold time (from rd )t hisd <56> 0 ns data setup time (to address) t said <57> (2 + n)t ? 65 ns t srdwt1 <58> 0.5t ? 32 ns wait setup time (to rd ) t srdwt2 <59> (0.5 + n )t ? 32 ns t hrdwt1 <60> 0.5t ns wait hold time (from rd ) t hrdwt2 <61> (0.5 + n)t ns t sawt1 <62> t ? 65 ns wait setup time (to address) t sawt2 <63> (1 + n)t ? 65 ns t hawt1 <64> t ns wait hold time (from address) t hawt2 <65> (1 + n)t ns cautions 1. the separate bus mode is not supported in the v850es/kf1. 2. set the following in accordance with the usage conditions of the cpu operation clock frequency (n = 0 to 3). ? 1/ f cpu < 100 ns set an address setup wait (aswn bit = 1). remarks 1 . t = 1/f cpu (f cpu : cpu operating clock frequency) 2. n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 3. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 26 electrical specifications user ? s manual u15862ej3v0ud 721 (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit address setup time (to rd )t sard <52> 0.5t ? 100 ns address hold time (from rd )t hard <53> ? 26 ns rd low-level width t wrdl <54> (1.5 + n )t ? 30 ns data setup time (to rd )t sisd <55> 60 ns data hold time (from rd )t hisd <56> 0 ns data setup time (to address) t said <57> (2 + n)t ? 120 ns t srdwt1 <58> 0.5t ? 50 ns wait setup time (to rd ) t srdwt2 <59> (0.5 + n )t ? 50 ns t hrdwt1 <60> 0.5t ns wait hold time (from rd ) t hrdwt2 <61> (0.5 + n)t ns t sawt1 <62> t ? 130 ns wait setup time (to address) t sawt2 <63> (1 + n)t ? 130 ns t hawt1 <64> t ns wait hold time (from address) t hawt2 <65> (1 + n)t ns cautions 1. the separate bus mode is not supported in the v850es/kf1. 2. set the following in accordance with the usage conditions of the cpu operation clock frequency (n = 0 to 3). ? 1/ f cpu < 200 ns set an address setup wait (aswn bit = 1). remarks 1. t = 1/f cpu (f cpu : cpu operating clock frequency) 2. n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 3. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 26 electrical specifications user ? s manual u15862ej3v0ud 722 (b) read cycle (clkout synchronous): in separate bus mode (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, 4.0 v bv dd v dd , 4.0 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit delay time from clkout to address, cs t dksa <66> 0 35 ns data input setup time (to clkout )t sisdk <67> 15 ns data input hold time (from clkout )t hkisd <68> 0 ns delay time from clkout to rd t dksr <69> 0 6 ns wait setup time (to clkout )t swtk <70> 20 ns wait hold time (from clkout )t hkwt <71> 0 ns caution the separate bus mode is not supported in the v850es/kf1. remark the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit delay time from clkout to address, cs t dksa <66> 0 65 ns data input setup time (to clkout )t sisdk <67> 30 ns data input hold time (from clkout )t hkisd <68> 0 ns delay time from clkout to rd t dksr <69> 0 10 ns wait setup time (to clkout )t swtk <70> 40 ns wait hold time (from clkout )t hkwt <71> 0 ns caution the separate bus mode is not supported in the v850es/kf1. remark the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 26 electrical specifications user ? s manual u15862ej3v0ud 723 (c) write cycle (clkout asynchronous): in separate bus mode (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, 4.0 v bv dd v dd , 4.0 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit address setup time (to wrm )t saw <72> t ? 60 ns address hold time (from wrm )t haw <73> 0.5t ? 10 ns wrm low-level width t wwrl <74> (0.5 + n )t ? 10 ns data output time from wrm t dosdw <75> ? 5ns data setup time (to wrm )t sosdw <76> (0.5 + n )t ? 20 ns data hold time (from wrm )t hosdw <77> 0.5t ? 20 ns data setup time (to address) t saod <78> t ? 30 ns t swrwt1 <79> 30 ns wait setup time (to wrm ) t swrwt2 <80> nt ? 30 ns t hwrwt1 <81> 0 ns wait hold time (from wrm ) t hwrwt2 <82> nt ns t sawt1 <83> t ? 45 ns wait setup time (to address) t sawt2 <84> (1 + n)t ? 45 ns t hawt1 <85> t ns wait hold time (from address) t hawt2 <86> (1 + n)t ns cautions 1. the separate bus mode is not supported in the v850es/kf1. 2. set the following in accordance with the usage conditions of the cpu operation clock frequency (n = 0 to 3). ? 1/ f cpu < 60 ns set an address setup wait (aswn bit = 1). remarks 1. m = 0, 1 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3 . n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 4. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 26 electrical specifications user ? s manual u15862ej3v0ud 724 (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit address setup time (to wrm )t saw <72> t ? 100 ns address hold time (from wrm )t haw <73> 0.5t ? 10 ns wrm low-level width t wwrl <74> (0.5 + n )t ? 10 ns data output time from wrm t dosdw <75> ? 5ns data setup time (to wrm )t sosdw <76> (0.5 + n )t ? 35 ns data hold time (from wrm )t hosdw <77> 0.5t ? 35 ns data setup time (to address) t saod <78> t ? 55 ns t swrwt1 <79> 50 ns wait setup time (to wrm ) t swrwt2 <80> nt ? 50 ns t hwrwt1 <81> 0 ns wait hold time (from wrm ) t hwrwt2 <82> nt ns t sawt1 <83> t ? 100 ns wait setup time (to address) t sawt2 <84> (1 + n)t ? 100 ns t hawt1 <85> t ns wait hold time (from address) t hawt2 <86> (1 + n)t ns cautions 1. the separate bus mode is not supported in the v850es/kf1. 2. set the following in accordance with the usage conditions of the cpu operation clock frequency (n = 0 to 3). ? 1/ f cpu < 100 ns set an address setup wait (aswn bit = 1). remarks 1. m = 0, 1 2. t = 1/f cpu (f cpu : cpu operating clock frequency) 3. n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 4. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 26 electrical specifications user ? s manual u15862ej3v0ud 725 (d) write cycle (clkout synchronous): in separate bus mode (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 4.0 to 5.5 v, 4.0 v bv dd v dd , 4.0 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (1/2) parameter symbol conditions min. max. unit delay time from clkout to address, cs t dksa <87> 0 35 ns data output delay time from clkout t dksd <88> 0 10 ns delay time from clkout to wrm t dksw <89> 0 10 ns wait setup time (to clkout )t swtk <90> 20 ns wait hold time (from clkout )t hkwt <91> 0 ns caution the separate bus mode is not supported in the v850es/kf1. remarks 1. m = 0, 1 2. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) (2/2) parameter symbol conditions min. max. unit delay time from clkout to address, cs t dksa <87> 0 65 ns data output delay time from clkout t dksd <88> 0 15 ns delay time from clkout to wrm t dksw <89> 0 15 ns wait setup time (to clkout )t swtk <90> 40 ns wait hold time (from clkout )t hkwt <91> 0 ns caution the separate bus mode is not supported in the v850es/kf1. remarks 1. m = 0, 1 2. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1. chapter 26 electrical specifications user ? s manual u15862ej3v0ud 726 read cycle (clkout asynchronous, 1 wait): in separate bus mode clkout (output) t1 <57> hi-z hi-z <52> <54> <61> <59> <60> <58> <62> <64> <63> <65> <56> <55> <53> tw t2 rd (output) cs0 to cs3 (output) a0 to a23 (output) ad0 to ad15 (i/o) wait (input) chapter 26 electrical specifications user ? s manual u15862ej3v0ud 727 read cycle (clkout synchronous, 1 wait): in separate bus mode clkout (output) t1 <69> <70> <71> <70> <71> <66> <69> <67> <68> hi-z hi-z tw t2 rd (output) cs0 to cs3 (output) a0 to a23 (output) ad0 to ad15 (i/o) wait (input) <66> chapter 26 electrical specifications user ? s manual u15862ej3v0ud 728 write cycle (clkout asynchronous, 1 wait): in separate bus mode clkout (output) t1 <78> <72> <75> <74> <82> <80> <81> <79> <83> <85> <84> <86> <77> <76> <73> tw t2 wr0, wr1 (output) cs0 to cs3 (output) a0 to a23 (output) ad0 to ad15 (i/o) wait (input) hi-z hi-z chapter 26 electrical specifications user ? s manual u15862ej3v0ud 729 write cycle (clkout synchronous, 1 wait): in separate bus mode clkout (output) t1 <88> <89> <91> <90> <89> tw t2 wr0, wr1 (output) cs0 to cs3 (output) a0 to a23 (output) ad0 to ad15 (i/o) wait (input) <87> <87> <91> <90> <88> hi-z hi-z chapter 26 electrical specifications user ? s manual u15862ej3v0ud 730 basic operation ( t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf ) parameter symbol conditions min. max. unit t wrsl1 <93> reset in power-on status 2 ns power-on-reset when regc = v dd 2 s reset low-level width t wrsl2 <94> power-on-reset when regc = capacity 10 s nmi high-level width t wnih <95> analog noise elimination 1 s nmi low-level width t wnil <96> analog noise elimination 1 s intpn high-level width t with <97> n = 0 to 6 ( analog noise elimination ) 1 s intpn low-level width t witl <98> n = 0 to 6 ( analog noise elimination ) 1 s remark t = 1/f xx reset interrupt <94> <93> v dd reset (input) nmi (input) intpn (input) <95> <96> <97> <98> remark n = 0 to 6 chapter 26 electrical specifications user ? s manual u15862ej3v0ud 731 timer timing ( t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf ) parameter symbol conditions min. max. unit ns ti0n high-level width t ti0h regc = v dd = 5 v 10% 2/fsam + 0.1 note ns ns ti0n low-level width t ti0l regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 2/fsam + 0.2 note ns ti50 high-level width t ti5h regc = v dd = 5 v 10% 50 ns ti51 low-level width t ti5l regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 100 ns note f sam = timer count clock however, f sam = f xx /4 when the ti0n valid edge is selected as the timer count clock. remark v850es/kf1: n = 00, 01, 10, 11 v850es/kg1: n = 00, 01, 10, 11, 20, 21, 30, 31 v850es/kj1: n = 00, 01, 10, 11, 20, 21, 30, 31, 40, 41, 50, 51 uart timing (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit transmit rate 31.25 kbps regc = v dd = 5 v 10% 12 mhz asck0 cycle time regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 6mhz chapter 26 electrical specifications user ? s manual u15862ej3v0ud 732 csi0 timing (1) master mode (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit regc = v dd = 4.0 to 5.5 v 200 ns sck0n cycle time t kcy1 <99> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 400 ns sck0n high-/low-level width t kh1 , t kl1 <100> t kcy1 /2 ? 30 ns regc = v dd = 4.0 to 5.5 v 30 ns si0n setup time (to sck0n )t sik1 <101> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 50 ns regc = v dd = 5 v 10% 30 ns si0n hold time (from sck0n )t ksi1 <102> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 50 ns regc = v dd = 4.0 to 5.5 v 30 ns delay time from sck0n to so0n output t kso1 <103> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) (2) slave mode (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit sck0n cycle time regc = v dd = 4.0 to 5.5 v 200 ns t kcy2 <99> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 400 ns regc = v dd = 4.0 to 5.5 v 45 ns sck0n high-/low-level width t kh2 , t kl2 <100> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 90 ns regc = v dd = 4.0 to 5.5 v 30 ns si0n setup time (to sck0n )t sik2 <101> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns regc = v dd = 4.0 to 5.5 v 30 ns si0n hold time (from sck0n )t ksi2 <102> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns regc = v dd = 4.0 to 5.5 v 50 ns delay time from sck0n to so0n output t kso2 <103> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 100 ns remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) chapter 26 electrical specifications user ? s manual u15862ej3v0ud 733 so0n (output) input data output data si0n (input) sck0n (i/o) <99> <100> <100> <101> <102> <103> hi-z hi-z remark n = 0, 1 (v850es/kf1, v850es/kg1), n = 0 to 2 (v850es/kj1) chapter 26 electrical specifications user ? s manual u15862ej3v0ud 734 csia timing (1) master mode (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit regc = v dd = 4.0 to 5.5 v 600 ns sckan cycle time t kcy3 <99> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 1000 ns sckan high-/low-level width t kh3 , t kl3 <100> t kcy3 /2 ? 30 ns regc = v dd = 4.0 to 5.5 v 30 ns sian setup time (to sckan )t sik3 <101> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns regc = v dd = 4.0 to 5.5 v 30 ns sian hold time (from sckan )t ksi3 <102> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns regc = v dd = 4.0 to 5.5 v 30 ns delay time from sckan to soan output t kso3 <103> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 60 ns remark n = 0 (v850es/kf1), n = 0, 1 (v850es/kg1, v850es/kj1) (2) slave mode (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit regc = v dd = 4.0 to 5.5 v 840 ns sckan cycle time t kcy4 <99> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 1700 ns sckan high-/low-level width t kh4 , t kl4 <100> t kcy4 /2 ? 30 ns regc = v dd = 4.0 to 5.5 v 50 ns sian setup time (to sckan )t sik4 <101> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 100 ns regc = v dd = 4.0 to 5.5 v 50 ns sian hold time (from sckan )t ksi4 <102> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v 100 ns regc = v dd = 4.0 to 5.5 v t cy 2 + 30 note ns delay time from sckan to soan output t kso4 <103> regc = capacity, v dd = 4.0 to 5.5 v, regc = v dd = 2.7 to 5.5 v t cy 2 + 60 note ns note t cy : internal clock output cycle f xx (cksan1 = 0, cksan0 = 0), f xx /2 (cksan1 = 0, cksan0 = 1) f xx /2 2 (cksan1 = 1, cksan0 = 0), f xx /2 3 (cksan1 = 1, cksan0 = 1) remark n = 0 (v850es/kf1), n = 0, 1 (v850es/kg1, v850es/kj1) chapter 26 electrical specifications user ? s manual u15862ej3v0ud 735 soan (output) input data output data sian (input) sckan (i/o) <99> <100> <100> <101> <102> <103> hi-z hi-z remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 26 electrical specifications user ? s manual u15862ej3v0ud 736 i 2 c bus mode (y products (products with on-chip i 2 c) only) (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v, c l = 50 pf) normal mode high-speed mode parameter symbol min. max. min. max. unit scln clock frequency f clk 0 100 0 400 khz bus free time (between start and stop conditions) t buf <104> 4.7 ? 1.3 ? s hold time note 1 t hd:sta <105> 4.0 ? 0.6 ? s scln clock low-level width t low <106> 4.7 ? 1.3 ? s scln clock high-level width t high <107> 4.0 ? 0.6 ? s setup time for start/restart conditions t su:sta <108> 4.7 ? 0.6 ? s cbus compatible master 5.0 ??? s data hold time i 2 c mode t hd:dat <109> 0 note 2 ? 0 note 2 0.9 note 3 s data setup time t su:dat <110> 250 ? 100 note 4 ? ns sdan and scln signal rise time t r <111> ? 1000 20 + 0.1cb note 5 300 ns sdan and scln signal fall time t f <112> ? 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto <113> 4.0 ? 0.6 ? s pulse width of spike suppressed by input filter t sp <114> ?? 050ns capacitance load of each bus line cb ? 400 ? 400 pf notes 1. at the start condition, the first clock pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time internally for the sdan signal (at v ihmin. of scln signal) in order to occupy the undefined area at the falling edge of scln. 3. if the system does not extend the scln signal low hold time (t low ), only the maximum data hold time (t hd : dat ) needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in the normal-mode i 2 c bus system. in this case, set the high- speed mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the scln signal ? s low state hold time: t su : dat 250 ns ? if the system extends the scln signal ? s low state hold time: transmit the following data bit to the sdan line prior to the scln line release (t rmax. + t su:dat = 1000 + 250 = 1250 ns: normal mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf) remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 26 electrical specifications user ? s manual u15862ej3v0ud 737 i 2 c bus mode (y products (products with on-chip i 2 c) only) stop condition start condition restart condition stop condition scln (i/o) sdan (i/o) <106> <112> <112> <111> <111> <109> <110> <108> <105> <104> <105> <114> <113> <107> remark n = 0 (v850es/kf1, v850es/kg1), n = 0, 1 (v850es/kj1) chapter 26 electrical specifications user ? s manual u15862ej3v0ud 738 a/d converter (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.0 av ref0 5.5 v 0.2 0.4 %fsr overall error note 1 2.7 av ref0 4.0 v 0.3 0.6 %fsr 4.0 av ref0 5.5 v 14 100 s conversion time t conv 2.7 av ref0 4.0 v 17 100 s 4.0 av ref0 5.5 v 0.4 %fsr zero-scale error note 1 2.7 av ref0 4.0 v 0.6 %fsr 4.0 av ref0 5.5 v 0.4 %fsr full-scale error note 1 2.7 av ref0 4.0 v 0.6 %fsr 4.0 av ref0 5.5 v 2.5 lsb non-linearity error note 2 2.7 av ref0 4.0 v 4.5 lsb 4.0 av ref0 5.5 v 1.5 lsb differential linearity error note 2 2.7 av ref0 4.0 v 2.0 lsb analog input voltage v ian 0av ref0 v when using a/d converter 1.0 2.0 ma av ref0 current ia ref0 when not using a/d converter 1.0 10 a notes 1. excluding quantization error ( 0.05%fsr). 2. excluding quantization error ( 0.5lsb). remark lsb: least significant bit fsr: full scale range d/a converter (v850es/kg1, v850es/kj1 only) (t a = ? ? ? ? 40 to + + + + 85 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8bit load condition = 2 m ? 1.2 %fsr load condition = 4 m ? 0.8 %fsr overall error notes 1, 2 load condition = 10 m ? 0.6 %fsr v dd = 4.5 to 5.5 v 10 s settling time notes 1, 2 c = 30 pf v dd = 2.7 to 4.5 v 15 s output resistance note 3 v o output data 55h 8 k ? during d/a conversion 1.5 3.0 ma av ref1 current note 4 iav ref1 when d/a conversion stopped 1.0 10 a notes 1. excluding quantization error ( 0.2%fsr). 2. r and c are the d/a converter output pin load resistance. 3. value of 1 channel of d/a converter 4. value of 2 channels of d/a converter chapter 26 electrical specifications user ? s manual u15862ej3v0ud 739 flash memory programming characteristics (t a = +10 to + + + + 40 c, v dd = ev dd = av ref0 = 2.7 to 5.5 v, 2.7 v bv dd v dd , 2.7 v av ref1 v dd , v ss = ev ss = bv ss = av ss = 0 v) (1) basic characteristics parameter symbol conditions min. typ. max. unit programming operation frequency 210mhz v pp supply voltage v pp2 during flash memory programming 9.7 10.0 10.3 v v dd supply current i dd when v pp = v pp2 , f xx = 10 mhz, v dd = 5.5 v 60 ma v pp supply current i pp when v pp = v pp2 100 ma step erase time t er note 1 0.196 0.2 0.204 s overall erase time t era when step erase time = 0.2 s, note 2 20 s/area writeback time t wb note 3 4.9 5.0 5.1 ms number of writebacks c wb when writeback time = 1 ms, note 4 100 times number of erases/writebacks c erwb 16 times step write time t wr note 5 49 50 51 s overall write time per word t wrw when step write time = 50 s (1 word = 4 byte), note 6 49 510 s/word number of rewrites per area c erwr 1 erase + 1 write after erase = 1 rewrite, note 7 20 count/area notes 1. the recommended setting value of the step erase time is 0.2 s. 2. the prewrite time prior to erasure and the erase verify time (writeback time) are not included. 3. the recommended setting value of the writeback time is 5.0 ms. 4. writeback is executed once by the issuance of the writeback command. therefore, the retry count must be the maximum value minus the number of commands issued. 5. the recommended setting value of the step writing time is 50 s. 6. 100 s is added to the actual writing time per word. the internal verify time during and after the writing is not included. 7. when writing initially to shipped products, it is counted as one rewrite for both ? erase to write ? and ? write only ? . example (p: write, e: erase) shipped product p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites chapter 26 electrical specifications user ? s manual u15862ej3v0ud 740 (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit setup time from v dd to v pp t dprsr 15 s setup time from v pp to reset t psrrf 10 s count start time from reset to v pph t rfof 2 s count complete time t count 20 ms v pp counter high-/low-level width t ch /t cl 8 s v pp pulse low-level input voltage v ppl 0.8v dd 1.2v dd v v pp pulse high-level input voltage v pph 9.7 10.0 10.3 v flash write mode setting timing v dd v dd 0 v ev dd reset (input) 0 v v pph v ppl v pp v dd t rfcf t psrrf t drpsr t ch t cl t count user?s manual u15862ej3v0ud 741 chapter 27 package drawings 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 ? 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 ? 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h chapter 27 package drawings user ? s manual u15862ej3v0ud 742 80-pin plastic tqfp (fine pitch) (12x12) item millimeters g h 0.22 0.05 1.25 a 14.0 0.2 c 12.0 0.2 d f 1.25 14.0 0.2 b 12.0 0.2 m n 0.08 0.145 0.05 p q 0.1 0.05 1.0 j 0.5 (t.p.) k l 0.5 1.0 0.2 i 0.08 s 1.1 0.1 r 3 + 4 ? 3 r h k l j f q g i t u s p detail of lead end note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. 60 41 40 21 61 80 120 m s s cd a b n m p80gk-50-9eu-1 t 0.25 u 0.6 0.15 chapter 27 package drawings user ? s manual u15862ej3v0ud 743 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.00 0.20 14.00 0.20 0.50 (t.p.) 1.00 j 16.00 0.20 k c 14.00 0.20 i 0.08 1.00 0.20 l 0.50 0.20 f 1.00 n p q 0.08 1.40 0.05 0.10 0.05 s100gc-50-8eu, 8ea-2 s 1.60 max. h 0.22 + 0.05 ? 0.04 m 0.17 + 0.03 ? 0.07 r3 + 7 ? 3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h chapter 27 package drawings user ? s manual u15862ej3v0ud 744 108 73 136 109 144 72 37 144-pin plastic lqfp (fine pitch) (20x20) item millimeters note a 22.0 0.2 b 20.0 0.2 c 20.0 0.2 d f 1.25 22.0 0.2 s144gj-50-uen s 1.5 0.1 k 1.0 0.2 l 0.5 0.2 r3 + 4 ? 3 g 1.25 h 0.22 0.05 i 0.08 j 0.5 (t.p.) m 0.17 n 0.08 p 1.4 q 0.10 0.05 + 0.03 ? 0.07 each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. s s m detail of lead end i j f g h q r p k m l n cd s a b user?s manual u15862ej3v0ud 745 chapter 28 recommended soldering conditions the v850es/kf1, v850es/kg1, and v850es/kj1 should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. table 28-1. surface mounting type soldering conditions (1/3) (1) pd703208gk-xxx-9eu: 80-pin plastic tqfp (fine pitch) (12 12) pd703208ygk-xxx-9eu: 80-pin plastic tqfp (fine pitch) (12 12) pd703209gk-xxx-9eu: 80-pin plastic tqfp (fine pitch) (12 12) pd703209ygk-xxx-9eu: 80-pin plastic tqfp (fine pitch) (12 12) pd703210gk-xxx-9eu: 80-pin plastic tqfp (fine pitch) (12 12) pd703210ygk-xxx-9eu: 80-pin plastic tqfp (fine pitch) (12 12) pd70f3210gk-9eu: 80-pin plastic tqfp (fine pitch) (12 12) pd70f3210ygk-9eu: 80-pin plastic tqfp (fine pitch) (12 12) pd703212gc-xxx-8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd703212ygc-xxx-8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd703213gc-xxx-8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd703213ygc-xxx-8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd703214gc-xxx-8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd703214ygc-xxx-8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3214gc-8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3214ygc-8eu: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125c for 10 to 72 hours) ir35-107-2 vps package peak temperature: 215c, time: 25 to 40 seconds (at 200c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125c for 10 to 72 hours) vp15-107-2 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). chapter 28 recommended soldering conditions user?s manual u15862ej3v0ud 746 table 28-1. surface mounting type soldering conditions (2/3) (2) pd703208gc-xxx-8bt: 80-pin plastic qfp (14 14) pd703208ygc-xxx-8bt: 80-pin plastic qfp (14 14) pd703209gc-xxx-8bt: 80-pin plastic qfp (14 14) pd703209ygc-xxx-8bt: 80-pin plastic qfp (14 14) pd703210gc-xxx-8bt: 80-pin plastic qfp (14 14) pd703210ygc-xxx-8bt: 80-pin plastic qfp (14 14) pd70f3210gc-8bt: 80-pin plastic qfp (14 14) pd70f3210ygc-8bt: 80-pin plastic qfp (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125c for 10 to 72 hours) ir35-107-2 vps package peak temperature: 215c, time: 25 to 40 seconds (at 200c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125c for 10 to 72 hours) vp15-107-2 wave soldering solder bath temperature: 260c max., time: 10 seconds max., count: once, preheating temperature: 120c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125c for 10 hours) ws60-107-1 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). chapter 28 recommended soldering conditions user?s manual u15862ej3v0ud 747 table 28-1. surface mounting type soldering conditions (3/3) (3) pd703216gj-xxx-uen: 144-pin plastic lqfp (fine pitch) (20 20) pd703216ygj-xxx-uen: 144-pin plastic lqfp (fine pitch) (20 20) pd703217gj-xxx-uen: 144-pin plastic lqfp (fine pitch) (20 20) pd703217ygj-xxx-uen: 144-pin plastic lqfp (fine pitch) (20 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125c for 10 to 72 hours) ir35-103-2 vps package peak temperature: 215c, time: 25 to 40 seconds (at 200c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125c for 10 to 72 hours) vp15-103-2 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). (4) pd70f3217gj- uen: 144-pin plastic lqfp (fine pitch) (20 20) pd70f3217ygj-uen: 144-pin plastic lqfp (fine pitch) (20 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125c for 36 hours) ir35-363-2 vps package peak temperature: 215c, time: 40 seconds max. (at 200c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125c for 36 hours) vp15-363-2 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). user?s manual u15862ej3v0ud 748 appendix a register index (1/7) symbol name unit page adcr a/d conversion result register adc 421 adic interrupt control register intc 629 adm a/d converter mode register adc 423 ads analog input channel specification register adc 425 adtc0 automatic data transfer address count register 0 csi 504 adtc1 automatic data transfer address count register 1 csi 504 adti0 automatic data transfer interval specification register 0 csi 510, 527 adti1 automatic data transfer interval specification register 1 csi 510, 527 adtp0 automatic data transfer address point specification register 0 csi 508, 525 adtp1 automatic data transfer address point specification register 1 csi 508, 525 asif0 asynchronous serial interface transmission status register 0 uart 449 asif1 asynchronous serial interface transmission status register 1 uart 449 asif2 asynchronous serial interface transmission status register 2 uart 449 asim0 asynchronous serial interface mode register 0 uart 445 asim1 asynchronous serial interface mode register 1 uart 445 asim2 asynchronous serial interface mode register 2 uart 445 asis0 asynchronous serial interface status register 0 uart 448 asis1 asynchronous serial interface status register 1 uart 448 asis2 asynchronous serial interface status register 2 uart 448 awc address wait control register bcu 280 bcc bus cycle control register bcu 281 brgc0 baud rate generator control register 0 brg 467 brgc1 baud rate generator control register 1 brg 467 brgc2 baud rate generator control register 2 brg 467 brgca0 divisor selection register 0 uart 508, 516, 525 brgca1 divisor selection register 1 uart 508, 516, 525 brgic interrupt control register bcu 629 bsc bus size configuration register bcu 270 cksr0 clock selection register 0 uart 466 cksr1 clock selection register 1 uart 466 cksr2 clock selection register 2 uart 466 cmp00 8-bit timer h compare register 00 timer 371 cmp01 8-bit timer h compare register 01 timer 371 cmp10 8-bit timer h compare register 10 timer 371 cmp11 8-bit timer h compare register 11 timer 371 corad0 correction address register 0 romc 678 corad1 correction address register 1 romc 678 corad2 correction address register 2 romc 678 corad3 correction address register 3 romc 678 appendix a register index user?s manual u15862ej3v0ud 749 (2/7) symbol name unit page corcn correction control register romc 679 cr000 16-bit timer capture/compare register 000 timer 305 cr001 16-bit timer capture/compare register 001 timer 307 cr010 16-bit timer capture/compare register 010 timer 305 cr011 16-bit timer capture/compare register 011 timer 307 cr020 16-bit timer capture/compare register 020 timer 305 cr021 16-bit timer capture/compare register 021 timer 307 cr030 16-bit timer capture/compare register 030 timer 305 cr031 16-bit timer capture/compare register 031 timer 307 cr040 16-bit timer capture/compare register 040 timer 305 cr041 16-bit timer capture/compare register 041 timer 307 cr050 16-bit timer capture/compare register 050 timer 305 cr051 16-bit timer capture/compare register 051 timer 307 cr5 16-bit timer compare register 5 timer 352 cr50 8-bit timer compare register 50 timer 352 cr51 8-bit timer compare register 51 timer 352 crc00 capture/compare control register 00 timer 310 crc01 capture/compare control register 01 timer 310 crc02 capture/compare control register 02 timer 310 crc03 capture/compare control register 03 timer 310 crc04 capture/compare control register 04 timer 310 crc05 capture/compare control register 05 timer 310 csi0ic0 interrupt control register intc 629 csi0ic1 interrupt control register intc 629 csi0ic2 interrupt control register intc 629 csia0bn csia0 buffer ramn (n = 0 to f) csi 510 csia1bn csia1 buffer ramn (n = 0 to f) csi 510 csiaic0 interrupt control register intc 629 csiaic1 interrupt control register intc 629 csic0 clocked serial interface clock selection register 0 csi 479 csic1 clocked serial interface clock selection register 1 csi 479 csic2 clocked serial interface clock selection register 2 csi 479 csim00 clocked serial interface mode register 00 csi 477 csim01 clocked serial interface mode register 01 csi 477 csim02 clocked serial interface mode register 02 csi 477 csima0 serial operation mode specification register 0 csi 505, 514, 522 csima1 serial operation mode specification register 1 csi 505, 514, 522 csis0 serial status register 0 csi 506, 515, 523 csis1 serial status register 1 csi 506, 515, 523 csit0 serial trigger register 0 csi 507, 524 csit1 serial trigger register 1 csi 507, 524 dacs0 d/a conversion value setting register 0 dac 438 dacs1 d/a conversion value setting register 1 dac 438 dam d/a converter mode register dac 437 appendix a register index user?s manual u15862ej3v0ud 750 (3/7) symbol name unit page dwc0 data wait control register 0 bcu 277 eximc external bus interface mode control register bcu 269 iic0 iic shift register 0 i 2 c 562 iic1 iic shift register 1 i 2 c 562 iicc0 iic control register 0 i 2 c 550 iicc1 iic control register 1 i 2 c 550 iiccl0 iic clock selection register 0 i 2 c 560 iiccl1 iic clock selection register 1 i 2 c 560 iicf0 iic flag register 0 i 2 c 558 iicf1 iic flag register 1 i 2 c 558 iicic0 interrupt control register intc 629 iicic1 interrupt control register intc 629 iics0 iic status register 0 i 2 c 555 iics1 iic status register 1 i 2 c 555 iicx0 iic function expansion register 0 i 2 c 561 iicx1 iic function expansion register 1 i 2 c 561 imr0 interrupt mask register 0 intc 634 imr1 interrupt mask register 1 intc 634 imr2 interrupt mask register 2 intc 634 intf0 external interrupt falling edge specification register 0 intc 145, 620 intf9h external interrupt falling edge specification register 9h intc 216, 641 intr0 external interrupt rising edge specification register 0 intc 146, 620 intr9h external interrupt rising edge specification register 9h intc 216, 641 ispr in-service priority register intc 637 kric interrupt control register intc 629 krm key return mode register kr 655 osts oscillation stabilization time selection register wdt 298, 410 p0 port 0 register port 143 p1 port 1 register port 150 p3 port 3 register port 155 p4 port 4 register port 166 p5 port 5 register port 173 p6 port 6 register port 183 p7 port 7 register port 196 p8 port 8 register port 199 p9 port 9 register port 206 pcc processor clock control register cg 295 pcd port cd register port 224 pcm port cm register port 228 pcs port cs register port 235 pct port ct register port 241 pdh port dh register port 247 pdl port dl register port 252 pf3h port 3 function register h port 158 appendix a register index user?s manual u15862ej3v0ud 751 (4/7) symbol name unit page pf4 port 4 function register port 167 pf5 port 5 function register port 175 pf6 port 6 function register port 186 pf8 port 8 function register port 200 pf9h port 9 function register h port 211 pfc3 port 3 function control register port 158 pfc5 port 5 function control register port 176 pfc6h port 6 function control register h port 186 pfc8 port 8 function control register port 201 pfc9 port 9 function control register port 211 pfm power-fail comparison mode register adc 426 pft power-fail comparison threshold value register adc 421 pic0 interrupt control register intc 629 pic1 interrupt control register intc 629 pic2 interrupt control register intc 629 pic3 interrupt control register intc 629 pic4 interrupt control register intc 629 pic5 interrupt control register intc 629 pic6 interrupt control register intc 629 pllctl pll control register cg 300, 399 pm0 port 0 mode register port 143 pm1 port 1 mode register port 150 pm3 port 3 mode register port 156 pm4 port 4 mode register port 166 pm5 port 5 mode register port 173 pm6 port 6 mode register port 184 pm8 port 8 mode register port 199 pm9 port 9 mode register port 207 pmc0 port 0 mode control register port 144 pmc3 port 3 mode control register port 157 pmc4 port 4 mode control register port 167 pmc5 port 5 mode control register port 174 pmc6 port 6 mode control register port 185 pmc8 port 8 mode control register port 200 pmc9 port 9 mode control register port 207 pmccm port cm mode control register port 230 pmccs port cs mode control register port 237 pmcct port ct mode control register port 243 pmcdh port dh mode control register port 249 pmcdl port dl mode control register port 253 pmcd port cd mode register port 225 pmcm port cm mode register port 229 pmcs port cs mode register port 236 pmct port ct mode register port 242 appendix a register index user?s manual u15862ej3v0ud 752 (5/7) symbol name unit page pmdh port dh mode register port 248 pmdl port dl mode register port 253 prcmd command register cpu 132 prm00 prescaler mode register 00 timer 313 prm01 prescaler mode register 01 timer 314 prm02 prescaler mode register 02 timer 315 prm03 prescaler mode register 03 timer 316 prm04 prescaler mode register 04 timer 317 prm05 prescaler mode register 05 timer 318 prscm prescaler compare register timer 407 prsm prescaler mode register cg 406 psc power save control register cg 297 psmr power save mode register cg 298 pu0 pull-up resistor option register 0 port 145 pu1 pull-up resistor option register 1 port 151 pu3 pull-up resistor option register 3 port 159 pu4 pull-up resistor option register 4 port 168 pu5 pull-up resistor option register 5 port 177 pu6 pull-up resistor option register 6 port 187 pu8 pull-up resistor option register 8 port 201 pu9 pull-up resistor option register 9 port 215 rtbh0 real-time output buffer register h0 rtp 393 rtbh1 real-time output buffer register h1 rtp 393 rtbl0 real-time output buffer register l0 rtp 393 rtbl1 real-time output buffer register l1 rtp 393 rtpc0 real-time output port control register 0 rtp 395 rtpc1 real-time output port control register 1 rtp 395 rtpm0 real-time output port mode register 0 rtp 394 rtpm1 real-time output port mode register 1 rtp 394 rxb0 receive buffer register 0 uart 450 rxb1 receive buffer register 1 uart 450 rxb2 receive buffer register 2 uart 450 sioa0 serial i/o shift register a0 csi 504 sioa1 serial i/o shift register a1 csi 504 sirb0 clocked serial interface receive buffer register 0 csi 480 sirb0l clocked serial interface receive buffer register 0l csi 480 sirb1 clocked serial interface receive buffer register 1 csi 480 sirb1l clocked serial interface receive buffer register 1l csi 480 sirb2 clocked serial interface receive buffer register 2 csi 480 sirb2l clocked serial interface receive buffer register 2l csi 480 sirbe0 clocked serial interface read-only receive buffer register 0 csi 481 sirbe0l clocked serial interface read-only receive buffer register 0l csi 481 sirbe1 clocked serial interface read-only receive buffer register 1 csi 481 sirbe1l clocked serial interface read-only receive buffer register 1l csi 481 appendix a register index user?s manual u15862ej3v0ud 753 (6/7) symbol name unit page sirbe2 clocked serial interface read-only receive buffer register 2 csi 481 sirbe2l clocked serial interface read-only receive buffer register 2l csi 481 sotb0 clocked serial interface transmit buffer register 0 csi 482 sotb0l clocked serial interface transmit buffer register 0l csi 482 sotb1 clocked serial interface transmit buffer register 1 csi 482 sotb1l clocked serial interface transmit buffer register 1l csi 482 sotb2 clocked serial interface transmit buffer register 2 csi 482 sotb2l clocked serial interface transmit buffer register 2l csi 482 sotbf0 clocked serial interface first stage transmit buffer register 0 csi 483 sotbf0l clocked serial interface first stage transmit buffer register 0l csi 483 sotbf1 clocked serial interface first stage transmit buffer register 1 csi 483 sotbf1l clocked serial interface first stage transmit buffer register 1l csi 483 sotbf2 clocked serial interface first stage transmit buffer register 2 csi 483 sotbf2l clocked serial interface first stage transmit buffer register 2l csi 483 sreic0 interrupt control register intc 629 sreic1 interrupt control register intc 629 sreic2 interrupt control register intc 629 sric0 interrupt control register intc 629 sric1 interrupt control register intc 629 sric2 interrupt control register intc 629 stic0 interrupt control register intc 629 stic1 interrupt control register intc 629 stic2 interrupt control register intc 629 sva1 slave address register 1 i 2 c 562 sva0 slave address register 0 i 2 c 562 sys system status register cpu 132 tcl5 timer clock selection register 5 timer 351 tcl50 timer clock selection register 50 timer 353 tcl51 timer clock selection register 51 timer 353 tm00 16-bit timer counter 00 timer 304 tm01 16-bit timer counter 01 timer 304 tm02 16-bit timer counter 02 timer 304 tm03 16-bit timer counter 03 timer 304 tm04 16-bit timer counter 04 timer 304 tm05 16-bit timer counter 05 timer 304 tm0ic00 interrupt control register intc 629 tm0ic01 interrupt control register intc 629 tm0ic10 interrupt control register intc 629 tm0ic11 interrupt control register intc 629 tm0ic20 interrupt control register intc 629 tm0ic21 interrupt control register intc 629 tm0ic30 interrupt control register intc 629 tm0ic31 interrupt control register intc 629 tm0ic40 interrupt control register intc 629 appendix a register index user?s manual u15862ej3v0ud 754 (7/7) symbol name unit page tm0ic41 interrupt control register intc 629 tm0ic50 interrupt control register intc 629 tm0ic51 interrupt control register intc 629 tm5 16-bit timer counter 5 timer 351 tm50 8-bit timer counter 50 timer 352 tm51 8-bit timer counter 51 timer 352 tm5ic0 interrupt control register intc 629 tm5ic1 interrupt control register intc 629 tmc00 16-bit timer mode control register 00 timer 308 tmc01 16-bit timer mode control register 01 timer 308 tmc02 16-bit timer mode control register 02 timer 308 tmc03 16-bit timer mode control register 03 timer 308 tmc04 16-bit timer mode control register 04 timer 308 tmc05 16-bit timer mode control register 05 timer 308 tmc5 16-bit timer mode control register 5 timer 351 tmc50 8-bit timer mode control register 50 timer 354 tmc51 8-bit timer mode control register 51 timer 354 tmcyc0 8-bit timer h carrier control register 0 timer 375 tmcyc1 8-bit timer h carrier control register 1 timer 375 tmhic0 interrupt control register intc 629 tmhic1 interrupt control register intc 629 tmhmd0 8-bit timer h mode register 0 timer 372 tmhmd1 8-bit timer h mode register 1 timer 372 toc00 16-bit timer output control register 00 timer 310 toc01 16-bit timer output control register 01 timer 310 toc02 16-bit timer output control register 02 timer 310 toc03 16-bit timer output control register 03 timer 310 toc04 16-bit timer output control register 04 timer 310 toc05 16-bit timer output control register 05 timer 310 txb0 transmit buffer register 0 uart 451 txb1 transmit buffer register 1 uart 451 txb2 transmit buffer register 2 uart 451 vswc system wait control register cpu 134 wdcs watchdog timer clock selection register wdt 411 wdt1ic interrupt control register intc 629 wdte watchdog timer enable register wdt 418 wdtm1 watchdog timer mode register 1 wdt 412, 639 wdtm2 watchdog timer mode register 2 wdt 417, 639 wtic interrupt control register intc 629 wtiic interrupt control register intc 629 wtm watch timer operation mode register wt 402 user?s manual u15862ej3v0ud 755 appendix b revision history the following table shows the revision history up to this edition. the ?applied to:? column indicates the chapters of each edition in which the revision was applied. (1/3) edition major revision from previous edition applied to: change of description in figure 12-1 block diagram of d/a converter chapter 12 d/a converter addition of caution in 14.3.4 interrupt control register (xxicn) addition of caution in 14.3.6 in-service priority register (ispr) chapter 14 interrupt/exception processing function addition of chapter 21 electrical specifications (target values) chapter 21 electrical specifications (target values) addition of chapter 22 package drawings chapter 22 package drawings 2nd addition of appendix a register index appendix a register index ? addition of the following special quality grade products. pd703208(a), 703208y(a), 703209(a), 703209y(a), 703210(a), 703210y(a), 703212(a), 703212y(a), 703213(a), 703213y(a), 703214(a), 703214y(a), 703216(a), 703216y(a), 703217(a), 703217y(a), 70f3210(a), 70f3210y(a), 70f3214(a), 70f3214y(a), 70f3217(a), 70f3217y(a) throughout addition of caution in 1.2.4 pin configuration (top view) (v850es/kf1) addition of caution in 1.3.4 pin configuration (top view) (v850es/kg1) addition of caution in 1.4.4 pin configuration (top view) (v850es/kj1) chapter 1 introduction addition of description in chapter 2 pin functions and addition of table 2-1 pin i/o buffer power supplies modification of description on recommended connection of p70 to p77, p78 to p715, ic, v pp , and xt1 in 2.4 pin i/o circuits and recommended connection of unused pins chapter 2 pin functions modification of description in 3.4.8 (2) access to special on-chip peripheral i/o registers chapter 3 cpu functions modification of description in 5.11 bus timing addition of 5.12 cautions chapter 5 bus control function addition of description on the main clock oscillator in 6.1 overview addition of description in 6.2 (1) main clock oscillator addition of caution 3 in 6.3 (1) processor clock control register (pcc) chapter 6 clock generation function addition of description in chapter 7 16-bit timer/event counters 00 to 05 modification of description of caution 4 in 7.2 (2) 16-bit timer capture/compare register 0n0 (cr0n0) modification of description of caution 4 in 7.2 (3) 16-bit timer capture/compare register 0n1 (cr0n1) modification of description of caution 1 in 7.3 (3) 16-bit timer output control register 0n (toc0n) 3rd addition of setting procedures and modification of description in 7.4.1 operation as interval timer (16 bits) chapter 7 16-bit timer/event counters 00 to 05 appendix b revision history user?s manual u15862ej3v0ud 756 (2/3) edition major revision from previous edition applied to: addition of setting procedures in 7.4.2 ppg output operation addition of figure 7-6 configuration of ppg output addition of figure 7-7 ppg output operation timing addition of setting procedures in 7.4.3 pulse width measurement addition of setting procedures and addition of caution 2 in 7.4.4 operation as external event counter addition of setting procedures and addition of caution in 7.4.5 square-wave output operation addition of setting procedures in 7.4.6 one-shot pulse output operation addition of caution 2 in 7.4.6 (1) one-shot pulse output with software trigger (16-bit timer/event counters 00, 01, 04 and 05 only) addition of caution 2 in 7.4.6 (2) one-shot pulse output with external trigger (16-bit timer/event counters 04 and 05 only) addition of caution in 7.4.7 (10) (b) when setting cr0n0, cr0n1 to compare mode chapter 7 16-bit timer/event counters 00 to 05 addition of description in chapter 8 8-bit timer/event counters 50 and 51 chapter 8 8-bit timer/event counters 50 and 51 addition of description in chapter 9 8-bit timers h0 and h1 addition of caution 3 in 9.3 (1) (a) 8-bit timer h mode register 0 (tmhmd0) addition of caution 3 in 9.3 (1) (b) 8-bit timer h mode register 1 (tmhmd1) addition of caution 2 in figure 9-7 transfer timing addition of caution 4 in 9.4.3 (4) timing chart chapter 9 8-bit timers h0 and h1 addition of 13.4 relationship between analog input voltage and a/d conversion result addition of 13.6 (3) a/d converter sampling time and a/d conversion start delay time addition of 13.7 how to read a/d converter characteristics table chapter 13 a/d converter addition of description in chapter 15 asynchronous serial interface (uart) modification of description in figure 15-6 continuous transmission starting procedure chapter 15 asynchronous serial interface (uart) addition of description in chapter 16 clocked serial interface 0 (csi0) chapter 16 clocked serial interface 0 (csi0) modification of description in chapter 17 clocked serial interface a (csia) with automatic transmit/receive function chapter 17 clocked serial interface a (csia) with automatic transmit/receive function addition of description in chapter 18 i 2 c bus chapter 18 i 2 c bus addition to cautions in table 25-1 wiring between pd70f3210 and 70f3210y (v850es/kf1), and pg-fp3 addition of figure 25-1 wiring example of v850es/kf1 flash writing adapter (fa- 80gc-8bt, fa-80gk-9eu) 3rd addition of cautions in table 25-2 wiring between pd70f3214 and 70f3214y (v850es/kg1), and pg-fp3 chapter 25 flash memory appendix b revision history user?s manual u15862ej3v0ud 757 (3/3) edition major revision from previous edition applied to: addition of figure 25-2 wiring example of v850es/kg1 flash writing adapter (fa- 100gc-8eu) addition of cautions in table 25-3 wiring between pd70f3217 and 70f3217y (v850es/kj1), and pg-fp3 addition of figure 25-3 wiring example of v850es/kj1 flash writing adapter (fa- 144gj-uen) chapter 25 flash memory addition of note 1 and description in absolute maximum ratings in chapter 26 electrical specifications addition of description on storage temperature in absolute maximum ratings in chapter 26 electrical specifications addition of (i) murata manufacturing co., ltd.: ceramic resonator (t a = ? ? ? ? 40 to +85 c) in chapter 26 electrical specifications change of values of supply current (flash memory version) in dc characteristics in chapter 26 electrical specifications change of values of supply current (mask rom version) in dc characteristics in chapter 26 electrical specifications addition of caution and a timing chart in data retention characteristics in chapter 26 electrical specifications addition of caution in bus timing (1) (a) clkout asynchronous: in multiplex bus mode (2/2) in chapter 26 electrical specifications addition of caution 2 in bus timing (2) (a) read cycle (clkout asynchronous): in separate bus mode (1/2) in chapter 26 electrical specifications addition of cautions in bus timing (2) (a) read cycle (clkout asynchronous): in separate bus mode (2/2) in chapter 26 electrical specifications addition of caution 2 in bus timing (2) (c) write cycle (clkout asynchronous): in separate bus mode (1/2) in chapter 26 electrical specifications addition of cautions in bus timing (2) (c) write cycle (clkout asynchronous): in separate bus mode (2/2) in chapter 26 electrical specifications addition of description in basic operation in chapter 26 electrical specifications addition of description in flash memory programming characteristics in chapter 26 electrical specifications chapter 26 electrical specifications addition of chapter 28 recommended soldering conditions chapter 28 recommended soldering conditions 3rd addition of appendix b revision history appendix b revision history |
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